1 files changed, 118 insertions, 199 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index b948d6cb1399..44547f951d92 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -46,6 +46,16 @@ static const u32 crtc_offsets[6] =
         SI_CRTC5_REGISTER_OFFSET
 };
 
+static const u32 hpd_offsets[] =
+{
+        DC_HPD1_INT_STATUS - DC_HPD1_INT_STATUS,
+        DC_HPD2_INT_STATUS - DC_HPD1_INT_STATUS,
+        DC_HPD3_INT_STATUS - DC_HPD1_INT_STATUS,
+        DC_HPD4_INT_STATUS - DC_HPD1_INT_STATUS,
+        DC_HPD5_INT_STATUS - DC_HPD1_INT_STATUS,
+        DC_HPD6_INT_STATUS - DC_HPD1_INT_STATUS,
+};
+
 static const uint32_t dig_offsets[] = {
         SI_CRTC0_REGISTER_OFFSET,
         SI_CRTC1_REGISTER_OFFSET,
@@ -94,15 +104,6 @@ static const struct {
         .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
 } };
 
-static const uint32_t hpd_int_control_offsets[6] = {
-        DC_HPD1_INT_CONTROL,
-        DC_HPD2_INT_CONTROL,
-        DC_HPD3_INT_CONTROL,
-        DC_HPD4_INT_CONTROL,
-        DC_HPD5_INT_CONTROL,
-        DC_HPD6_INT_CONTROL,
-};
-
 static u32 dce_v6_0_audio_endpt_rreg(struct amdgpu_device *adev,
                                      u32 block_offset, u32 reg)
 {
@@ -257,34 +258,11 @@ static bool dce_v6_0_hpd_sense(struct amdgpu_device *adev,
 {
         bool connected = false;
 
-        switch (hpd) {
-        case AMDGPU_HPD_1:
-                if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
-                        connected = true;
-                break;
-        case AMDGPU_HPD_2:
-                if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
-                        connected = true;
-                break;
-        case AMDGPU_HPD_3:
-                if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
-                        connected = true;
-                break;
-        case AMDGPU_HPD_4:
-                if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
-                        connected = true;
-                break;
-        case AMDGPU_HPD_5:
-                if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
-                        connected = true;
-                break;
-        case AMDGPU_HPD_6:
-                if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
-                        connected = true;
-                break;
-        default:
-                break;
-        }
+        if (hpd >= adev->mode_info.num_hpd)
+                return connected;
+
+        if (RREG32(DC_HPD1_INT_STATUS + hpd_offsets[hpd]) & DC_HPDx_SENSE)
+                connected = true;
 
         return connected;
 }
@@ -303,58 +281,15 @@ static void dce_v6_0_hpd_set_polarity(struct amdgpu_device *adev,
         u32 tmp;
         bool connected = dce_v6_0_hpd_sense(adev, hpd);
 
-        switch (hpd) {
-        case AMDGPU_HPD_1:
-                tmp = RREG32(DC_HPD1_INT_CONTROL);
-                if (connected)
-                        tmp &= ~DC_HPDx_INT_POLARITY;
-                else
-                        tmp |= DC_HPDx_INT_POLARITY;
-                WREG32(DC_HPD1_INT_CONTROL, tmp);
-                break;
-        case AMDGPU_HPD_2:
-                tmp = RREG32(DC_HPD2_INT_CONTROL);
-                if (connected)
-                        tmp &= ~DC_HPDx_INT_POLARITY;
-                else
-                        tmp |= DC_HPDx_INT_POLARITY;
-                WREG32(DC_HPD2_INT_CONTROL, tmp);
-                break;
-        case AMDGPU_HPD_3:
-                tmp = RREG32(DC_HPD3_INT_CONTROL);
-                if (connected)
-                        tmp &= ~DC_HPDx_INT_POLARITY;
-                else
-                        tmp |= DC_HPDx_INT_POLARITY;
-                WREG32(DC_HPD3_INT_CONTROL, tmp);
-                break;
-        case AMDGPU_HPD_4:
-                tmp = RREG32(DC_HPD4_INT_CONTROL);
-                if (connected)
-                        tmp &= ~DC_HPDx_INT_POLARITY;
-                else
-                        tmp |= DC_HPDx_INT_POLARITY;
-                WREG32(DC_HPD4_INT_CONTROL, tmp);
-                break;
-        case AMDGPU_HPD_5:
-                tmp = RREG32(DC_HPD5_INT_CONTROL);
-                if (connected)
-                        tmp &= ~DC_HPDx_INT_POLARITY;
-                else
-                        tmp |= DC_HPDx_INT_POLARITY;
-                WREG32(DC_HPD5_INT_CONTROL, tmp);
-                        break;
-        case AMDGPU_HPD_6:
-                tmp = RREG32(DC_HPD6_INT_CONTROL);
-                if (connected)
-                        tmp &= ~DC_HPDx_INT_POLARITY;
-                else
-                        tmp |= DC_HPDx_INT_POLARITY;
-                WREG32(DC_HPD6_INT_CONTROL, tmp);
-                break;
-        default:
-                break;
-        }
+        if (hpd >= adev->mode_info.num_hpd)
+                return;
+
+        tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
+        if (connected)
+                tmp &= ~DC_HPDx_INT_POLARITY;
+        else
+                tmp |= DC_HPDx_INT_POLARITY;
+        WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
 }
 
 /**
@@ -369,34 +304,17 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
 {
         struct drm_device *dev = adev->ddev;
         struct drm_connector *connector;
-        u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
-                DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
+        u32 tmp;
 
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 
-                switch (amdgpu_connector->hpd.hpd) {
-                case AMDGPU_HPD_1:
-                        WREG32(DC_HPD1_CONTROL, tmp);
-                        break;
-                case AMDGPU_HPD_2:
-                        WREG32(DC_HPD2_CONTROL, tmp);
-                        break;
-                case AMDGPU_HPD_3:
-                        WREG32(DC_HPD3_CONTROL, tmp);
-                        break;
-                case AMDGPU_HPD_4:
-                        WREG32(DC_HPD4_CONTROL, tmp);
-                        break;
-                case AMDGPU_HPD_5:
-                        WREG32(DC_HPD5_CONTROL, tmp);
-                        break;
-                case AMDGPU_HPD_6:
-                        WREG32(DC_HPD6_CONTROL, tmp);
-                        break;
-                default:
-                        break;
-                }
+                if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+                        continue;
+
+                tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+                tmp |= DC_HPDx_EN;
+                WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
 
                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
                     connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
@@ -405,34 +323,9 @@ static void dce_v6_0_hpd_init(struct amdgpu_device *adev)
                          * https://bugzilla.redhat.com/show_bug.cgi?id=726143
                          * also avoid interrupt storms during dpms.
                          */
-                        u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
-
-                        switch (amdgpu_connector->hpd.hpd) {
-                        case AMDGPU_HPD_1:
-                                dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL;
-                                break;
-                        case AMDGPU_HPD_2:
-                                dc_hpd_int_cntl_reg = DC_HPD2_INT_CONTROL;
-                                break;
-                        case AMDGPU_HPD_3:
-                                dc_hpd_int_cntl_reg = DC_HPD3_INT_CONTROL;
-                                break;
-                        case AMDGPU_HPD_4:
-                                dc_hpd_int_cntl_reg = DC_HPD4_INT_CONTROL;
-                                break;
-                        case AMDGPU_HPD_5:
-                                dc_hpd_int_cntl_reg = DC_HPD5_INT_CONTROL;
-                                break;
-                        case AMDGPU_HPD_6:
-                                dc_hpd_int_cntl_reg = DC_HPD6_INT_CONTROL;
-                                break;
-                        default:
-                                continue;
-                        }
-
-                        dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
-                        dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
-                        WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
+                        tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+                        tmp &= ~DC_HPDx_INT_EN;
+                        WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
                         continue;
                 }
 
@@ -454,32 +347,18 @@ static void dce_v6_0_hpd_fini(struct amdgpu_device *adev)
 {
         struct drm_device *dev = adev->ddev;
         struct drm_connector *connector;
+        u32 tmp;
 
         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
                 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
 
-                switch (amdgpu_connector->hpd.hpd) {
-                case AMDGPU_HPD_1:
-                        WREG32(DC_HPD1_CONTROL, 0);
-                        break;
-                case AMDGPU_HPD_2:
-                        WREG32(DC_HPD2_CONTROL, 0);
-                        break;
-                case AMDGPU_HPD_3:
-                        WREG32(DC_HPD3_CONTROL, 0);
-                        break;
-                case AMDGPU_HPD_4:
-                        WREG32(DC_HPD4_CONTROL, 0);
-                        break;
-                case AMDGPU_HPD_5:
-                        WREG32(DC_HPD5_CONTROL, 0);
-                        break;
-                case AMDGPU_HPD_6:
-                        WREG32(DC_HPD6_CONTROL, 0);
-                        break;
-                default:
-                        break;
-                }
+                if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
+                        continue;
+
+                tmp = RREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
+                tmp &= ~DC_HPDx_EN;
+                WREG32(DC_HPD1_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], 0);
+
                 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
         }
 }
@@ -611,12 +490,55 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
 static void dce_v6_0_set_vga_render_state(struct amdgpu_device *adev,
                                           bool render)
 {
-        if (!render) 
+        if (!render)
                 WREG32(R_000300_VGA_RENDER_CONTROL,
                         RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
 
 }
 
+static int dce_v6_0_get_num_crtc(struct amdgpu_device *adev)
+{
+        int num_crtc = 0;
+
+        switch (adev->asic_type) {
+        case CHIP_TAHITI:
+        case CHIP_PITCAIRN:
+        case CHIP_VERDE:
+                num_crtc = 6;
+                break;
+        case CHIP_OLAND:
+                num_crtc = 2;
+                break;
+        default:
+                num_crtc = 0;
+        }
+        return num_crtc;
+}
+
+void dce_v6_0_disable_dce(struct amdgpu_device *adev)
+{
+        /*Disable VGA render and enabled crtc, if has DCE engine*/
+        if (amdgpu_atombios_has_dce_engine_info(adev)) {
+                u32 tmp;
+                int crtc_enabled, i;
+
+                dce_v6_0_set_vga_render_state(adev, false);
+
+                /*Disable crtc*/
+                for (i = 0; i < dce_v6_0_get_num_crtc(adev); i++) {
+                        crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) &
+                                EVERGREEN_CRTC_MASTER_EN;
+                        if (crtc_enabled) {
+                                WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+                                tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
+                                tmp &= ~EVERGREEN_CRTC_MASTER_EN;
+                                WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
+                                WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+                        }
+                }
+        }
+}
+
 static void dce_v6_0_program_fmt(struct drm_encoder *encoder)
 {
 
@@ -2338,21 +2260,20 @@ static int dce_v6_0_early_init(void *handle)
         dce_v6_0_set_display_funcs(adev);
         dce_v6_0_set_irq_funcs(adev);
 
+        adev->mode_info.num_crtc = dce_v6_0_get_num_crtc(adev);
+
         switch (adev->asic_type) {
         case CHIP_TAHITI:
         case CHIP_PITCAIRN:
         case CHIP_VERDE:
-                adev->mode_info.num_crtc = 6;
                 adev->mode_info.num_hpd = 6;
                 adev->mode_info.num_dig = 6;
                 break;
         case CHIP_OLAND:
-                adev->mode_info.num_crtc = 2;
                 adev->mode_info.num_hpd = 2;
                 adev->mode_info.num_dig = 2;
                 break;
         default:
-                /* FIXME: not supported yet */
                 return -EINVAL;
         }
 
@@ -2588,42 +2509,23 @@ static int dce_v6_0_set_hpd_interrupt_state(struct amdgpu_device *adev,
                                             unsigned type,
                                             enum amdgpu_interrupt_state state)
 {
-        u32 dc_hpd_int_cntl_reg, dc_hpd_int_cntl;
+        u32 dc_hpd_int_cntl;
 
-        switch (type) {
-        case AMDGPU_HPD_1:
-                dc_hpd_int_cntl_reg = DC_HPD1_INT_CONTROL;
-                break;
-        case AMDGPU_HPD_2:
-                dc_hpd_int_cntl_reg = DC_HPD2_INT_CONTROL;
-                break;
-        case AMDGPU_HPD_3:
-                dc_hpd_int_cntl_reg = DC_HPD3_INT_CONTROL;
-                break;
-        case AMDGPU_HPD_4:
-                dc_hpd_int_cntl_reg = DC_HPD4_INT_CONTROL;
-                break;
-        case AMDGPU_HPD_5:
-                dc_hpd_int_cntl_reg = DC_HPD5_INT_CONTROL;
-                break;
-        case AMDGPU_HPD_6:
-                dc_hpd_int_cntl_reg = DC_HPD6_INT_CONTROL;
-                break;
-        default:
+        if (type >= adev->mode_info.num_hpd) {
                 DRM_DEBUG("invalid hdp %d\n", type);
                 return 0;
         }
 
         switch (state) {
         case AMDGPU_IRQ_STATE_DISABLE:
-                dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
-                dc_hpd_int_cntl &= ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
-                WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
+                dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
+                dc_hpd_int_cntl &= ~DC_HPDx_INT_EN;
+                WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
                 break;
         case AMDGPU_IRQ_STATE_ENABLE:
-                dc_hpd_int_cntl = RREG32(dc_hpd_int_cntl_reg);
-                dc_hpd_int_cntl |= (DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN);
-                WREG32(dc_hpd_int_cntl_reg, dc_hpd_int_cntl);
+                dc_hpd_int_cntl = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type]);
+                dc_hpd_int_cntl |= DC_HPDx_INT_EN;
+                WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[type], dc_hpd_int_cntl);
                 break;
         default:
                 break;
@@ -2796,7 +2698,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
                             struct amdgpu_irq_src *source,
                             struct amdgpu_iv_entry *entry)
 {
-        uint32_t disp_int, mask, int_control, tmp;
+        uint32_t disp_int, mask, tmp;
         unsigned hpd;
 
         if (entry->src_data >= adev->mode_info.num_hpd) {
@@ -2807,12 +2709,11 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
         hpd = entry->src_data;
         disp_int = RREG32(interrupt_status_offsets[hpd].reg);
         mask = interrupt_status_offsets[hpd].hpd;
-        int_control = hpd_int_control_offsets[hpd];
 
         if (disp_int & mask) {
-                tmp = RREG32(int_control);
+                tmp = RREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd]);
                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
-                WREG32(int_control, tmp);
+                WREG32(DC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
                 schedule_work(&adev->hotplug_work);
                 DRM_INFO("IH: HPD%d\n", hpd + 1);
         }
@@ -2833,7 +2734,7 @@ static int dce_v6_0_set_powergating_state(void *handle,
         return 0;
 }
 
-const struct amd_ip_funcs dce_v6_0_ip_funcs = {
+static const struct amd_ip_funcs dce_v6_0_ip_funcs = {
         .name = "dce_v6_0",
         .early_init = dce_v6_0_early_init,
         .late_init = NULL,
@@ -3174,3 +3075,21 @@ static void dce_v6_0_set_irq_funcs(struct amdgpu_device *adev)
         adev->hpd_irq.num_types = AMDGPU_HPD_LAST;
         adev->hpd_irq.funcs = &dce_v6_0_hpd_irq_funcs;
 }
+
+const struct amdgpu_ip_block_version dce_v6_0_ip_block =
+{
+        .type = AMD_IP_BLOCK_TYPE_DCE,
+        .major = 6,
+        .minor = 0,
+        .rev = 0,
+        .funcs = &dce_v6_0_ip_funcs,
+};
+
+const struct amdgpu_ip_block_version dce_v6_4_ip_block =
+{
+        .type = AMD_IP_BLOCK_TYPE_DCE,
+        .major = 6,
+        .minor = 4,
+        .rev = 0,
+        .funcs = &dce_v6_0_ip_funcs,
+};