1 files changed, 20 insertions, 69 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
index bd2c4f727df6..9f67b7fd3487 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c
@@ -142,64 +142,6 @@ static void dce_v6_0_audio_endpt_wreg(struct amdgpu_device *adev,
         spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
 }
 
-static bool dce_v6_0_is_in_vblank(struct amdgpu_device *adev, int crtc)
-{
-        if (RREG32(mmCRTC_STATUS + crtc_offsets[crtc]) & CRTC_STATUS__CRTC_V_BLANK_MASK)
-                return true;
-        else
-                return false;
-}
-
-static bool dce_v6_0_is_counter_moving(struct amdgpu_device *adev, int crtc)
-{
-        u32 pos1, pos2;
-
-        pos1 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
-        pos2 = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
-
-        if (pos1 != pos2)
-                return true;
-        else
-                return false;
-}
-
-/**
- * dce_v6_0_wait_for_vblank - vblank wait asic callback.
- *
- * @crtc: crtc to wait for vblank on
- *
- * Wait for vblank on the requested crtc (evergreen+).
- */
-static void dce_v6_0_vblank_wait(struct amdgpu_device *adev, int crtc)
-{
-        unsigned i = 100;
-
-        if (crtc >= adev->mode_info.num_crtc)
-                return;
-
-        if (!(RREG32(mmCRTC_CONTROL + crtc_offsets[crtc]) & CRTC_CONTROL__CRTC_MASTER_EN_MASK))
-                return;
-
-        /* depending on when we hit vblank, we may be close to active; if so,
-         * wait for another frame.
-         */
-        while (dce_v6_0_is_in_vblank(adev, crtc)) {
-                if (i++ == 100) {
-                        i = 0;
-                        if (!dce_v6_0_is_counter_moving(adev, crtc))
-                                break;
-                }
-        }
-
-        while (!dce_v6_0_is_in_vblank(adev, crtc)) {
-                if (i++ == 100) {
-                        i = 0;
-                        if (!dce_v6_0_is_counter_moving(adev, crtc))
-                                break;
-                }
-        }
-}
-
 static u32 dce_v6_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
 {
         if (crtc >= adev->mode_info.num_crtc)
@@ -1108,7 +1050,7 @@ static void dce_v6_0_bandwidth_update(struct amdgpu_device *adev)
         if (!adev->mode_info.mode_config_initialized)
                 return;
 
-        amdgpu_update_display_priority(adev);
+        amdgpu_display_update_priority(adev);
 
         for (i = 0; i < adev->mode_info.num_crtc; i++) {
                 if (adev->mode_info.crtcs[i]->base.enabled)
@@ -2407,9 +2349,9 @@ static const struct drm_crtc_funcs dce_v6_0_crtc_funcs = {
         .cursor_set2 = dce_v6_0_crtc_cursor_set2,
         .cursor_move = dce_v6_0_crtc_cursor_move,
         .gamma_set = dce_v6_0_crtc_gamma_set,
-        .set_config = amdgpu_crtc_set_config,
+        .set_config = amdgpu_display_crtc_set_config,
         .destroy = dce_v6_0_crtc_destroy,
-        .page_flip_target = amdgpu_crtc_page_flip_target,
+        .page_flip_target = amdgpu_display_crtc_page_flip_target,
 };
 
 static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
@@ -2425,7 +2367,8 @@ static void dce_v6_0_crtc_dpms(struct drm_crtc *crtc, int mode)
                 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
                 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
                 /* Make sure VBLANK and PFLIP interrupts are still enabled */
-                type = amdgpu_crtc_idx_to_irq_type(adev, amdgpu_crtc->crtc_id);
+                type = amdgpu_display_crtc_idx_to_irq_type(adev,
+                                                amdgpu_crtc->crtc_id);
                 amdgpu_irq_update(adev, &adev->crtc_irq, type);
                 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
                 drm_crtc_vblank_on(crtc);
@@ -2562,7 +2505,7 @@ static bool dce_v6_0_crtc_mode_fixup(struct drm_crtc *crtc,
                 amdgpu_crtc->connector = NULL;
                 return false;
         }
-        if (!amdgpu_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
+        if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
                 return false;
         if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
                 return false;
@@ -2693,9 +2636,9 @@ static int dce_v6_0_sw_init(void *handle)
         adev->ddev->mode_config.max_height = 16384;
         adev->ddev->mode_config.preferred_depth = 24;
         adev->ddev->mode_config.prefer_shadow = 1;
-        adev->ddev->mode_config.fb_base = adev->mc.aper_base;
+        adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
 
-        r = amdgpu_modeset_create_props(adev);
+        r = amdgpu_display_modeset_create_props(adev);
         if (r)
                 return r;
 
@@ -2711,7 +2654,7 @@ static int dce_v6_0_sw_init(void *handle)
 
         ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
         if (ret)
-                amdgpu_print_display_setup(adev->ddev);
+                amdgpu_display_print_display_setup(adev->ddev);
         else
                 return -EINVAL;
 
@@ -2787,6 +2730,11 @@ static int dce_v6_0_hw_fini(void *handle)
 
 static int dce_v6_0_suspend(void *handle)
 {
+        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+
+        adev->mode_info.bl_level =
+                amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
+
         return dce_v6_0_hw_fini(handle);
 }
 
@@ -2795,6 +2743,9 @@ static int dce_v6_0_resume(void *handle)
         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
         int ret;
 
+        amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
+                                                           adev->mode_info.bl_level);
+
         ret = dce_v6_0_hw_init(handle);
 
         /* turn on the BL */
@@ -2966,7 +2917,8 @@ static int dce_v6_0_crtc_irq(struct amdgpu_device *adev,
 {
         unsigned crtc = entry->src_id - 1;
         uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
-        unsigned irq_type = amdgpu_crtc_idx_to_irq_type(adev, crtc);
+        unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
+                                                                    crtc);
 
         switch (entry->src_data[0]) {
         case 0: /* vblank */
@@ -3093,7 +3045,7 @@ static int dce_v6_0_hpd_irq(struct amdgpu_device *adev,
                 tmp |= DC_HPD1_INT_CONTROL__DC_HPD1_INT_ACK_MASK;
                 WREG32(mmDC_HPD1_INT_CONTROL + hpd_offsets[hpd], tmp);
                 schedule_work(&adev->hotplug_work);
-                DRM_INFO("IH: HPD%d\n", hpd + 1);
+                DRM_DEBUG("IH: HPD%d\n", hpd + 1);
         }
 
         return 0;
@@ -3407,7 +3359,6 @@ static void dce_v6_0_encoder_add(struct amdgpu_device *adev,
 static const struct amdgpu_display_funcs dce_v6_0_display_funcs = {
         .bandwidth_update = &dce_v6_0_bandwidth_update,
         .vblank_get_counter = &dce_v6_0_vblank_get_counter,
-        .vblank_wait = &dce_v6_0_vblank_wait,
         .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
         .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
         .hpd_sense = &dce_v6_0_hpd_sense,