1 files changed, 41 insertions, 1 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 7f642b57223e..b888d7223e8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -712,6 +712,45 @@ static void dce_v10_0_set_vga_render_state(struct amdgpu_device *adev,
         WREG32(mmVGA_RENDER_CONTROL, tmp);
 }
 
+static int dce_v10_0_get_num_crtc(struct amdgpu_device *adev)
+{
+        int num_crtc = 0;
+
+        switch (adev->asic_type) {
+        case CHIP_FIJI:
+        case CHIP_TONGA:
+                num_crtc = 6;
+                break;
+        default:
+                num_crtc = 0;
+        }
+        return num_crtc;
+}
+
+void dce_v10_0_disable_dce(struct amdgpu_device *adev)
+{
+        /*Disable VGA render and enabled crtc, if has DCE engine*/
+        if (amdgpu_atombios_has_dce_engine_info(adev)) {
+                u32 tmp;
+                int crtc_enabled, i;
+
+                dce_v10_0_set_vga_render_state(adev, false);
+
+                /*Disable crtc*/
+                for (i = 0; i < dce_v10_0_get_num_crtc(adev); i++) {
+                        crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
+                                                                         CRTC_CONTROL, CRTC_MASTER_EN);
+                        if (crtc_enabled) {
+                                WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
+                                tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
+                                tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
+                                WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
+                                WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
+                        }
+                }
+        }
+}
+
 static void dce_v10_0_program_fmt(struct drm_encoder *encoder)
 {
         struct drm_device *dev = encoder->dev;
@@ -2962,10 +3001,11 @@ static int dce_v10_0_early_init(void *handle)
         dce_v10_0_set_display_funcs(adev);
         dce_v10_0_set_irq_funcs(adev);
 
+        adev->mode_info.num_crtc = dce_v10_0_get_num_crtc(adev);
+
         switch (adev->asic_type) {
         case CHIP_FIJI:
         case CHIP_TONGA:
-                adev->mode_info.num_crtc = 6; /* XXX 7??? */
                 adev->mode_info.num_hpd = 6;
                 adev->mode_info.num_dig = 7;
                 break;