diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h | 185 |
1 files changed, 185 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h b/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h new file mode 100644 index 000000000000..273616ab43db --- /dev/null +++ b/drivers/gpu/drm/amd/amdgpu/cz_ppsmc.h | |||
@@ -0,0 +1,185 @@ | |||
1 | /* | ||
2 | * Copyright 2014 Advanced Micro Devices, Inc. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR | ||
18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, | ||
19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | ||
20 | * OTHER DEALINGS IN THE SOFTWARE. | ||
21 | * | ||
22 | */ | ||
23 | |||
24 | #ifndef CZ_PP_SMC_H | ||
25 | #define CZ_PP_SMC_H | ||
26 | |||
27 | #pragma pack(push, 1) | ||
28 | |||
29 | /* Fan control algorithm:*/ | ||
30 | #define FDO_MODE_HARDWARE 0 | ||
31 | #define FDO_MODE_PIECE_WISE_LINEAR 1 | ||
32 | |||
33 | enum FAN_CONTROL { | ||
34 | FAN_CONTROL_FUZZY, | ||
35 | FAN_CONTROL_TABLE | ||
36 | }; | ||
37 | |||
38 | enum DPM_ARRAY { | ||
39 | DPM_ARRAY_HARD_MAX, | ||
40 | DPM_ARRAY_HARD_MIN, | ||
41 | DPM_ARRAY_SOFT_MAX, | ||
42 | DPM_ARRAY_SOFT_MIN | ||
43 | }; | ||
44 | |||
45 | /* | ||
46 | * Return codes for driver to SMC communication. | ||
47 | * Leave these #define-s, enums might not be exactly 8-bits on the microcontroller. | ||
48 | */ | ||
49 | #define PPSMC_Result_OK ((uint16_t)0x01) | ||
50 | #define PPSMC_Result_NoMore ((uint16_t)0x02) | ||
51 | #define PPSMC_Result_NotNow ((uint16_t)0x03) | ||
52 | #define PPSMC_Result_Failed ((uint16_t)0xFF) | ||
53 | #define PPSMC_Result_UnknownCmd ((uint16_t)0xFE) | ||
54 | #define PPSMC_Result_UnknownVT ((uint16_t)0xFD) | ||
55 | |||
56 | #define PPSMC_isERROR(x) ((uint16_t)0x80 & (x)) | ||
57 | |||
58 | /* | ||
59 | * Supported driver messages | ||
60 | */ | ||
61 | #define PPSMC_MSG_Test ((uint16_t) 0x1) | ||
62 | #define PPSMC_MSG_GetFeatureStatus ((uint16_t) 0x2) | ||
63 | #define PPSMC_MSG_EnableAllSmuFeatures ((uint16_t) 0x3) | ||
64 | #define PPSMC_MSG_DisableAllSmuFeatures ((uint16_t) 0x4) | ||
65 | #define PPSMC_MSG_OptimizeBattery ((uint16_t) 0x5) | ||
66 | #define PPSMC_MSG_MaximizePerf ((uint16_t) 0x6) | ||
67 | #define PPSMC_MSG_UVDPowerOFF ((uint16_t) 0x7) | ||
68 | #define PPSMC_MSG_UVDPowerON ((uint16_t) 0x8) | ||
69 | #define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x9) | ||
70 | #define PPSMC_MSG_VCEPowerON ((uint16_t) 0xA) | ||
71 | #define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0xB) | ||
72 | #define PPSMC_MSG_ACPPowerON ((uint16_t) 0xC) | ||
73 | #define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0xD) | ||
74 | #define PPSMC_MSG_SDMAPowerON ((uint16_t) 0xE) | ||
75 | #define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0xF) | ||
76 | #define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x10) | ||
77 | #define PPSMC_MSG_SetMinDeepSleepSclk ((uint16_t) 0x11) | ||
78 | #define PPSMC_MSG_SetSclkSoftMin ((uint16_t) 0x12) | ||
79 | #define PPSMC_MSG_SetSclkSoftMax ((uint16_t) 0x13) | ||
80 | #define PPSMC_MSG_SetSclkHardMin ((uint16_t) 0x14) | ||
81 | #define PPSMC_MSG_SetSclkHardMax ((uint16_t) 0x15) | ||
82 | #define PPSMC_MSG_SetLclkSoftMin ((uint16_t) 0x16) | ||
83 | #define PPSMC_MSG_SetLclkSoftMax ((uint16_t) 0x17) | ||
84 | #define PPSMC_MSG_SetLclkHardMin ((uint16_t) 0x18) | ||
85 | #define PPSMC_MSG_SetLclkHardMax ((uint16_t) 0x19) | ||
86 | #define PPSMC_MSG_SetUvdSoftMin ((uint16_t) 0x1A) | ||
87 | #define PPSMC_MSG_SetUvdSoftMax ((uint16_t) 0x1B) | ||
88 | #define PPSMC_MSG_SetUvdHardMin ((uint16_t) 0x1C) | ||
89 | #define PPSMC_MSG_SetUvdHardMax ((uint16_t) 0x1D) | ||
90 | #define PPSMC_MSG_SetEclkSoftMin ((uint16_t) 0x1E) | ||
91 | #define PPSMC_MSG_SetEclkSoftMax ((uint16_t) 0x1F) | ||
92 | #define PPSMC_MSG_SetEclkHardMin ((uint16_t) 0x20) | ||
93 | #define PPSMC_MSG_SetEclkHardMax ((uint16_t) 0x21) | ||
94 | #define PPSMC_MSG_SetAclkSoftMin ((uint16_t) 0x22) | ||
95 | #define PPSMC_MSG_SetAclkSoftMax ((uint16_t) 0x23) | ||
96 | #define PPSMC_MSG_SetAclkHardMin ((uint16_t) 0x24) | ||
97 | #define PPSMC_MSG_SetAclkHardMax ((uint16_t) 0x25) | ||
98 | #define PPSMC_MSG_SetNclkSoftMin ((uint16_t) 0x26) | ||
99 | #define PPSMC_MSG_SetNclkSoftMax ((uint16_t) 0x27) | ||
100 | #define PPSMC_MSG_SetNclkHardMin ((uint16_t) 0x28) | ||
101 | #define PPSMC_MSG_SetNclkHardMax ((uint16_t) 0x29) | ||
102 | #define PPSMC_MSG_SetPstateSoftMin ((uint16_t) 0x2A) | ||
103 | #define PPSMC_MSG_SetPstateSoftMax ((uint16_t) 0x2B) | ||
104 | #define PPSMC_MSG_SetPstateHardMin ((uint16_t) 0x2C) | ||
105 | #define PPSMC_MSG_SetPstateHardMax ((uint16_t) 0x2D) | ||
106 | #define PPSMC_MSG_DisableLowMemoryPstate ((uint16_t) 0x2E) | ||
107 | #define PPSMC_MSG_EnableLowMemoryPstate ((uint16_t) 0x2F) | ||
108 | #define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x30) | ||
109 | #define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x31) | ||
110 | #define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x32) | ||
111 | #define PPSMC_MSG_DriverDramAddrHi ((uint16_t) 0x33) | ||
112 | #define PPSMC_MSG_DriverDramAddrLo ((uint16_t) 0x34) | ||
113 | #define PPSMC_MSG_CondExecDramAddrHi ((uint16_t) 0x35) | ||
114 | #define PPSMC_MSG_CondExecDramAddrLo ((uint16_t) 0x36) | ||
115 | #define PPSMC_MSG_LoadUcodes ((uint16_t) 0x37) | ||
116 | #define PPSMC_MSG_DriverResetMode ((uint16_t) 0x38) | ||
117 | #define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x39) | ||
118 | #define PPSMC_MSG_SetDisplayPhyConfig ((uint16_t) 0x3A) | ||
119 | #define PPSMC_MSG_GetMaxSclkLevel ((uint16_t) 0x3B) | ||
120 | #define PPSMC_MSG_GetMaxLclkLevel ((uint16_t) 0x3C) | ||
121 | #define PPSMC_MSG_GetMaxUvdLevel ((uint16_t) 0x3D) | ||
122 | #define PPSMC_MSG_GetMaxEclkLevel ((uint16_t) 0x3E) | ||
123 | #define PPSMC_MSG_GetMaxAclkLevel ((uint16_t) 0x3F) | ||
124 | #define PPSMC_MSG_GetMaxNclkLevel ((uint16_t) 0x40) | ||
125 | #define PPSMC_MSG_GetMaxPstate ((uint16_t) 0x41) | ||
126 | #define PPSMC_MSG_DramAddrHiVirtual ((uint16_t) 0x42) | ||
127 | #define PPSMC_MSG_DramAddrLoVirtual ((uint16_t) 0x43) | ||
128 | #define PPSMC_MSG_DramAddrHiPhysical ((uint16_t) 0x44) | ||
129 | #define PPSMC_MSG_DramAddrLoPhysical ((uint16_t) 0x45) | ||
130 | #define PPSMC_MSG_DramBufferSize ((uint16_t) 0x46) | ||
131 | #define PPSMC_MSG_SetMmPwrLogDramAddrHi ((uint16_t) 0x47) | ||
132 | #define PPSMC_MSG_SetMmPwrLogDramAddrLo ((uint16_t) 0x48) | ||
133 | #define PPSMC_MSG_SetClkTableAddrHi ((uint16_t) 0x49) | ||
134 | #define PPSMC_MSG_SetClkTableAddrLo ((uint16_t) 0x4A) | ||
135 | #define PPSMC_MSG_GetConservativePowerLimit ((uint16_t) 0x4B) | ||
136 | |||
137 | #define PPSMC_MSG_InitJobs ((uint16_t) 0x252) | ||
138 | #define PPSMC_MSG_ExecuteJob ((uint16_t) 0x254) | ||
139 | |||
140 | #define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140) | ||
141 | #define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141) | ||
142 | |||
143 | #define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d) | ||
144 | #define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e) | ||
145 | |||
146 | #define PPSMC_MSG_PmStatusLogStart ((uint16_t) 0x170) | ||
147 | #define PPSMC_MSG_PmStatusLogSample ((uint16_t) 0x171) | ||
148 | |||
149 | #define PPSMC_MSG_AllowLowSclkInterrupt ((uint16_t) 0x184) | ||
150 | #define PPSMC_MSG_MmPowerMonitorStart ((uint16_t) 0x18F) | ||
151 | #define PPSMC_MSG_MmPowerMonitorStop ((uint16_t) 0x190) | ||
152 | #define PPSMC_MSG_MmPowerMonitorRestart ((uint16_t) 0x191) | ||
153 | |||
154 | #define PPSMC_MSG_SetClockGateMask ((uint16_t) 0x260) | ||
155 | #define PPSMC_MSG_SetFpsThresholdLo ((uint16_t) 0x264) | ||
156 | #define PPSMC_MSG_SetFpsThresholdHi ((uint16_t) 0x265) | ||
157 | #define PPSMC_MSG_SetLowSclkIntrThreshold ((uint16_t) 0x266) | ||
158 | |||
159 | #define PPSMC_MSG_ClkTableXferToDram ((uint16_t) 0x267) | ||
160 | #define PPSMC_MSG_ClkTableXferToSmu ((uint16_t) 0x268) | ||
161 | #define PPSMC_MSG_GetAverageGraphicsActivity ((uint16_t) 0x269) | ||
162 | #define PPSMC_MSG_GetAverageGioActivity ((uint16_t) 0x26A) | ||
163 | #define PPSMC_MSG_SetLoggerBufferSize ((uint16_t) 0x26B) | ||
164 | #define PPSMC_MSG_SetLoggerAddressHigh ((uint16_t) 0x26C) | ||
165 | #define PPSMC_MSG_SetLoggerAddressLow ((uint16_t) 0x26D) | ||
166 | #define PPSMC_MSG_SetWatermarkFrequency ((uint16_t) 0x26E) | ||
167 | |||
168 | /* REMOVE LATER*/ | ||
169 | #define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104) | ||
170 | |||
171 | /* Feature Enable Masks*/ | ||
172 | #define NB_DPM_MASK 0x00000800 | ||
173 | #define VDDGFX_MASK 0x00800000 | ||
174 | #define VCE_DPM_MASK 0x00400000 | ||
175 | #define ACP_DPM_MASK 0x00040000 | ||
176 | #define UVD_DPM_MASK 0x00010000 | ||
177 | #define GFX_CU_PG_MASK 0x00004000 | ||
178 | #define SCLK_DPM_MASK 0x00080000 | ||
179 | |||
180 | #if !defined(SMC_MICROCODE) | ||
181 | #pragma pack(pop) | ||
182 | |||
183 | #endif | ||
184 | |||
185 | #endif | ||