diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik_sdma.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 15 |
1 files changed, 3 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c index 037e3db69547..d5055ea4d112 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c | |||
@@ -188,8 +188,6 @@ static void cik_sdma_ring_set_wptr(struct amdgpu_ring *ring) | |||
188 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); | 188 | WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[me], (ring->wptr << 2) & 0x3fffc); |
189 | } | 189 | } |
190 | 190 | ||
191 | static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *); | ||
192 | |||
193 | /** | 191 | /** |
194 | * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine | 192 | * cik_sdma_ring_emit_ib - Schedule an IB on the DMA engine |
195 | * | 193 | * |
@@ -204,9 +202,6 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |||
204 | u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; | 202 | u32 extra_bits = (ib->vm ? ib->vm->ids[ring->idx].id : 0) & 0xf; |
205 | u32 next_rptr = ring->wptr + 5; | 203 | u32 next_rptr = ring->wptr + 5; |
206 | 204 | ||
207 | if (ib->flush_hdp_writefifo) | ||
208 | next_rptr += 6; | ||
209 | |||
210 | while ((next_rptr & 7) != 4) | 205 | while ((next_rptr & 7) != 4) |
211 | next_rptr++; | 206 | next_rptr++; |
212 | 207 | ||
@@ -217,11 +212,6 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |||
217 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ | 212 | amdgpu_ring_write(ring, 1); /* number of DWs to follow */ |
218 | amdgpu_ring_write(ring, next_rptr); | 213 | amdgpu_ring_write(ring, next_rptr); |
219 | 214 | ||
220 | if (ib->flush_hdp_writefifo) { | ||
221 | /* flush HDP */ | ||
222 | cik_sdma_hdp_flush_ring_emit(ring); | ||
223 | } | ||
224 | |||
225 | /* IB packet must end on a 8 DW boundary */ | 215 | /* IB packet must end on a 8 DW boundary */ |
226 | while ((ring->wptr & 7) != 4) | 216 | while ((ring->wptr & 7) != 4) |
227 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); | 217 | amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); |
@@ -233,13 +223,13 @@ static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring, | |||
233 | } | 223 | } |
234 | 224 | ||
235 | /** | 225 | /** |
236 | * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring | 226 | * cik_sdma_ring_emit_hdp_flush - emit an hdp flush on the DMA ring |
237 | * | 227 | * |
238 | * @ring: amdgpu ring pointer | 228 | * @ring: amdgpu ring pointer |
239 | * | 229 | * |
240 | * Emit an hdp flush packet on the requested DMA ring. | 230 | * Emit an hdp flush packet on the requested DMA ring. |
241 | */ | 231 | */ |
242 | static void cik_sdma_hdp_flush_ring_emit(struct amdgpu_ring *ring) | 232 | static void cik_sdma_ring_emit_hdp_flush(struct amdgpu_ring *ring) |
243 | { | 233 | { |
244 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | | 234 | u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | |
245 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ | 235 | SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ |
@@ -1317,6 +1307,7 @@ static const struct amdgpu_ring_funcs cik_sdma_ring_funcs = { | |||
1317 | .emit_fence = cik_sdma_ring_emit_fence, | 1307 | .emit_fence = cik_sdma_ring_emit_fence, |
1318 | .emit_semaphore = cik_sdma_ring_emit_semaphore, | 1308 | .emit_semaphore = cik_sdma_ring_emit_semaphore, |
1319 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, | 1309 | .emit_vm_flush = cik_sdma_ring_emit_vm_flush, |
1310 | .emit_hdp_flush = cik_sdma_ring_emit_hdp_flush, | ||
1320 | .test_ring = cik_sdma_ring_test_ring, | 1311 | .test_ring = cik_sdma_ring_test_ring, |
1321 | .test_ib = cik_sdma_ring_test_ib, | 1312 | .test_ib = cik_sdma_ring_test_ib, |
1322 | .is_lockup = cik_sdma_ring_is_lockup, | 1313 | .is_lockup = cik_sdma_ring_is_lockup, |