diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/cik.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c index b3b66a0d5ff7..4b6ce74753cd 100644 --- a/drivers/gpu/drm/amd/amdgpu/cik.c +++ b/drivers/gpu/drm/amd/amdgpu/cik.c | |||
@@ -838,7 +838,7 @@ static u32 cik_get_xclk(struct amdgpu_device *adev) | |||
838 | { | 838 | { |
839 | u32 reference_clock = adev->clock.spll.reference_freq; | 839 | u32 reference_clock = adev->clock.spll.reference_freq; |
840 | 840 | ||
841 | if (adev->flags & AMDGPU_IS_APU) { | 841 | if (adev->flags & AMD_IS_APU) { |
842 | if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) | 842 | if (RREG32_SMC(ixGENERAL_PWRMGT) & GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK) |
843 | return reference_clock / 2; | 843 | return reference_clock / 2; |
844 | } else { | 844 | } else { |
@@ -1235,7 +1235,7 @@ static void cik_gpu_soft_reset(struct amdgpu_device *adev, u32 reset_mask) | |||
1235 | if (reset_mask & AMDGPU_RESET_VMC) | 1235 | if (reset_mask & AMDGPU_RESET_VMC) |
1236 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; | 1236 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_VMC_MASK; |
1237 | 1237 | ||
1238 | if (!(adev->flags & AMDGPU_IS_APU)) { | 1238 | if (!(adev->flags & AMD_IS_APU)) { |
1239 | if (reset_mask & AMDGPU_RESET_MC) | 1239 | if (reset_mask & AMDGPU_RESET_MC) |
1240 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; | 1240 | srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_MC_MASK; |
1241 | } | 1241 | } |
@@ -1411,7 +1411,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) | |||
1411 | dev_warn(adev->dev, "Wait for MC idle timed out !\n"); | 1411 | dev_warn(adev->dev, "Wait for MC idle timed out !\n"); |
1412 | } | 1412 | } |
1413 | 1413 | ||
1414 | if (adev->flags & AMDGPU_IS_APU) | 1414 | if (adev->flags & AMD_IS_APU) |
1415 | kv_save_regs_for_reset(adev, &kv_save); | 1415 | kv_save_regs_for_reset(adev, &kv_save); |
1416 | 1416 | ||
1417 | /* disable BM */ | 1417 | /* disable BM */ |
@@ -1429,7 +1429,7 @@ static void cik_gpu_pci_config_reset(struct amdgpu_device *adev) | |||
1429 | } | 1429 | } |
1430 | 1430 | ||
1431 | /* does asic init need to be run first??? */ | 1431 | /* does asic init need to be run first??? */ |
1432 | if (adev->flags & AMDGPU_IS_APU) | 1432 | if (adev->flags & AMD_IS_APU) |
1433 | kv_restore_regs_for_reset(adev, &kv_save); | 1433 | kv_restore_regs_for_reset(adev, &kv_save); |
1434 | } | 1434 | } |
1435 | 1435 | ||
@@ -1570,7 +1570,7 @@ static void cik_pcie_gen3_enable(struct amdgpu_device *adev) | |||
1570 | if (amdgpu_pcie_gen2 == 0) | 1570 | if (amdgpu_pcie_gen2 == 0) |
1571 | return; | 1571 | return; |
1572 | 1572 | ||
1573 | if (adev->flags & AMDGPU_IS_APU) | 1573 | if (adev->flags & AMD_IS_APU) |
1574 | return; | 1574 | return; |
1575 | 1575 | ||
1576 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); | 1576 | ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask); |
@@ -1730,7 +1730,7 @@ static void cik_program_aspm(struct amdgpu_device *adev) | |||
1730 | return; | 1730 | return; |
1731 | 1731 | ||
1732 | /* XXX double check APUs */ | 1732 | /* XXX double check APUs */ |
1733 | if (adev->flags & AMDGPU_IS_APU) | 1733 | if (adev->flags & AMD_IS_APU) |
1734 | return; | 1734 | return; |
1735 | 1735 | ||
1736 | orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); | 1736 | orig = data = RREG32_PCIE(ixPCIE_LC_N_FTS_CNTL); |