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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/cik.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/cik.c834
1 files changed, 80 insertions, 754 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/cik.c b/drivers/gpu/drm/amd/amdgpu/cik.c
index a845b6a93b79..302df85893ab 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik.c
@@ -1189,18 +1189,6 @@ static int cik_gpu_pci_config_reset(struct amdgpu_device *adev)
1189 return r; 1189 return r;
1190} 1190}
1191 1191
1192static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hung)
1193{
1194 u32 tmp = RREG32(mmBIOS_SCRATCH_3);
1195
1196 if (hung)
1197 tmp |= ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1198 else
1199 tmp &= ~ATOM_S3_ASIC_GUI_ENGINE_HUNG;
1200
1201 WREG32(mmBIOS_SCRATCH_3, tmp);
1202}
1203
1204/** 1192/**
1205 * cik_asic_reset - soft reset GPU 1193 * cik_asic_reset - soft reset GPU
1206 * 1194 *
@@ -1213,11 +1201,12 @@ static void cik_set_bios_scratch_engine_hung(struct amdgpu_device *adev, bool hu
1213static int cik_asic_reset(struct amdgpu_device *adev) 1201static int cik_asic_reset(struct amdgpu_device *adev)
1214{ 1202{
1215 int r; 1203 int r;
1216 cik_set_bios_scratch_engine_hung(adev, true); 1204
1205 amdgpu_atombios_scratch_regs_engine_hung(adev, true);
1217 1206
1218 r = cik_gpu_pci_config_reset(adev); 1207 r = cik_gpu_pci_config_reset(adev);
1219 1208
1220 cik_set_bios_scratch_engine_hung(adev, false); 1209 amdgpu_atombios_scratch_regs_engine_hung(adev, false);
1221 1210
1222 return r; 1211 return r;
1223} 1212}
@@ -1641,745 +1630,6 @@ static void cik_detect_hw_virtualization(struct amdgpu_device *adev)
1641 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE; 1630 adev->virtualization.virtual_caps |= AMDGPU_PASSTHROUGH_MODE;
1642} 1631}
1643 1632
1644static const struct amdgpu_ip_block_version bonaire_ip_blocks[] =
1645{
1646 /* ORDER MATTERS! */
1647 {
1648 .type = AMD_IP_BLOCK_TYPE_COMMON,
1649 .major = 1,
1650 .minor = 0,
1651 .rev = 0,
1652 .funcs = &cik_common_ip_funcs,
1653 },
1654 {
1655 .type = AMD_IP_BLOCK_TYPE_GMC,
1656 .major = 7,
1657 .minor = 0,
1658 .rev = 0,
1659 .funcs = &gmc_v7_0_ip_funcs,
1660 },
1661 {
1662 .type = AMD_IP_BLOCK_TYPE_IH,
1663 .major = 2,
1664 .minor = 0,
1665 .rev = 0,
1666 .funcs = &cik_ih_ip_funcs,
1667 },
1668 {
1669 .type = AMD_IP_BLOCK_TYPE_SMC,
1670 .major = 7,
1671 .minor = 0,
1672 .rev = 0,
1673 .funcs = &amdgpu_pp_ip_funcs,
1674 },
1675 {
1676 .type = AMD_IP_BLOCK_TYPE_DCE,
1677 .major = 8,
1678 .minor = 2,
1679 .rev = 0,
1680 .funcs = &dce_v8_0_ip_funcs,
1681 },
1682 {
1683 .type = AMD_IP_BLOCK_TYPE_GFX,
1684 .major = 7,
1685 .minor = 2,
1686 .rev = 0,
1687 .funcs = &gfx_v7_0_ip_funcs,
1688 },
1689 {
1690 .type = AMD_IP_BLOCK_TYPE_SDMA,
1691 .major = 2,
1692 .minor = 0,
1693 .rev = 0,
1694 .funcs = &cik_sdma_ip_funcs,
1695 },
1696 {
1697 .type = AMD_IP_BLOCK_TYPE_UVD,
1698 .major = 4,
1699 .minor = 2,
1700 .rev = 0,
1701 .funcs = &uvd_v4_2_ip_funcs,
1702 },
1703 {
1704 .type = AMD_IP_BLOCK_TYPE_VCE,
1705 .major = 2,
1706 .minor = 0,
1707 .rev = 0,
1708 .funcs = &vce_v2_0_ip_funcs,
1709 },
1710};
1711
1712static const struct amdgpu_ip_block_version bonaire_ip_blocks_vd[] =
1713{
1714 /* ORDER MATTERS! */
1715 {
1716 .type = AMD_IP_BLOCK_TYPE_COMMON,
1717 .major = 1,
1718 .minor = 0,
1719 .rev = 0,
1720 .funcs = &cik_common_ip_funcs,
1721 },
1722 {
1723 .type = AMD_IP_BLOCK_TYPE_GMC,
1724 .major = 7,
1725 .minor = 0,
1726 .rev = 0,
1727 .funcs = &gmc_v7_0_ip_funcs,
1728 },
1729 {
1730 .type = AMD_IP_BLOCK_TYPE_IH,
1731 .major = 2,
1732 .minor = 0,
1733 .rev = 0,
1734 .funcs = &cik_ih_ip_funcs,
1735 },
1736 {
1737 .type = AMD_IP_BLOCK_TYPE_SMC,
1738 .major = 7,
1739 .minor = 0,
1740 .rev = 0,
1741 .funcs = &amdgpu_pp_ip_funcs,
1742 },
1743 {
1744 .type = AMD_IP_BLOCK_TYPE_DCE,
1745 .major = 8,
1746 .minor = 2,
1747 .rev = 0,
1748 .funcs = &dce_virtual_ip_funcs,
1749 },
1750 {
1751 .type = AMD_IP_BLOCK_TYPE_GFX,
1752 .major = 7,
1753 .minor = 2,
1754 .rev = 0,
1755 .funcs = &gfx_v7_0_ip_funcs,
1756 },
1757 {
1758 .type = AMD_IP_BLOCK_TYPE_SDMA,
1759 .major = 2,
1760 .minor = 0,
1761 .rev = 0,
1762 .funcs = &cik_sdma_ip_funcs,
1763 },
1764 {
1765 .type = AMD_IP_BLOCK_TYPE_UVD,
1766 .major = 4,
1767 .minor = 2,
1768 .rev = 0,
1769 .funcs = &uvd_v4_2_ip_funcs,
1770 },
1771 {
1772 .type = AMD_IP_BLOCK_TYPE_VCE,
1773 .major = 2,
1774 .minor = 0,
1775 .rev = 0,
1776 .funcs = &vce_v2_0_ip_funcs,
1777 },
1778};
1779
1780static const struct amdgpu_ip_block_version hawaii_ip_blocks[] =
1781{
1782 /* ORDER MATTERS! */
1783 {
1784 .type = AMD_IP_BLOCK_TYPE_COMMON,
1785 .major = 1,
1786 .minor = 0,
1787 .rev = 0,
1788 .funcs = &cik_common_ip_funcs,
1789 },
1790 {
1791 .type = AMD_IP_BLOCK_TYPE_GMC,
1792 .major = 7,
1793 .minor = 0,
1794 .rev = 0,
1795 .funcs = &gmc_v7_0_ip_funcs,
1796 },
1797 {
1798 .type = AMD_IP_BLOCK_TYPE_IH,
1799 .major = 2,
1800 .minor = 0,
1801 .rev = 0,
1802 .funcs = &cik_ih_ip_funcs,
1803 },
1804 {
1805 .type = AMD_IP_BLOCK_TYPE_SMC,
1806 .major = 7,
1807 .minor = 0,
1808 .rev = 0,
1809 .funcs = &amdgpu_pp_ip_funcs,
1810 },
1811 {
1812 .type = AMD_IP_BLOCK_TYPE_DCE,
1813 .major = 8,
1814 .minor = 5,
1815 .rev = 0,
1816 .funcs = &dce_v8_0_ip_funcs,
1817 },
1818 {
1819 .type = AMD_IP_BLOCK_TYPE_GFX,
1820 .major = 7,
1821 .minor = 3,
1822 .rev = 0,
1823 .funcs = &gfx_v7_0_ip_funcs,
1824 },
1825 {
1826 .type = AMD_IP_BLOCK_TYPE_SDMA,
1827 .major = 2,
1828 .minor = 0,
1829 .rev = 0,
1830 .funcs = &cik_sdma_ip_funcs,
1831 },
1832 {
1833 .type = AMD_IP_BLOCK_TYPE_UVD,
1834 .major = 4,
1835 .minor = 2,
1836 .rev = 0,
1837 .funcs = &uvd_v4_2_ip_funcs,
1838 },
1839 {
1840 .type = AMD_IP_BLOCK_TYPE_VCE,
1841 .major = 2,
1842 .minor = 0,
1843 .rev = 0,
1844 .funcs = &vce_v2_0_ip_funcs,
1845 },
1846};
1847
1848static const struct amdgpu_ip_block_version hawaii_ip_blocks_vd[] =
1849{
1850 /* ORDER MATTERS! */
1851 {
1852 .type = AMD_IP_BLOCK_TYPE_COMMON,
1853 .major = 1,
1854 .minor = 0,
1855 .rev = 0,
1856 .funcs = &cik_common_ip_funcs,
1857 },
1858 {
1859 .type = AMD_IP_BLOCK_TYPE_GMC,
1860 .major = 7,
1861 .minor = 0,
1862 .rev = 0,
1863 .funcs = &gmc_v7_0_ip_funcs,
1864 },
1865 {
1866 .type = AMD_IP_BLOCK_TYPE_IH,
1867 .major = 2,
1868 .minor = 0,
1869 .rev = 0,
1870 .funcs = &cik_ih_ip_funcs,
1871 },
1872 {
1873 .type = AMD_IP_BLOCK_TYPE_SMC,
1874 .major = 7,
1875 .minor = 0,
1876 .rev = 0,
1877 .funcs = &amdgpu_pp_ip_funcs,
1878 },
1879 {
1880 .type = AMD_IP_BLOCK_TYPE_DCE,
1881 .major = 8,
1882 .minor = 5,
1883 .rev = 0,
1884 .funcs = &dce_virtual_ip_funcs,
1885 },
1886 {
1887 .type = AMD_IP_BLOCK_TYPE_GFX,
1888 .major = 7,
1889 .minor = 3,
1890 .rev = 0,
1891 .funcs = &gfx_v7_0_ip_funcs,
1892 },
1893 {
1894 .type = AMD_IP_BLOCK_TYPE_SDMA,
1895 .major = 2,
1896 .minor = 0,
1897 .rev = 0,
1898 .funcs = &cik_sdma_ip_funcs,
1899 },
1900 {
1901 .type = AMD_IP_BLOCK_TYPE_UVD,
1902 .major = 4,
1903 .minor = 2,
1904 .rev = 0,
1905 .funcs = &uvd_v4_2_ip_funcs,
1906 },
1907 {
1908 .type = AMD_IP_BLOCK_TYPE_VCE,
1909 .major = 2,
1910 .minor = 0,
1911 .rev = 0,
1912 .funcs = &vce_v2_0_ip_funcs,
1913 },
1914};
1915
1916static const struct amdgpu_ip_block_version kabini_ip_blocks[] =
1917{
1918 /* ORDER MATTERS! */
1919 {
1920 .type = AMD_IP_BLOCK_TYPE_COMMON,
1921 .major = 1,
1922 .minor = 0,
1923 .rev = 0,
1924 .funcs = &cik_common_ip_funcs,
1925 },
1926 {
1927 .type = AMD_IP_BLOCK_TYPE_GMC,
1928 .major = 7,
1929 .minor = 0,
1930 .rev = 0,
1931 .funcs = &gmc_v7_0_ip_funcs,
1932 },
1933 {
1934 .type = AMD_IP_BLOCK_TYPE_IH,
1935 .major = 2,
1936 .minor = 0,
1937 .rev = 0,
1938 .funcs = &cik_ih_ip_funcs,
1939 },
1940 {
1941 .type = AMD_IP_BLOCK_TYPE_SMC,
1942 .major = 7,
1943 .minor = 0,
1944 .rev = 0,
1945 .funcs = &amdgpu_pp_ip_funcs,
1946 },
1947 {
1948 .type = AMD_IP_BLOCK_TYPE_DCE,
1949 .major = 8,
1950 .minor = 3,
1951 .rev = 0,
1952 .funcs = &dce_v8_0_ip_funcs,
1953 },
1954 {
1955 .type = AMD_IP_BLOCK_TYPE_GFX,
1956 .major = 7,
1957 .minor = 2,
1958 .rev = 0,
1959 .funcs = &gfx_v7_0_ip_funcs,
1960 },
1961 {
1962 .type = AMD_IP_BLOCK_TYPE_SDMA,
1963 .major = 2,
1964 .minor = 0,
1965 .rev = 0,
1966 .funcs = &cik_sdma_ip_funcs,
1967 },
1968 {
1969 .type = AMD_IP_BLOCK_TYPE_UVD,
1970 .major = 4,
1971 .minor = 2,
1972 .rev = 0,
1973 .funcs = &uvd_v4_2_ip_funcs,
1974 },
1975 {
1976 .type = AMD_IP_BLOCK_TYPE_VCE,
1977 .major = 2,
1978 .minor = 0,
1979 .rev = 0,
1980 .funcs = &vce_v2_0_ip_funcs,
1981 },
1982};
1983
1984static const struct amdgpu_ip_block_version kabini_ip_blocks_vd[] =
1985{
1986 /* ORDER MATTERS! */
1987 {
1988 .type = AMD_IP_BLOCK_TYPE_COMMON,
1989 .major = 1,
1990 .minor = 0,
1991 .rev = 0,
1992 .funcs = &cik_common_ip_funcs,
1993 },
1994 {
1995 .type = AMD_IP_BLOCK_TYPE_GMC,
1996 .major = 7,
1997 .minor = 0,
1998 .rev = 0,
1999 .funcs = &gmc_v7_0_ip_funcs,
2000 },
2001 {
2002 .type = AMD_IP_BLOCK_TYPE_IH,
2003 .major = 2,
2004 .minor = 0,
2005 .rev = 0,
2006 .funcs = &cik_ih_ip_funcs,
2007 },
2008 {
2009 .type = AMD_IP_BLOCK_TYPE_SMC,
2010 .major = 7,
2011 .minor = 0,
2012 .rev = 0,
2013 .funcs = &amdgpu_pp_ip_funcs,
2014 },
2015 {
2016 .type = AMD_IP_BLOCK_TYPE_DCE,
2017 .major = 8,
2018 .minor = 3,
2019 .rev = 0,
2020 .funcs = &dce_virtual_ip_funcs,
2021 },
2022 {
2023 .type = AMD_IP_BLOCK_TYPE_GFX,
2024 .major = 7,
2025 .minor = 2,
2026 .rev = 0,
2027 .funcs = &gfx_v7_0_ip_funcs,
2028 },
2029 {
2030 .type = AMD_IP_BLOCK_TYPE_SDMA,
2031 .major = 2,
2032 .minor = 0,
2033 .rev = 0,
2034 .funcs = &cik_sdma_ip_funcs,
2035 },
2036 {
2037 .type = AMD_IP_BLOCK_TYPE_UVD,
2038 .major = 4,
2039 .minor = 2,
2040 .rev = 0,
2041 .funcs = &uvd_v4_2_ip_funcs,
2042 },
2043 {
2044 .type = AMD_IP_BLOCK_TYPE_VCE,
2045 .major = 2,
2046 .minor = 0,
2047 .rev = 0,
2048 .funcs = &vce_v2_0_ip_funcs,
2049 },
2050};
2051
2052static const struct amdgpu_ip_block_version mullins_ip_blocks[] =
2053{
2054 /* ORDER MATTERS! */
2055 {
2056 .type = AMD_IP_BLOCK_TYPE_COMMON,
2057 .major = 1,
2058 .minor = 0,
2059 .rev = 0,
2060 .funcs = &cik_common_ip_funcs,
2061 },
2062 {
2063 .type = AMD_IP_BLOCK_TYPE_GMC,
2064 .major = 7,
2065 .minor = 0,
2066 .rev = 0,
2067 .funcs = &gmc_v7_0_ip_funcs,
2068 },
2069 {
2070 .type = AMD_IP_BLOCK_TYPE_IH,
2071 .major = 2,
2072 .minor = 0,
2073 .rev = 0,
2074 .funcs = &cik_ih_ip_funcs,
2075 },
2076 {
2077 .type = AMD_IP_BLOCK_TYPE_SMC,
2078 .major = 7,
2079 .minor = 0,
2080 .rev = 0,
2081 .funcs = &amdgpu_pp_ip_funcs,
2082 },
2083 {
2084 .type = AMD_IP_BLOCK_TYPE_DCE,
2085 .major = 8,
2086 .minor = 3,
2087 .rev = 0,
2088 .funcs = &dce_v8_0_ip_funcs,
2089 },
2090 {
2091 .type = AMD_IP_BLOCK_TYPE_GFX,
2092 .major = 7,
2093 .minor = 2,
2094 .rev = 0,
2095 .funcs = &gfx_v7_0_ip_funcs,
2096 },
2097 {
2098 .type = AMD_IP_BLOCK_TYPE_SDMA,
2099 .major = 2,
2100 .minor = 0,
2101 .rev = 0,
2102 .funcs = &cik_sdma_ip_funcs,
2103 },
2104 {
2105 .type = AMD_IP_BLOCK_TYPE_UVD,
2106 .major = 4,
2107 .minor = 2,
2108 .rev = 0,
2109 .funcs = &uvd_v4_2_ip_funcs,
2110 },
2111 {
2112 .type = AMD_IP_BLOCK_TYPE_VCE,
2113 .major = 2,
2114 .minor = 0,
2115 .rev = 0,
2116 .funcs = &vce_v2_0_ip_funcs,
2117 },
2118};
2119
2120static const struct amdgpu_ip_block_version mullins_ip_blocks_vd[] =
2121{
2122 /* ORDER MATTERS! */
2123 {
2124 .type = AMD_IP_BLOCK_TYPE_COMMON,
2125 .major = 1,
2126 .minor = 0,
2127 .rev = 0,
2128 .funcs = &cik_common_ip_funcs,
2129 },
2130 {
2131 .type = AMD_IP_BLOCK_TYPE_GMC,
2132 .major = 7,
2133 .minor = 0,
2134 .rev = 0,
2135 .funcs = &gmc_v7_0_ip_funcs,
2136 },
2137 {
2138 .type = AMD_IP_BLOCK_TYPE_IH,
2139 .major = 2,
2140 .minor = 0,
2141 .rev = 0,
2142 .funcs = &cik_ih_ip_funcs,
2143 },
2144 {
2145 .type = AMD_IP_BLOCK_TYPE_SMC,
2146 .major = 7,
2147 .minor = 0,
2148 .rev = 0,
2149 .funcs = &amdgpu_pp_ip_funcs,
2150 },
2151 {
2152 .type = AMD_IP_BLOCK_TYPE_DCE,
2153 .major = 8,
2154 .minor = 3,
2155 .rev = 0,
2156 .funcs = &dce_virtual_ip_funcs,
2157 },
2158 {
2159 .type = AMD_IP_BLOCK_TYPE_GFX,
2160 .major = 7,
2161 .minor = 2,
2162 .rev = 0,
2163 .funcs = &gfx_v7_0_ip_funcs,
2164 },
2165 {
2166 .type = AMD_IP_BLOCK_TYPE_SDMA,
2167 .major = 2,
2168 .minor = 0,
2169 .rev = 0,
2170 .funcs = &cik_sdma_ip_funcs,
2171 },
2172 {
2173 .type = AMD_IP_BLOCK_TYPE_UVD,
2174 .major = 4,
2175 .minor = 2,
2176 .rev = 0,
2177 .funcs = &uvd_v4_2_ip_funcs,
2178 },
2179 {
2180 .type = AMD_IP_BLOCK_TYPE_VCE,
2181 .major = 2,
2182 .minor = 0,
2183 .rev = 0,
2184 .funcs = &vce_v2_0_ip_funcs,
2185 },
2186};
2187
2188static const struct amdgpu_ip_block_version kaveri_ip_blocks[] =
2189{
2190 /* ORDER MATTERS! */
2191 {
2192 .type = AMD_IP_BLOCK_TYPE_COMMON,
2193 .major = 1,
2194 .minor = 0,
2195 .rev = 0,
2196 .funcs = &cik_common_ip_funcs,
2197 },
2198 {
2199 .type = AMD_IP_BLOCK_TYPE_GMC,
2200 .major = 7,
2201 .minor = 0,
2202 .rev = 0,
2203 .funcs = &gmc_v7_0_ip_funcs,
2204 },
2205 {
2206 .type = AMD_IP_BLOCK_TYPE_IH,
2207 .major = 2,
2208 .minor = 0,
2209 .rev = 0,
2210 .funcs = &cik_ih_ip_funcs,
2211 },
2212 {
2213 .type = AMD_IP_BLOCK_TYPE_SMC,
2214 .major = 7,
2215 .minor = 0,
2216 .rev = 0,
2217 .funcs = &amdgpu_pp_ip_funcs,
2218 },
2219 {
2220 .type = AMD_IP_BLOCK_TYPE_DCE,
2221 .major = 8,
2222 .minor = 1,
2223 .rev = 0,
2224 .funcs = &dce_v8_0_ip_funcs,
2225 },
2226 {
2227 .type = AMD_IP_BLOCK_TYPE_GFX,
2228 .major = 7,
2229 .minor = 1,
2230 .rev = 0,
2231 .funcs = &gfx_v7_0_ip_funcs,
2232 },
2233 {
2234 .type = AMD_IP_BLOCK_TYPE_SDMA,
2235 .major = 2,
2236 .minor = 0,
2237 .rev = 0,
2238 .funcs = &cik_sdma_ip_funcs,
2239 },
2240 {
2241 .type = AMD_IP_BLOCK_TYPE_UVD,
2242 .major = 4,
2243 .minor = 2,
2244 .rev = 0,
2245 .funcs = &uvd_v4_2_ip_funcs,
2246 },
2247 {
2248 .type = AMD_IP_BLOCK_TYPE_VCE,
2249 .major = 2,
2250 .minor = 0,
2251 .rev = 0,
2252 .funcs = &vce_v2_0_ip_funcs,
2253 },
2254};
2255
2256static const struct amdgpu_ip_block_version kaveri_ip_blocks_vd[] =
2257{
2258 /* ORDER MATTERS! */
2259 {
2260 .type = AMD_IP_BLOCK_TYPE_COMMON,
2261 .major = 1,
2262 .minor = 0,
2263 .rev = 0,
2264 .funcs = &cik_common_ip_funcs,
2265 },
2266 {
2267 .type = AMD_IP_BLOCK_TYPE_GMC,
2268 .major = 7,
2269 .minor = 0,
2270 .rev = 0,
2271 .funcs = &gmc_v7_0_ip_funcs,
2272 },
2273 {
2274 .type = AMD_IP_BLOCK_TYPE_IH,
2275 .major = 2,
2276 .minor = 0,
2277 .rev = 0,
2278 .funcs = &cik_ih_ip_funcs,
2279 },
2280 {
2281 .type = AMD_IP_BLOCK_TYPE_SMC,
2282 .major = 7,
2283 .minor = 0,
2284 .rev = 0,
2285 .funcs = &amdgpu_pp_ip_funcs,
2286 },
2287 {
2288 .type = AMD_IP_BLOCK_TYPE_DCE,
2289 .major = 8,
2290 .minor = 1,
2291 .rev = 0,
2292 .funcs = &dce_virtual_ip_funcs,
2293 },
2294 {
2295 .type = AMD_IP_BLOCK_TYPE_GFX,
2296 .major = 7,
2297 .minor = 1,
2298 .rev = 0,
2299 .funcs = &gfx_v7_0_ip_funcs,
2300 },
2301 {
2302 .type = AMD_IP_BLOCK_TYPE_SDMA,
2303 .major = 2,
2304 .minor = 0,
2305 .rev = 0,
2306 .funcs = &cik_sdma_ip_funcs,
2307 },
2308 {
2309 .type = AMD_IP_BLOCK_TYPE_UVD,
2310 .major = 4,
2311 .minor = 2,
2312 .rev = 0,
2313 .funcs = &uvd_v4_2_ip_funcs,
2314 },
2315 {
2316 .type = AMD_IP_BLOCK_TYPE_VCE,
2317 .major = 2,
2318 .minor = 0,
2319 .rev = 0,
2320 .funcs = &vce_v2_0_ip_funcs,
2321 },
2322};
2323
2324int cik_set_ip_blocks(struct amdgpu_device *adev)
2325{
2326 if (adev->enable_virtual_display) {
2327 switch (adev->asic_type) {
2328 case CHIP_BONAIRE:
2329 adev->ip_blocks = bonaire_ip_blocks_vd;
2330 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks_vd);
2331 break;
2332 case CHIP_HAWAII:
2333 adev->ip_blocks = hawaii_ip_blocks_vd;
2334 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks_vd);
2335 break;
2336 case CHIP_KAVERI:
2337 adev->ip_blocks = kaveri_ip_blocks_vd;
2338 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks_vd);
2339 break;
2340 case CHIP_KABINI:
2341 adev->ip_blocks = kabini_ip_blocks_vd;
2342 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks_vd);
2343 break;
2344 case CHIP_MULLINS:
2345 adev->ip_blocks = mullins_ip_blocks_vd;
2346 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks_vd);
2347 break;
2348 default:
2349 /* FIXME: not supported yet */
2350 return -EINVAL;
2351 }
2352 } else {
2353 switch (adev->asic_type) {
2354 case CHIP_BONAIRE:
2355 adev->ip_blocks = bonaire_ip_blocks;
2356 adev->num_ip_blocks = ARRAY_SIZE(bonaire_ip_blocks);
2357 break;
2358 case CHIP_HAWAII:
2359 adev->ip_blocks = hawaii_ip_blocks;
2360 adev->num_ip_blocks = ARRAY_SIZE(hawaii_ip_blocks);
2361 break;
2362 case CHIP_KAVERI:
2363 adev->ip_blocks = kaveri_ip_blocks;
2364 adev->num_ip_blocks = ARRAY_SIZE(kaveri_ip_blocks);
2365 break;
2366 case CHIP_KABINI:
2367 adev->ip_blocks = kabini_ip_blocks;
2368 adev->num_ip_blocks = ARRAY_SIZE(kabini_ip_blocks);
2369 break;
2370 case CHIP_MULLINS:
2371 adev->ip_blocks = mullins_ip_blocks;
2372 adev->num_ip_blocks = ARRAY_SIZE(mullins_ip_blocks);
2373 break;
2374 default:
2375 /* FIXME: not supported yet */
2376 return -EINVAL;
2377 }
2378 }
2379
2380 return 0;
2381}
2382
2383static const struct amdgpu_asic_funcs cik_asic_funcs = 1633static const struct amdgpu_asic_funcs cik_asic_funcs =
2384{ 1634{
2385 .read_disabled_bios = &cik_read_disabled_bios, 1635 .read_disabled_bios = &cik_read_disabled_bios,
@@ -2612,7 +1862,7 @@ static int cik_common_set_powergating_state(void *handle,
2612 return 0; 1862 return 0;
2613} 1863}
2614 1864
2615const struct amd_ip_funcs cik_common_ip_funcs = { 1865static const struct amd_ip_funcs cik_common_ip_funcs = {
2616 .name = "cik_common", 1866 .name = "cik_common",
2617 .early_init = cik_common_early_init, 1867 .early_init = cik_common_early_init,
2618 .late_init = NULL, 1868 .late_init = NULL,
@@ -2628,3 +1878,79 @@ const struct amd_ip_funcs cik_common_ip_funcs = {
2628 .set_clockgating_state = cik_common_set_clockgating_state, 1878 .set_clockgating_state = cik_common_set_clockgating_state,
2629 .set_powergating_state = cik_common_set_powergating_state, 1879 .set_powergating_state = cik_common_set_powergating_state,
2630}; 1880};
1881
1882static const struct amdgpu_ip_block_version cik_common_ip_block =
1883{
1884 .type = AMD_IP_BLOCK_TYPE_COMMON,
1885 .major = 1,
1886 .minor = 0,
1887 .rev = 0,
1888 .funcs = &cik_common_ip_funcs,
1889};
1890
1891int cik_set_ip_blocks(struct amdgpu_device *adev)
1892{
1893 switch (adev->asic_type) {
1894 case CHIP_BONAIRE:
1895 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1896 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1897 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1898 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1899 if (adev->enable_virtual_display)
1900 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1901 else
1902 amdgpu_ip_block_add(adev, &dce_v8_2_ip_block);
1903 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
1904 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1905 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1906 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1907 break;
1908 case CHIP_HAWAII:
1909 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1910 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1911 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1912 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1913 if (adev->enable_virtual_display)
1914 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1915 else
1916 amdgpu_ip_block_add(adev, &dce_v8_5_ip_block);
1917 amdgpu_ip_block_add(adev, &gfx_v7_3_ip_block);
1918 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1919 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1920 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1921 break;
1922 case CHIP_KAVERI:
1923 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1924 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1925 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1926 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1927 if (adev->enable_virtual_display)
1928 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1929 else
1930 amdgpu_ip_block_add(adev, &dce_v8_1_ip_block);
1931 amdgpu_ip_block_add(adev, &gfx_v7_1_ip_block);
1932 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1933 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1934 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1935 break;
1936 case CHIP_KABINI:
1937 case CHIP_MULLINS:
1938 amdgpu_ip_block_add(adev, &cik_common_ip_block);
1939 amdgpu_ip_block_add(adev, &gmc_v7_0_ip_block);
1940 amdgpu_ip_block_add(adev, &cik_ih_ip_block);
1941 amdgpu_ip_block_add(adev, &amdgpu_pp_ip_block);
1942 if (adev->enable_virtual_display)
1943 amdgpu_ip_block_add(adev, &dce_virtual_ip_block);
1944 else
1945 amdgpu_ip_block_add(adev, &dce_v8_3_ip_block);
1946 amdgpu_ip_block_add(adev, &gfx_v7_2_ip_block);
1947 amdgpu_ip_block_add(adev, &cik_sdma_ip_block);
1948 amdgpu_ip_block_add(adev, &uvd_v4_2_ip_block);
1949 amdgpu_ip_block_add(adev, &vce_v2_0_ip_block);
1950 break;
1951 default:
1952 /* FIXME: not supported yet */
1953 return -EINVAL;
1954 }
1955 return 0;
1956}
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-02 02:48:58 -0400