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path: root/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/atombios_dp.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/atombios_dp.c775
1 files changed, 775 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_dp.c b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
new file mode 100644
index 000000000000..9ba0a7d5bc8e
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_dp.c
@@ -0,0 +1,775 @@
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 * Jerome Glisse
26 */
27#include <drm/drmP.h>
28#include <drm/amdgpu_drm.h>
29#include "amdgpu.h"
30
31#include "atom.h"
32#include "atom-bits.h"
33#include "atombios_encoders.h"
34#include "atombios_dp.h"
35#include "amdgpu_connectors.h"
36#include "amdgpu_atombios.h"
37#include <drm/drm_dp_helper.h>
38
39/* move these to drm_dp_helper.c/h */
40#define DP_LINK_CONFIGURATION_SIZE 9
41#define DP_DPCD_SIZE DP_RECEIVER_CAP_SIZE
42
43static char *voltage_names[] = {
44 "0.4V", "0.6V", "0.8V", "1.2V"
45};
46static char *pre_emph_names[] = {
47 "0dB", "3.5dB", "6dB", "9.5dB"
48};
49
50/***** amdgpu AUX functions *****/
51
52union aux_channel_transaction {
53 PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
54 PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
55};
56
57static int amdgpu_atombios_dp_process_aux_ch(struct amdgpu_i2c_chan *chan,
58 u8 *send, int send_bytes,
59 u8 *recv, int recv_size,
60 u8 delay, u8 *ack)
61{
62 struct drm_device *dev = chan->dev;
63 struct amdgpu_device *adev = dev->dev_private;
64 union aux_channel_transaction args;
65 int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
66 unsigned char *base;
67 int recv_bytes;
68 int r = 0;
69
70 memset(&args, 0, sizeof(args));
71
72 mutex_lock(&chan->mutex);
73
74 base = (unsigned char *)(adev->mode_info.atom_context->scratch + 1);
75
76 amdgpu_atombios_copy_swap(base, send, send_bytes, true);
77
78 args.v2.lpAuxRequest = cpu_to_le16((u16)(0 + 4));
79 args.v2.lpDataOut = cpu_to_le16((u16)(16 + 4));
80 args.v2.ucDataOutLen = 0;
81 args.v2.ucChannelID = chan->rec.i2c_id;
82 args.v2.ucDelay = delay / 10;
83 args.v2.ucHPD_ID = chan->rec.hpd;
84
85 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
86
87 *ack = args.v2.ucReplyStatus;
88
89 /* timeout */
90 if (args.v2.ucReplyStatus == 1) {
91 DRM_DEBUG_KMS("dp_aux_ch timeout\n");
92 r = -ETIMEDOUT;
93 goto done;
94 }
95
96 /* flags not zero */
97 if (args.v2.ucReplyStatus == 2) {
98 DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
99 r = -EIO;
100 goto done;
101 }
102
103 /* error */
104 if (args.v2.ucReplyStatus == 3) {
105 DRM_DEBUG_KMS("dp_aux_ch error\n");
106 r = -EIO;
107 goto done;
108 }
109
110 recv_bytes = args.v1.ucDataOutLen;
111 if (recv_bytes > recv_size)
112 recv_bytes = recv_size;
113
114 if (recv && recv_size)
115 amdgpu_atombios_copy_swap(recv, base + 16, recv_bytes, false);
116
117 r = recv_bytes;
118done:
119 mutex_unlock(&chan->mutex);
120
121 return r;
122}
123
124#define BARE_ADDRESS_SIZE 3
125#define HEADER_SIZE (BARE_ADDRESS_SIZE + 1)
126
127static ssize_t
128amdgpu_atombios_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
129{
130 struct amdgpu_i2c_chan *chan =
131 container_of(aux, struct amdgpu_i2c_chan, aux);
132 int ret;
133 u8 tx_buf[20];
134 size_t tx_size;
135 u8 ack, delay = 0;
136
137 if (WARN_ON(msg->size > 16))
138 return -E2BIG;
139
140 tx_buf[0] = msg->address & 0xff;
141 tx_buf[1] = msg->address >> 8;
142 tx_buf[2] = msg->request << 4;
143 tx_buf[3] = msg->size ? (msg->size - 1) : 0;
144
145 switch (msg->request & ~DP_AUX_I2C_MOT) {
146 case DP_AUX_NATIVE_WRITE:
147 case DP_AUX_I2C_WRITE:
148 /* tx_size needs to be 4 even for bare address packets since the atom
149 * table needs the info in tx_buf[3].
150 */
151 tx_size = HEADER_SIZE + msg->size;
152 if (msg->size == 0)
153 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
154 else
155 tx_buf[3] |= tx_size << 4;
156 memcpy(tx_buf + HEADER_SIZE, msg->buffer, msg->size);
157 ret = amdgpu_atombios_dp_process_aux_ch(chan,
158 tx_buf, tx_size, NULL, 0, delay, &ack);
159 if (ret >= 0)
160 /* Return payload size. */
161 ret = msg->size;
162 break;
163 case DP_AUX_NATIVE_READ:
164 case DP_AUX_I2C_READ:
165 /* tx_size needs to be 4 even for bare address packets since the atom
166 * table needs the info in tx_buf[3].
167 */
168 tx_size = HEADER_SIZE;
169 if (msg->size == 0)
170 tx_buf[3] |= BARE_ADDRESS_SIZE << 4;
171 else
172 tx_buf[3] |= tx_size << 4;
173 ret = amdgpu_atombios_dp_process_aux_ch(chan,
174 tx_buf, tx_size, msg->buffer, msg->size, delay, &ack);
175 break;
176 default:
177 ret = -EINVAL;
178 break;
179 }
180
181 if (ret >= 0)
182 msg->reply = ack >> 4;
183
184 return ret;
185}
186
187void amdgpu_atombios_dp_aux_init(struct amdgpu_connector *amdgpu_connector)
188{
189 int ret;
190
191 amdgpu_connector->ddc_bus->rec.hpd = amdgpu_connector->hpd.hpd;
192 amdgpu_connector->ddc_bus->aux.dev = amdgpu_connector->base.kdev;
193 amdgpu_connector->ddc_bus->aux.transfer = amdgpu_atombios_dp_aux_transfer;
194 ret = drm_dp_aux_register(&amdgpu_connector->ddc_bus->aux);
195 if (!ret)
196 amdgpu_connector->ddc_bus->has_aux = true;
197
198 WARN(ret, "drm_dp_aux_register_i2c_bus() failed with error %d\n", ret);
199}
200
201/***** general DP utility functions *****/
202
203#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_LEVEL_3
204#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPH_LEVEL_3
205
206static void amdgpu_atombios_dp_get_adjust_train(const u8 link_status[DP_LINK_STATUS_SIZE],
207 int lane_count,
208 u8 train_set[4])
209{
210 u8 v = 0;
211 u8 p = 0;
212 int lane;
213
214 for (lane = 0; lane < lane_count; lane++) {
215 u8 this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
216 u8 this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
217
218 DRM_DEBUG_KMS("requested signal parameters: lane %d voltage %s pre_emph %s\n",
219 lane,
220 voltage_names[this_v >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
221 pre_emph_names[this_p >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
222
223 if (this_v > v)
224 v = this_v;
225 if (this_p > p)
226 p = this_p;
227 }
228
229 if (v >= DP_VOLTAGE_MAX)
230 v |= DP_TRAIN_MAX_SWING_REACHED;
231
232 if (p >= DP_PRE_EMPHASIS_MAX)
233 p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
234
235 DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
236 voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
237 pre_emph_names[(p & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT]);
238
239 for (lane = 0; lane < 4; lane++)
240 train_set[lane] = v | p;
241}
242
243/* convert bits per color to bits per pixel */
244/* get bpc from the EDID */
245static int amdgpu_atombios_dp_convert_bpc_to_bpp(int bpc)
246{
247 if (bpc == 0)
248 return 24;
249 else
250 return bpc * 3;
251}
252
253/* get the max pix clock supported by the link rate and lane num */
254static int amdgpu_atombios_dp_get_max_dp_pix_clock(int link_rate,
255 int lane_num,
256 int bpp)
257{
258 return (link_rate * lane_num * 8) / bpp;
259}
260
261/***** amdgpu specific DP functions *****/
262
263/* First get the min lane# when low rate is used according to pixel clock
264 * (prefer low rate), second check max lane# supported by DP panel,
265 * if the max lane# < low rate lane# then use max lane# instead.
266 */
267static int amdgpu_atombios_dp_get_dp_lane_number(struct drm_connector *connector,
268 const u8 dpcd[DP_DPCD_SIZE],
269 int pix_clock)
270{
271 int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
272 int max_link_rate = drm_dp_max_link_rate(dpcd);
273 int max_lane_num = drm_dp_max_lane_count(dpcd);
274 int lane_num;
275 int max_dp_pix_clock;
276
277 for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
278 max_dp_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
279 if (pix_clock <= max_dp_pix_clock)
280 break;
281 }
282
283 return lane_num;
284}
285
286static int amdgpu_atombios_dp_get_dp_link_clock(struct drm_connector *connector,
287 const u8 dpcd[DP_DPCD_SIZE],
288 int pix_clock)
289{
290 int bpp = amdgpu_atombios_dp_convert_bpc_to_bpp(amdgpu_connector_get_monitor_bpc(connector));
291 int lane_num, max_pix_clock;
292
293 if (amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector) ==
294 ENCODER_OBJECT_ID_NUTMEG)
295 return 270000;
296
297 lane_num = amdgpu_atombios_dp_get_dp_lane_number(connector, dpcd, pix_clock);
298 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(162000, lane_num, bpp);
299 if (pix_clock <= max_pix_clock)
300 return 162000;
301 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(270000, lane_num, bpp);
302 if (pix_clock <= max_pix_clock)
303 return 270000;
304 if (amdgpu_connector_is_dp12_capable(connector)) {
305 max_pix_clock = amdgpu_atombios_dp_get_max_dp_pix_clock(540000, lane_num, bpp);
306 if (pix_clock <= max_pix_clock)
307 return 540000;
308 }
309
310 return drm_dp_max_link_rate(dpcd);
311}
312
313static u8 amdgpu_atombios_dp_encoder_service(struct amdgpu_device *adev,
314 int action, int dp_clock,
315 u8 ucconfig, u8 lane_num)
316{
317 DP_ENCODER_SERVICE_PARAMETERS args;
318 int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
319
320 memset(&args, 0, sizeof(args));
321 args.ucLinkClock = dp_clock / 10;
322 args.ucConfig = ucconfig;
323 args.ucAction = action;
324 args.ucLaneNum = lane_num;
325 args.ucStatus = 0;
326
327 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
328 return args.ucStatus;
329}
330
331u8 amdgpu_atombios_dp_get_sinktype(struct amdgpu_connector *amdgpu_connector)
332{
333 struct drm_device *dev = amdgpu_connector->base.dev;
334 struct amdgpu_device *adev = dev->dev_private;
335
336 return amdgpu_atombios_dp_encoder_service(adev, ATOM_DP_ACTION_GET_SINK_TYPE, 0,
337 amdgpu_connector->ddc_bus->rec.i2c_id, 0);
338}
339
340static void amdgpu_atombios_dp_probe_oui(struct amdgpu_connector *amdgpu_connector)
341{
342 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
343 u8 buf[3];
344
345 if (!(dig_connector->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
346 return;
347
348 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_SINK_OUI, buf, 3) == 3)
349 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
350 buf[0], buf[1], buf[2]);
351
352 if (drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_BRANCH_OUI, buf, 3) == 3)
353 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
354 buf[0], buf[1], buf[2]);
355}
356
357int amdgpu_atombios_dp_get_dpcd(struct amdgpu_connector *amdgpu_connector)
358{
359 struct amdgpu_connector_atom_dig *dig_connector = amdgpu_connector->con_priv;
360 u8 msg[DP_DPCD_SIZE];
361 int ret, i;
362
363 for (i = 0; i < 7; i++) {
364 ret = drm_dp_dpcd_read(&amdgpu_connector->ddc_bus->aux, DP_DPCD_REV, msg,
365 DP_DPCD_SIZE);
366 if (ret == DP_DPCD_SIZE) {
367 memcpy(dig_connector->dpcd, msg, DP_DPCD_SIZE);
368
369 DRM_DEBUG_KMS("DPCD: %*ph\n", (int)sizeof(dig_connector->dpcd),
370 dig_connector->dpcd);
371
372 amdgpu_atombios_dp_probe_oui(amdgpu_connector);
373
374 return 0;
375 }
376 }
377 dig_connector->dpcd[0] = 0;
378 return -EINVAL;
379}
380
381int amdgpu_atombios_dp_get_panel_mode(struct drm_encoder *encoder,
382 struct drm_connector *connector)
383{
384 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
385 struct amdgpu_connector_atom_dig *dig_connector;
386 int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
387 u16 dp_bridge = amdgpu_connector_encoder_get_dp_bridge_encoder_id(connector);
388 u8 tmp;
389
390 if (!amdgpu_connector->con_priv)
391 return panel_mode;
392
393 dig_connector = amdgpu_connector->con_priv;
394
395 if (dp_bridge != ENCODER_OBJECT_ID_NONE) {
396 /* DP bridge chips */
397 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
398 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
399 if (tmp & 1)
400 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
401 else if ((dp_bridge == ENCODER_OBJECT_ID_NUTMEG) ||
402 (dp_bridge == ENCODER_OBJECT_ID_TRAVIS))
403 panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
404 else
405 panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
406 }
407 } else if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
408 /* eDP */
409 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux,
410 DP_EDP_CONFIGURATION_CAP, &tmp) == 1) {
411 if (tmp & 1)
412 panel_mode = DP_PANEL_MODE_INTERNAL_DP2_MODE;
413 }
414 }
415
416 return panel_mode;
417}
418
419void amdgpu_atombios_dp_set_link_config(struct drm_connector *connector,
420 const struct drm_display_mode *mode)
421{
422 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
423 struct amdgpu_connector_atom_dig *dig_connector;
424
425 if (!amdgpu_connector->con_priv)
426 return;
427 dig_connector = amdgpu_connector->con_priv;
428
429 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
430 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
431 dig_connector->dp_clock =
432 amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
433 dig_connector->dp_lane_count =
434 amdgpu_atombios_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
435 }
436}
437
438int amdgpu_atombios_dp_mode_valid_helper(struct drm_connector *connector,
439 struct drm_display_mode *mode)
440{
441 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
442 struct amdgpu_connector_atom_dig *dig_connector;
443 int dp_clock;
444
445 if (!amdgpu_connector->con_priv)
446 return MODE_CLOCK_HIGH;
447 dig_connector = amdgpu_connector->con_priv;
448
449 dp_clock =
450 amdgpu_atombios_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
451
452 if ((dp_clock == 540000) &&
453 (!amdgpu_connector_is_dp12_capable(connector)))
454 return MODE_CLOCK_HIGH;
455
456 return MODE_OK;
457}
458
459bool amdgpu_atombios_dp_needs_link_train(struct amdgpu_connector *amdgpu_connector)
460{
461 u8 link_status[DP_LINK_STATUS_SIZE];
462 struct amdgpu_connector_atom_dig *dig = amdgpu_connector->con_priv;
463
464 if (drm_dp_dpcd_read_link_status(&amdgpu_connector->ddc_bus->aux, link_status)
465 <= 0)
466 return false;
467 if (drm_dp_channel_eq_ok(link_status, dig->dp_lane_count))
468 return false;
469 return true;
470}
471
472void amdgpu_atombios_dp_set_rx_power_state(struct drm_connector *connector,
473 u8 power_state)
474{
475 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
476 struct amdgpu_connector_atom_dig *dig_connector;
477
478 if (!amdgpu_connector->con_priv)
479 return;
480
481 dig_connector = amdgpu_connector->con_priv;
482
483 /* power up/down the sink */
484 if (dig_connector->dpcd[0] >= 0x11) {
485 drm_dp_dpcd_writeb(&amdgpu_connector->ddc_bus->aux,
486 DP_SET_POWER, power_state);
487 usleep_range(1000, 2000);
488 }
489}
490
491struct amdgpu_atombios_dp_link_train_info {
492 struct amdgpu_device *adev;
493 struct drm_encoder *encoder;
494 struct drm_connector *connector;
495 int dp_clock;
496 int dp_lane_count;
497 bool tp3_supported;
498 u8 dpcd[DP_RECEIVER_CAP_SIZE];
499 u8 train_set[4];
500 u8 link_status[DP_LINK_STATUS_SIZE];
501 u8 tries;
502 struct drm_dp_aux *aux;
503};
504
505static void
506amdgpu_atombios_dp_update_vs_emph(struct amdgpu_atombios_dp_link_train_info *dp_info)
507{
508 /* set the initial vs/emph on the source */
509 amdgpu_atombios_encoder_setup_dig_transmitter(dp_info->encoder,
510 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
511 0, dp_info->train_set[0]); /* sets all lanes at once */
512
513 /* set the vs/emph on the sink */
514 drm_dp_dpcd_write(dp_info->aux, DP_TRAINING_LANE0_SET,
515 dp_info->train_set, dp_info->dp_lane_count);
516}
517
518static void
519amdgpu_atombios_dp_set_tp(struct amdgpu_atombios_dp_link_train_info *dp_info, int tp)
520{
521 int rtp = 0;
522
523 /* set training pattern on the source */
524 switch (tp) {
525 case DP_TRAINING_PATTERN_1:
526 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
527 break;
528 case DP_TRAINING_PATTERN_2:
529 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
530 break;
531 case DP_TRAINING_PATTERN_3:
532 rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
533 break;
534 }
535 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder, rtp, 0);
536
537 /* enable training pattern on the sink */
538 drm_dp_dpcd_writeb(dp_info->aux, DP_TRAINING_PATTERN_SET, tp);
539}
540
541static int
542amdgpu_atombios_dp_link_train_init(struct amdgpu_atombios_dp_link_train_info *dp_info)
543{
544 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(dp_info->encoder);
545 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
546 u8 tmp;
547
548 /* power up the sink */
549 amdgpu_atombios_dp_set_rx_power_state(dp_info->connector, DP_SET_POWER_D0);
550
551 /* possibly enable downspread on the sink */
552 if (dp_info->dpcd[3] & 0x1)
553 drm_dp_dpcd_writeb(dp_info->aux,
554 DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
555 else
556 drm_dp_dpcd_writeb(dp_info->aux,
557 DP_DOWNSPREAD_CTRL, 0);
558
559 if (dig->panel_mode == DP_PANEL_MODE_INTERNAL_DP2_MODE)
560 drm_dp_dpcd_writeb(dp_info->aux, DP_EDP_CONFIGURATION_SET, 1);
561
562 /* set the lane count on the sink */
563 tmp = dp_info->dp_lane_count;
564 if (drm_dp_enhanced_frame_cap(dp_info->dpcd))
565 tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
566 drm_dp_dpcd_writeb(dp_info->aux, DP_LANE_COUNT_SET, tmp);
567
568 /* set the link rate on the sink */
569 tmp = drm_dp_link_rate_to_bw_code(dp_info->dp_clock);
570 drm_dp_dpcd_writeb(dp_info->aux, DP_LINK_BW_SET, tmp);
571
572 /* start training on the source */
573 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
574 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
575
576 /* disable the training pattern on the sink */
577 drm_dp_dpcd_writeb(dp_info->aux,
578 DP_TRAINING_PATTERN_SET,
579 DP_TRAINING_PATTERN_DISABLE);
580
581 return 0;
582}
583
584static int
585amdgpu_atombios_dp_link_train_finish(struct amdgpu_atombios_dp_link_train_info *dp_info)
586{
587 udelay(400);
588
589 /* disable the training pattern on the sink */
590 drm_dp_dpcd_writeb(dp_info->aux,
591 DP_TRAINING_PATTERN_SET,
592 DP_TRAINING_PATTERN_DISABLE);
593
594 /* disable the training pattern on the source */
595 amdgpu_atombios_encoder_setup_dig_encoder(dp_info->encoder,
596 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
597
598 return 0;
599}
600
601static int
602amdgpu_atombios_dp_link_train_cr(struct amdgpu_atombios_dp_link_train_info *dp_info)
603{
604 bool clock_recovery;
605 u8 voltage;
606 int i;
607
608 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
609 memset(dp_info->train_set, 0, 4);
610 amdgpu_atombios_dp_update_vs_emph(dp_info);
611
612 udelay(400);
613
614 /* clock recovery loop */
615 clock_recovery = false;
616 dp_info->tries = 0;
617 voltage = 0xff;
618 while (1) {
619 drm_dp_link_train_clock_recovery_delay(dp_info->dpcd);
620
621 if (drm_dp_dpcd_read_link_status(dp_info->aux,
622 dp_info->link_status) <= 0) {
623 DRM_ERROR("displayport link status failed\n");
624 break;
625 }
626
627 if (drm_dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
628 clock_recovery = true;
629 break;
630 }
631
632 for (i = 0; i < dp_info->dp_lane_count; i++) {
633 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
634 break;
635 }
636 if (i == dp_info->dp_lane_count) {
637 DRM_ERROR("clock recovery reached max voltage\n");
638 break;
639 }
640
641 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
642 ++dp_info->tries;
643 if (dp_info->tries == 5) {
644 DRM_ERROR("clock recovery tried 5 times\n");
645 break;
646 }
647 } else
648 dp_info->tries = 0;
649
650 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
651
652 /* Compute new train_set as requested by sink */
653 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
654 dp_info->train_set);
655
656 amdgpu_atombios_dp_update_vs_emph(dp_info);
657 }
658 if (!clock_recovery) {
659 DRM_ERROR("clock recovery failed\n");
660 return -1;
661 } else {
662 DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
663 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
664 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
665 DP_TRAIN_PRE_EMPHASIS_SHIFT);
666 return 0;
667 }
668}
669
670static int
671amdgpu_atombios_dp_link_train_ce(struct amdgpu_atombios_dp_link_train_info *dp_info)
672{
673 bool channel_eq;
674
675 if (dp_info->tp3_supported)
676 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
677 else
678 amdgpu_atombios_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
679
680 /* channel equalization loop */
681 dp_info->tries = 0;
682 channel_eq = false;
683 while (1) {
684 drm_dp_link_train_channel_eq_delay(dp_info->dpcd);
685
686 if (drm_dp_dpcd_read_link_status(dp_info->aux,
687 dp_info->link_status) <= 0) {
688 DRM_ERROR("displayport link status failed\n");
689 break;
690 }
691
692 if (drm_dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
693 channel_eq = true;
694 break;
695 }
696
697 /* Try 5 times */
698 if (dp_info->tries > 5) {
699 DRM_ERROR("channel eq failed: 5 tries\n");
700 break;
701 }
702
703 /* Compute new train_set as requested by sink */
704 amdgpu_atombios_dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count,
705 dp_info->train_set);
706
707 amdgpu_atombios_dp_update_vs_emph(dp_info);
708 dp_info->tries++;
709 }
710
711 if (!channel_eq) {
712 DRM_ERROR("channel eq failed\n");
713 return -1;
714 } else {
715 DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
716 dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
717 (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
718 >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
719 return 0;
720 }
721}
722
723void amdgpu_atombios_dp_link_train(struct drm_encoder *encoder,
724 struct drm_connector *connector)
725{
726 struct drm_device *dev = encoder->dev;
727 struct amdgpu_device *adev = dev->dev_private;
728 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
729 struct amdgpu_encoder_atom_dig *dig;
730 struct amdgpu_connector *amdgpu_connector;
731 struct amdgpu_connector_atom_dig *dig_connector;
732 struct amdgpu_atombios_dp_link_train_info dp_info;
733 u8 tmp;
734
735 if (!amdgpu_encoder->enc_priv)
736 return;
737 dig = amdgpu_encoder->enc_priv;
738
739 amdgpu_connector = to_amdgpu_connector(connector);
740 if (!amdgpu_connector->con_priv)
741 return;
742 dig_connector = amdgpu_connector->con_priv;
743
744 if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
745 (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
746 return;
747
748 if (drm_dp_dpcd_readb(&amdgpu_connector->ddc_bus->aux, DP_MAX_LANE_COUNT, &tmp)
749 == 1) {
750 if (tmp & DP_TPS3_SUPPORTED)
751 dp_info.tp3_supported = true;
752 else
753 dp_info.tp3_supported = false;
754 } else {
755 dp_info.tp3_supported = false;
756 }
757
758 memcpy(dp_info.dpcd, dig_connector->dpcd, DP_RECEIVER_CAP_SIZE);
759 dp_info.adev = adev;
760 dp_info.encoder = encoder;
761 dp_info.connector = connector;
762 dp_info.dp_lane_count = dig_connector->dp_lane_count;
763 dp_info.dp_clock = dig_connector->dp_clock;
764 dp_info.aux = &amdgpu_connector->ddc_bus->aux;
765
766 if (amdgpu_atombios_dp_link_train_init(&dp_info))
767 goto done;
768 if (amdgpu_atombios_dp_link_train_cr(&dp_info))
769 goto done;
770 if (amdgpu_atombios_dp_link_train_ce(&dp_info))
771 goto done;
772done:
773 if (amdgpu_atombios_dp_link_train_finish(&dp_info))
774 return;
775}
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-05 11:53:16 -0400