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path: root/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/atombios_crtc.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/atombios_crtc.c807
1 files changed, 807 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
new file mode 100644
index 000000000000..49aa35016653
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/atombios_crtc.c
@@ -0,0 +1,807 @@
1/*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/amdgpu_drm.h>
29#include <drm/drm_fixed.h>
30#include "amdgpu.h"
31#include "atom.h"
32#include "atom-bits.h"
33#include "atombios_encoders.h"
34#include "amdgpu_atombios.h"
35#include "amdgpu_pll.h"
36#include "amdgpu_connectors.h"
37
38void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc,
39 struct drm_display_mode *mode,
40 struct drm_display_mode *adjusted_mode)
41{
42 struct drm_device *dev = crtc->dev;
43 struct amdgpu_device *adev = dev->dev_private;
44 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
45 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
46 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
47 int a1, a2;
48
49 memset(&args, 0, sizeof(args));
50
51 args.ucCRTC = amdgpu_crtc->crtc_id;
52
53 switch (amdgpu_crtc->rmx_type) {
54 case RMX_CENTER:
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
59 break;
60 case RMX_ASPECT:
61 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
62 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
63
64 if (a1 > a2) {
65 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
66 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
67 } else if (a2 > a1) {
68 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
69 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
70 }
71 break;
72 case RMX_FULL:
73 default:
74 args.usOverscanRight = cpu_to_le16(amdgpu_crtc->h_border);
75 args.usOverscanLeft = cpu_to_le16(amdgpu_crtc->h_border);
76 args.usOverscanBottom = cpu_to_le16(amdgpu_crtc->v_border);
77 args.usOverscanTop = cpu_to_le16(amdgpu_crtc->v_border);
78 break;
79 }
80 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
81}
82
83void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc)
84{
85 struct drm_device *dev = crtc->dev;
86 struct amdgpu_device *adev = dev->dev_private;
87 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
88 ENABLE_SCALER_PS_ALLOCATION args;
89 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
90
91 memset(&args, 0, sizeof(args));
92
93 args.ucScaler = amdgpu_crtc->crtc_id;
94
95 switch (amdgpu_crtc->rmx_type) {
96 case RMX_FULL:
97 args.ucEnable = ATOM_SCALER_EXPANSION;
98 break;
99 case RMX_CENTER:
100 args.ucEnable = ATOM_SCALER_CENTER;
101 break;
102 case RMX_ASPECT:
103 args.ucEnable = ATOM_SCALER_EXPANSION;
104 break;
105 default:
106 args.ucEnable = ATOM_SCALER_DISABLE;
107 break;
108 }
109 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
110}
111
112void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock)
113{
114 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
115 struct drm_device *dev = crtc->dev;
116 struct amdgpu_device *adev = dev->dev_private;
117 int index =
118 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
119 ENABLE_CRTC_PS_ALLOCATION args;
120
121 memset(&args, 0, sizeof(args));
122
123 args.ucCRTC = amdgpu_crtc->crtc_id;
124 args.ucEnable = lock;
125
126 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
127}
128
129void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state)
130{
131 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
132 struct drm_device *dev = crtc->dev;
133 struct amdgpu_device *adev = dev->dev_private;
134 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
135 ENABLE_CRTC_PS_ALLOCATION args;
136
137 memset(&args, 0, sizeof(args));
138
139 args.ucCRTC = amdgpu_crtc->crtc_id;
140 args.ucEnable = state;
141
142 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
143}
144
145void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state)
146{
147 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
148 struct drm_device *dev = crtc->dev;
149 struct amdgpu_device *adev = dev->dev_private;
150 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
151 BLANK_CRTC_PS_ALLOCATION args;
152
153 memset(&args, 0, sizeof(args));
154
155 args.ucCRTC = amdgpu_crtc->crtc_id;
156 args.ucBlanking = state;
157
158 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
159}
160
161void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state)
162{
163 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
164 struct drm_device *dev = crtc->dev;
165 struct amdgpu_device *adev = dev->dev_private;
166 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
167 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
168
169 memset(&args, 0, sizeof(args));
170
171 args.ucDispPipeId = amdgpu_crtc->crtc_id;
172 args.ucEnable = state;
173
174 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
175}
176
177void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev)
178{
179 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
180 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
181
182 memset(&args, 0, sizeof(args));
183
184 args.ucEnable = ATOM_INIT;
185
186 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
187}
188
189void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc,
190 struct drm_display_mode *mode)
191{
192 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
193 struct drm_device *dev = crtc->dev;
194 struct amdgpu_device *adev = dev->dev_private;
195 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
196 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
197 u16 misc = 0;
198
199 memset(&args, 0, sizeof(args));
200 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (amdgpu_crtc->h_border * 2));
201 args.usH_Blanking_Time =
202 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (amdgpu_crtc->h_border * 2));
203 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (amdgpu_crtc->v_border * 2));
204 args.usV_Blanking_Time =
205 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (amdgpu_crtc->v_border * 2));
206 args.usH_SyncOffset =
207 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + amdgpu_crtc->h_border);
208 args.usH_SyncWidth =
209 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
210 args.usV_SyncOffset =
211 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + amdgpu_crtc->v_border);
212 args.usV_SyncWidth =
213 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
214 args.ucH_Border = amdgpu_crtc->h_border;
215 args.ucV_Border = amdgpu_crtc->v_border;
216
217 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
218 misc |= ATOM_VSYNC_POLARITY;
219 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
220 misc |= ATOM_HSYNC_POLARITY;
221 if (mode->flags & DRM_MODE_FLAG_CSYNC)
222 misc |= ATOM_COMPOSITESYNC;
223 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
224 misc |= ATOM_INTERLACE;
225 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
226 misc |= ATOM_DOUBLE_CLOCK_MODE;
227
228 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
229 args.ucCRTC = amdgpu_crtc->crtc_id;
230
231 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
232}
233
234union atom_enable_ss {
235 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
236 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
237 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
238};
239
240static void amdgpu_atombios_crtc_program_ss(struct amdgpu_device *adev,
241 int enable,
242 int pll_id,
243 int crtc_id,
244 struct amdgpu_atom_ss *ss)
245{
246 unsigned i;
247 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
248 union atom_enable_ss args;
249
250 if (enable) {
251 /* Don't mess with SS if percentage is 0 or external ss.
252 * SS is already disabled previously, and disabling it
253 * again can cause display problems if the pll is already
254 * programmed.
255 */
256 if (ss->percentage == 0)
257 return;
258 if (ss->type & ATOM_EXTERNAL_SS_MASK)
259 return;
260 } else {
261 for (i = 0; i < adev->mode_info.num_crtc; i++) {
262 if (adev->mode_info.crtcs[i] &&
263 adev->mode_info.crtcs[i]->enabled &&
264 i != crtc_id &&
265 pll_id == adev->mode_info.crtcs[i]->pll_id) {
266 /* one other crtc is using this pll don't turn
267 * off spread spectrum as it might turn off
268 * display on active crtc
269 */
270 return;
271 }
272 }
273 }
274
275 memset(&args, 0, sizeof(args));
276
277 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
278 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
279 switch (pll_id) {
280 case ATOM_PPLL1:
281 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
282 break;
283 case ATOM_PPLL2:
284 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
285 break;
286 case ATOM_DCPLL:
287 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
288 break;
289 case ATOM_PPLL_INVALID:
290 return;
291 }
292 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
293 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
294 args.v3.ucEnable = enable;
295
296 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
297}
298
299union adjust_pixel_clock {
300 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
301 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
302};
303
304static u32 amdgpu_atombios_crtc_adjust_pll(struct drm_crtc *crtc,
305 struct drm_display_mode *mode)
306{
307 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
308 struct drm_device *dev = crtc->dev;
309 struct amdgpu_device *adev = dev->dev_private;
310 struct drm_encoder *encoder = amdgpu_crtc->encoder;
311 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
312 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
313 u32 adjusted_clock = mode->clock;
314 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(encoder);
315 u32 dp_clock = mode->clock;
316 u32 clock = mode->clock;
317 int bpc = amdgpu_crtc->bpc;
318 bool is_duallink = amdgpu_dig_monitor_is_duallink(encoder, mode->clock);
319 union adjust_pixel_clock args;
320 u8 frev, crev;
321 int index;
322
323 amdgpu_crtc->pll_flags = AMDGPU_PLL_USE_FRAC_FB_DIV;
324
325 if ((amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
326 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
327 if (connector) {
328 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
329 struct amdgpu_connector_atom_dig *dig_connector =
330 amdgpu_connector->con_priv;
331
332 dp_clock = dig_connector->dp_clock;
333 }
334 }
335
336 /* use recommended ref_div for ss */
337 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
338 if (amdgpu_crtc->ss_enabled) {
339 if (amdgpu_crtc->ss.refdiv) {
340 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
341 amdgpu_crtc->pll_reference_div = amdgpu_crtc->ss.refdiv;
342 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
343 }
344 }
345 }
346
347 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
348 if (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
349 adjusted_clock = mode->clock * 2;
350 if (amdgpu_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
351 amdgpu_crtc->pll_flags |= AMDGPU_PLL_PREFER_CLOSEST_LOWER;
352 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
353 amdgpu_crtc->pll_flags |= AMDGPU_PLL_IS_LCD;
354
355
356 /* adjust pll for deep color modes */
357 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
358 switch (bpc) {
359 case 8:
360 default:
361 break;
362 case 10:
363 clock = (clock * 5) / 4;
364 break;
365 case 12:
366 clock = (clock * 3) / 2;
367 break;
368 case 16:
369 clock = clock * 2;
370 break;
371 }
372 }
373
374 /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
375 * accordingly based on the encoder/transmitter to work around
376 * special hw requirements.
377 */
378 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
379 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
380 &crev))
381 return adjusted_clock;
382
383 memset(&args, 0, sizeof(args));
384
385 switch (frev) {
386 case 1:
387 switch (crev) {
388 case 1:
389 case 2:
390 args.v1.usPixelClock = cpu_to_le16(clock / 10);
391 args.v1.ucTransmitterID = amdgpu_encoder->encoder_id;
392 args.v1.ucEncodeMode = encoder_mode;
393 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
394 args.v1.ucConfig |=
395 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
396
397 amdgpu_atom_execute_table(adev->mode_info.atom_context,
398 index, (uint32_t *)&args);
399 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
400 break;
401 case 3:
402 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
403 args.v3.sInput.ucTransmitterID = amdgpu_encoder->encoder_id;
404 args.v3.sInput.ucEncodeMode = encoder_mode;
405 args.v3.sInput.ucDispPllConfig = 0;
406 if (amdgpu_crtc->ss_enabled && amdgpu_crtc->ss.percentage)
407 args.v3.sInput.ucDispPllConfig |=
408 DISPPLL_CONFIG_SS_ENABLE;
409 if (ENCODER_MODE_IS_DP(encoder_mode)) {
410 args.v3.sInput.ucDispPllConfig |=
411 DISPPLL_CONFIG_COHERENT_MODE;
412 /* 16200 or 27000 */
413 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
414 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
415 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
416 if (dig->coherent_mode)
417 args.v3.sInput.ucDispPllConfig |=
418 DISPPLL_CONFIG_COHERENT_MODE;
419 if (is_duallink)
420 args.v3.sInput.ucDispPllConfig |=
421 DISPPLL_CONFIG_DUAL_LINK;
422 }
423 if (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
424 ENCODER_OBJECT_ID_NONE)
425 args.v3.sInput.ucExtTransmitterID =
426 amdgpu_encoder_get_dp_bridge_encoder_id(encoder);
427 else
428 args.v3.sInput.ucExtTransmitterID = 0;
429
430 amdgpu_atom_execute_table(adev->mode_info.atom_context,
431 index, (uint32_t *)&args);
432 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
433 if (args.v3.sOutput.ucRefDiv) {
434 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
435 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_REF_DIV;
436 amdgpu_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
437 }
438 if (args.v3.sOutput.ucPostDiv) {
439 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_FRAC_FB_DIV;
440 amdgpu_crtc->pll_flags |= AMDGPU_PLL_USE_POST_DIV;
441 amdgpu_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
442 }
443 break;
444 default:
445 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
446 return adjusted_clock;
447 }
448 break;
449 default:
450 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
451 return adjusted_clock;
452 }
453
454 return adjusted_clock;
455}
456
457union set_pixel_clock {
458 SET_PIXEL_CLOCK_PS_ALLOCATION base;
459 PIXEL_CLOCK_PARAMETERS v1;
460 PIXEL_CLOCK_PARAMETERS_V2 v2;
461 PIXEL_CLOCK_PARAMETERS_V3 v3;
462 PIXEL_CLOCK_PARAMETERS_V5 v5;
463 PIXEL_CLOCK_PARAMETERS_V6 v6;
464};
465
466/* on DCE5, make sure the voltage is high enough to support the
467 * required disp clk.
468 */
469void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev,
470 u32 dispclk)
471{
472 u8 frev, crev;
473 int index;
474 union set_pixel_clock args;
475
476 memset(&args, 0, sizeof(args));
477
478 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
479 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
480 &crev))
481 return;
482
483 switch (frev) {
484 case 1:
485 switch (crev) {
486 case 5:
487 /* if the default dcpll clock is specified,
488 * SetPixelClock provides the dividers
489 */
490 args.v5.ucCRTC = ATOM_CRTC_INVALID;
491 args.v5.usPixelClock = cpu_to_le16(dispclk);
492 args.v5.ucPpll = ATOM_DCPLL;
493 break;
494 case 6:
495 /* if the default dcpll clock is specified,
496 * SetPixelClock provides the dividers
497 */
498 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
499 args.v6.ucPpll = ATOM_EXT_PLL1;
500 break;
501 default:
502 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
503 return;
504 }
505 break;
506 default:
507 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
508 return;
509 }
510 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
511}
512
513static bool is_pixel_clock_source_from_pll(u32 encoder_mode, int pll_id)
514{
515 if (ENCODER_MODE_IS_DP(encoder_mode)) {
516 if (pll_id < ATOM_EXT_PLL1)
517 return true;
518 else
519 return false;
520 } else {
521 return true;
522 }
523}
524
525void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc,
526 u32 crtc_id,
527 int pll_id,
528 u32 encoder_mode,
529 u32 encoder_id,
530 u32 clock,
531 u32 ref_div,
532 u32 fb_div,
533 u32 frac_fb_div,
534 u32 post_div,
535 int bpc,
536 bool ss_enabled,
537 struct amdgpu_atom_ss *ss)
538{
539 struct drm_device *dev = crtc->dev;
540 struct amdgpu_device *adev = dev->dev_private;
541 u8 frev, crev;
542 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
543 union set_pixel_clock args;
544
545 memset(&args, 0, sizeof(args));
546
547 if (!amdgpu_atom_parse_cmd_header(adev->mode_info.atom_context, index, &frev,
548 &crev))
549 return;
550
551 switch (frev) {
552 case 1:
553 switch (crev) {
554 case 1:
555 if (clock == ATOM_DISABLE)
556 return;
557 args.v1.usPixelClock = cpu_to_le16(clock / 10);
558 args.v1.usRefDiv = cpu_to_le16(ref_div);
559 args.v1.usFbDiv = cpu_to_le16(fb_div);
560 args.v1.ucFracFbDiv = frac_fb_div;
561 args.v1.ucPostDiv = post_div;
562 args.v1.ucPpll = pll_id;
563 args.v1.ucCRTC = crtc_id;
564 args.v1.ucRefDivSrc = 1;
565 break;
566 case 2:
567 args.v2.usPixelClock = cpu_to_le16(clock / 10);
568 args.v2.usRefDiv = cpu_to_le16(ref_div);
569 args.v2.usFbDiv = cpu_to_le16(fb_div);
570 args.v2.ucFracFbDiv = frac_fb_div;
571 args.v2.ucPostDiv = post_div;
572 args.v2.ucPpll = pll_id;
573 args.v2.ucCRTC = crtc_id;
574 args.v2.ucRefDivSrc = 1;
575 break;
576 case 3:
577 args.v3.usPixelClock = cpu_to_le16(clock / 10);
578 args.v3.usRefDiv = cpu_to_le16(ref_div);
579 args.v3.usFbDiv = cpu_to_le16(fb_div);
580 args.v3.ucFracFbDiv = frac_fb_div;
581 args.v3.ucPostDiv = post_div;
582 args.v3.ucPpll = pll_id;
583 if (crtc_id == ATOM_CRTC2)
584 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
585 else
586 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
587 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
588 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
589 args.v3.ucTransmitterId = encoder_id;
590 args.v3.ucEncoderMode = encoder_mode;
591 break;
592 case 5:
593 args.v5.ucCRTC = crtc_id;
594 args.v5.usPixelClock = cpu_to_le16(clock / 10);
595 args.v5.ucRefDiv = ref_div;
596 args.v5.usFbDiv = cpu_to_le16(fb_div);
597 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
598 args.v5.ucPostDiv = post_div;
599 args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
600 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
601 (pll_id < ATOM_EXT_PLL1))
602 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
603 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
604 switch (bpc) {
605 case 8:
606 default:
607 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
608 break;
609 case 10:
610 /* yes this is correct, the atom define is wrong */
611 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
612 break;
613 case 12:
614 /* yes this is correct, the atom define is wrong */
615 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
616 break;
617 }
618 }
619 args.v5.ucTransmitterID = encoder_id;
620 args.v5.ucEncoderMode = encoder_mode;
621 args.v5.ucPpll = pll_id;
622 break;
623 case 6:
624 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
625 args.v6.ucRefDiv = ref_div;
626 args.v6.usFbDiv = cpu_to_le16(fb_div);
627 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
628 args.v6.ucPostDiv = post_div;
629 args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
630 if ((ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK)) &&
631 (pll_id < ATOM_EXT_PLL1) &&
632 !is_pixel_clock_source_from_pll(encoder_mode, pll_id))
633 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
634 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
635 switch (bpc) {
636 case 8:
637 default:
638 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
639 break;
640 case 10:
641 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
642 break;
643 case 12:
644 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
645 break;
646 case 16:
647 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
648 break;
649 }
650 }
651 args.v6.ucTransmitterID = encoder_id;
652 args.v6.ucEncoderMode = encoder_mode;
653 args.v6.ucPpll = pll_id;
654 break;
655 default:
656 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
657 return;
658 }
659 break;
660 default:
661 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
662 return;
663 }
664
665 amdgpu_atom_execute_table(adev->mode_info.atom_context, index, (uint32_t *)&args);
666}
667
668int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc,
669 struct drm_display_mode *mode)
670{
671 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
672 struct drm_device *dev = crtc->dev;
673 struct amdgpu_device *adev = dev->dev_private;
674 struct amdgpu_encoder *amdgpu_encoder =
675 to_amdgpu_encoder(amdgpu_crtc->encoder);
676 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
677
678 amdgpu_crtc->bpc = 8;
679 amdgpu_crtc->ss_enabled = false;
680
681 if ((amdgpu_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
682 (amdgpu_encoder_get_dp_bridge_encoder_id(amdgpu_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
683 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
684 struct drm_connector *connector =
685 amdgpu_get_connector_for_encoder(amdgpu_crtc->encoder);
686 struct amdgpu_connector *amdgpu_connector =
687 to_amdgpu_connector(connector);
688 struct amdgpu_connector_atom_dig *dig_connector =
689 amdgpu_connector->con_priv;
690 int dp_clock;
691
692 /* Assign mode clock for hdmi deep color max clock limit check */
693 amdgpu_connector->pixelclock_for_modeset = mode->clock;
694 amdgpu_crtc->bpc = amdgpu_connector_get_monitor_bpc(connector);
695
696 switch (encoder_mode) {
697 case ATOM_ENCODER_MODE_DP_MST:
698 case ATOM_ENCODER_MODE_DP:
699 /* DP/eDP */
700 dp_clock = dig_connector->dp_clock / 10;
701 amdgpu_crtc->ss_enabled =
702 amdgpu_atombios_get_asic_ss_info(adev, &amdgpu_crtc->ss,
703 ASIC_INTERNAL_SS_ON_DP,
704 dp_clock);
705 break;
706 case ATOM_ENCODER_MODE_LVDS:
707 amdgpu_crtc->ss_enabled =
708 amdgpu_atombios_get_asic_ss_info(adev,
709 &amdgpu_crtc->ss,
710 dig->lcd_ss_id,
711 mode->clock / 10);
712 break;
713 case ATOM_ENCODER_MODE_DVI:
714 amdgpu_crtc->ss_enabled =
715 amdgpu_atombios_get_asic_ss_info(adev,
716 &amdgpu_crtc->ss,
717 ASIC_INTERNAL_SS_ON_TMDS,
718 mode->clock / 10);
719 break;
720 case ATOM_ENCODER_MODE_HDMI:
721 amdgpu_crtc->ss_enabled =
722 amdgpu_atombios_get_asic_ss_info(adev,
723 &amdgpu_crtc->ss,
724 ASIC_INTERNAL_SS_ON_HDMI,
725 mode->clock / 10);
726 break;
727 default:
728 break;
729 }
730 }
731
732 /* adjust pixel clock as needed */
733 amdgpu_crtc->adjusted_clock = amdgpu_atombios_crtc_adjust_pll(crtc, mode);
734
735 return 0;
736}
737
738void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
739{
740 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
741 struct drm_device *dev = crtc->dev;
742 struct amdgpu_device *adev = dev->dev_private;
743 struct amdgpu_encoder *amdgpu_encoder =
744 to_amdgpu_encoder(amdgpu_crtc->encoder);
745 u32 pll_clock = mode->clock;
746 u32 clock = mode->clock;
747 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
748 struct amdgpu_pll *pll;
749 int encoder_mode = amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
750
751 /* pass the actual clock to amdgpu_atombios_crtc_program_pll for HDMI */
752 if ((encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
753 (amdgpu_crtc->bpc > 8))
754 clock = amdgpu_crtc->adjusted_clock;
755
756 switch (amdgpu_crtc->pll_id) {
757 case ATOM_PPLL1:
758 pll = &adev->clock.ppll[0];
759 break;
760 case ATOM_PPLL2:
761 pll = &adev->clock.ppll[1];
762 break;
763 case ATOM_PPLL0:
764 case ATOM_PPLL_INVALID:
765 default:
766 pll = &adev->clock.ppll[2];
767 break;
768 }
769
770 /* update pll params */
771 pll->flags = amdgpu_crtc->pll_flags;
772 pll->reference_div = amdgpu_crtc->pll_reference_div;
773 pll->post_div = amdgpu_crtc->pll_post_div;
774
775 amdgpu_pll_compute(pll, amdgpu_crtc->adjusted_clock, &pll_clock,
776 &fb_div, &frac_fb_div, &ref_div, &post_div);
777
778 amdgpu_atombios_crtc_program_ss(adev, ATOM_DISABLE, amdgpu_crtc->pll_id,
779 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
780
781 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
782 encoder_mode, amdgpu_encoder->encoder_id, clock,
783 ref_div, fb_div, frac_fb_div, post_div,
784 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
785
786 if (amdgpu_crtc->ss_enabled) {
787 /* calculate ss amount and step size */
788 u32 step_size;
789 u32 amount = (((fb_div * 10) + frac_fb_div) *
790 (u32)amdgpu_crtc->ss.percentage) /
791 (100 * (u32)amdgpu_crtc->ss.percentage_divider);
792 amdgpu_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
793 amdgpu_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
794 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
795 if (amdgpu_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
796 step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
797 (125 * 25 * pll->reference_freq / 100);
798 else
799 step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) /
800 (125 * 25 * pll->reference_freq / 100);
801 amdgpu_crtc->ss.step = step_size;
802
803 amdgpu_atombios_crtc_program_ss(adev, ATOM_ENABLE, amdgpu_crtc->pll_id,
804 amdgpu_crtc->crtc_id, &amdgpu_crtc->ss);
805 }
806}
807
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-05 16:18:04 -0400