diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c index 64e527b1c02f..27da13df2f11 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | |||
| @@ -121,8 +121,7 @@ int amdgpu_vcn_sw_init(struct amdgpu_device *adev) | |||
| 121 | version_major, version_minor, family_id); | 121 | version_major, version_minor, family_id); |
| 122 | } | 122 | } |
| 123 | 123 | ||
| 124 | bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE | 124 | bo_size = AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_CONTEXT_SIZE; |
| 125 | + AMDGPU_VCN_SESSION_SIZE * 40; | ||
| 126 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) | 125 | if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) |
| 127 | bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); | 126 | bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8); |
| 128 | r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, | 127 | r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, |
| @@ -263,7 +262,7 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, | |||
| 263 | 262 | ||
| 264 | ring = &adev->vcn.ring_dec; | 263 | ring = &adev->vcn.ring_dec; |
| 265 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, | 264 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, |
| 266 | lower_32_bits(ring->wptr) | 0x80000000); | 265 | RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2)); |
| 267 | SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, | 266 | SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, |
| 268 | UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, | 267 | UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, |
| 269 | UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); | 268 | UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); |
| @@ -309,18 +308,21 @@ static int amdgpu_vcn_pause_dpg_mode(struct amdgpu_device *adev, | |||
| 309 | /* Restore */ | 308 | /* Restore */ |
| 310 | ring = &adev->vcn.ring_jpeg; | 309 | ring = &adev->vcn.ring_jpeg; |
| 311 | WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); | 310 | WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0); |
| 312 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000001L | 0x00000002L); | 311 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, |
| 312 | UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK | | ||
| 313 | UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); | ||
| 313 | WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, | 314 | WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, |
| 314 | lower_32_bits(ring->gpu_addr)); | 315 | lower_32_bits(ring->gpu_addr)); |
| 315 | WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, | 316 | WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH, |
| 316 | upper_32_bits(ring->gpu_addr)); | 317 | upper_32_bits(ring->gpu_addr)); |
| 317 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); | 318 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr); |
| 318 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); | 319 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr); |
| 319 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, 0x00000002L); | 320 | WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL, |
| 321 | UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK); | ||
| 320 | 322 | ||
| 321 | ring = &adev->vcn.ring_dec; | 323 | ring = &adev->vcn.ring_dec; |
| 322 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, | 324 | WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, |
| 323 | lower_32_bits(ring->wptr) | 0x80000000); | 325 | RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2)); |
| 324 | SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, | 326 | SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, |
| 325 | UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, | 327 | UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON, |
| 326 | UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); | 328 | UVD_POWER_STATUS__UVD_POWER_STATUS_MASK, ret_code); |