diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c')
-rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | 40 |
1 files changed, 13 insertions, 27 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c index 1df6b03a3680..bf462c59cb76 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/module.h> | 26 | #include <linux/module.h> |
27 | #include "amdgpu.h" | 27 | #include "amdgpu.h" |
28 | #include "amdgpu_ras.h" | 28 | #include "amdgpu_ras.h" |
29 | #include "amdgpu_atomfirmware.h" | ||
29 | 30 | ||
30 | struct ras_ih_data { | 31 | struct ras_ih_data { |
31 | /* interrupt bottom half */ | 32 | /* interrupt bottom half */ |
@@ -1327,36 +1328,21 @@ static int amdgpu_ras_recovery_fini(struct amdgpu_device *adev) | |||
1327 | } | 1328 | } |
1328 | /* recovery end */ | 1329 | /* recovery end */ |
1329 | 1330 | ||
1330 | struct ras_DID_capability { | ||
1331 | u16 did; | ||
1332 | u8 rid; | ||
1333 | u32 capability; | ||
1334 | }; | ||
1335 | |||
1336 | static const struct ras_DID_capability supported_DID_array[] = { | ||
1337 | {0x66a0, 0x00, AMDGPU_RAS_BLOCK_MASK}, | ||
1338 | {0x66a0, 0x02, AMDGPU_RAS_BLOCK_MASK}, | ||
1339 | {0x66a1, 0x00, AMDGPU_RAS_BLOCK_MASK}, | ||
1340 | {0x66a1, 0x01, AMDGPU_RAS_BLOCK_MASK}, | ||
1341 | {0x66a1, 0x04, AMDGPU_RAS_BLOCK_MASK}, | ||
1342 | {0x66a3, 0x00, AMDGPU_RAS_BLOCK_MASK}, | ||
1343 | {0x66a7, 0x00, AMDGPU_RAS_BLOCK_MASK}, | ||
1344 | }; | ||
1345 | |||
1346 | static uint32_t amdgpu_ras_check_supported(struct amdgpu_device *adev) | 1331 | static uint32_t amdgpu_ras_check_supported(struct amdgpu_device *adev) |
1347 | { | 1332 | { |
1348 | /* TODO need check vbios table */ | 1333 | uint32_t supported = 0; |
1349 | int i; | ||
1350 | int did = adev->pdev->device; | ||
1351 | int rid = adev->pdev->revision; | ||
1352 | 1334 | ||
1353 | for (i = 0; i < ARRAY_SIZE(supported_DID_array); i++) { | 1335 | if (amdgpu_ras_enable == 0 || |
1354 | if (did == supported_DID_array[i].did && | 1336 | amdgpu_sriov_vf(adev) || |
1355 | rid == supported_DID_array[i].rid) { | 1337 | adev->asic_type != CHIP_VEGA20) |
1356 | return supported_DID_array[i].capability; | 1338 | return 0; |
1357 | } | 1339 | |
1340 | if (amdgpu_atomfirmware_mem_ecc_supported(adev) || | ||
1341 | amdgpu_atomfirmware_sram_ecc_supported(adev)) { | ||
1342 | supported = AMDGPU_RAS_BLOCK_MASK; | ||
1358 | } | 1343 | } |
1359 | return 0; | 1344 | |
1345 | return supported & amdgpu_ras_mask; | ||
1360 | } | 1346 | } |
1361 | 1347 | ||
1362 | int amdgpu_ras_init(struct amdgpu_device *adev) | 1348 | int amdgpu_ras_init(struct amdgpu_device *adev) |
@@ -1364,7 +1350,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) | |||
1364 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); | 1350 | struct amdgpu_ras *con = amdgpu_ras_get_context(adev); |
1365 | uint32_t supported = amdgpu_ras_check_supported(adev); | 1351 | uint32_t supported = amdgpu_ras_check_supported(adev); |
1366 | 1352 | ||
1367 | if (con || supported == 0) | 1353 | if (con) |
1368 | return 0; | 1354 | return 0; |
1369 | 1355 | ||
1370 | con = kmalloc(sizeof(struct amdgpu_ras) + | 1356 | con = kmalloc(sizeof(struct amdgpu_ras) + |