diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | 65 |
1 files changed, 53 insertions, 12 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h index 129209686848..8b8720e9c3f0 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.h | |||
| @@ -32,8 +32,10 @@ | |||
| 32 | #define PSP_CMD_BUFFER_SIZE 0x1000 | 32 | #define PSP_CMD_BUFFER_SIZE 0x1000 |
| 33 | #define PSP_ASD_SHARED_MEM_SIZE 0x4000 | 33 | #define PSP_ASD_SHARED_MEM_SIZE 0x4000 |
| 34 | #define PSP_1_MEG 0x100000 | 34 | #define PSP_1_MEG 0x100000 |
| 35 | #define PSP_TMR_SIZE 0x400000 | ||
| 35 | 36 | ||
| 36 | struct psp_context; | 37 | struct psp_context; |
| 38 | struct psp_xgmi_topology_info; | ||
| 37 | 39 | ||
| 38 | enum psp_ring_type | 40 | enum psp_ring_type |
| 39 | { | 41 | { |
| @@ -63,18 +65,27 @@ struct psp_funcs | |||
| 63 | int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, | 65 | int (*prep_cmd_buf)(struct amdgpu_firmware_info *ucode, |
| 64 | struct psp_gfx_cmd_resp *cmd); | 66 | struct psp_gfx_cmd_resp *cmd); |
| 65 | int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); | 67 | int (*ring_init)(struct psp_context *psp, enum psp_ring_type ring_type); |
| 66 | int (*ring_create)(struct psp_context *psp, enum psp_ring_type ring_type); | 68 | int (*ring_create)(struct psp_context *psp, |
| 69 | enum psp_ring_type ring_type); | ||
| 67 | int (*ring_stop)(struct psp_context *psp, | 70 | int (*ring_stop)(struct psp_context *psp, |
| 68 | enum psp_ring_type ring_type); | 71 | enum psp_ring_type ring_type); |
| 69 | int (*ring_destroy)(struct psp_context *psp, | 72 | int (*ring_destroy)(struct psp_context *psp, |
| 70 | enum psp_ring_type ring_type); | 73 | enum psp_ring_type ring_type); |
| 71 | int (*cmd_submit)(struct psp_context *psp, struct amdgpu_firmware_info *ucode, | 74 | int (*cmd_submit)(struct psp_context *psp, |
| 72 | uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, int index); | 75 | struct amdgpu_firmware_info *ucode, |
| 76 | uint64_t cmd_buf_mc_addr, uint64_t fence_mc_addr, | ||
| 77 | int index); | ||
| 73 | bool (*compare_sram_data)(struct psp_context *psp, | 78 | bool (*compare_sram_data)(struct psp_context *psp, |
| 74 | struct amdgpu_firmware_info *ucode, | 79 | struct amdgpu_firmware_info *ucode, |
| 75 | enum AMDGPU_UCODE_ID ucode_type); | 80 | enum AMDGPU_UCODE_ID ucode_type); |
| 76 | bool (*smu_reload_quirk)(struct psp_context *psp); | 81 | bool (*smu_reload_quirk)(struct psp_context *psp); |
| 77 | int (*mode1_reset)(struct psp_context *psp); | 82 | int (*mode1_reset)(struct psp_context *psp); |
| 83 | uint64_t (*xgmi_get_device_id)(struct psp_context *psp); | ||
| 84 | uint64_t (*xgmi_get_hive_id)(struct psp_context *psp); | ||
| 85 | int (*xgmi_get_topology_info)(struct psp_context *psp, int number_devices, | ||
| 86 | struct psp_xgmi_topology_info *topology); | ||
| 87 | int (*xgmi_set_topology_info)(struct psp_context *psp, int number_devices, | ||
| 88 | struct psp_xgmi_topology_info *topology); | ||
| 78 | }; | 89 | }; |
| 79 | 90 | ||
| 80 | struct psp_context | 91 | struct psp_context |
| @@ -83,11 +94,11 @@ struct psp_context | |||
| 83 | struct psp_ring km_ring; | 94 | struct psp_ring km_ring; |
| 84 | struct psp_gfx_cmd_resp *cmd; | 95 | struct psp_gfx_cmd_resp *cmd; |
| 85 | 96 | ||
| 86 | const struct psp_funcs *funcs; | 97 | const struct psp_funcs *funcs; |
| 87 | 98 | ||
| 88 | /* fence buffer */ | 99 | /* fence buffer */ |
| 89 | struct amdgpu_bo *fw_pri_bo; | 100 | struct amdgpu_bo *fw_pri_bo; |
| 90 | uint64_t fw_pri_mc_addr; | 101 | uint64_t fw_pri_mc_addr; |
| 91 | void *fw_pri_buf; | 102 | void *fw_pri_buf; |
| 92 | 103 | ||
| 93 | /* sos firmware */ | 104 | /* sos firmware */ |
| @@ -100,8 +111,8 @@ struct psp_context | |||
| 100 | uint8_t *sos_start_addr; | 111 | uint8_t *sos_start_addr; |
| 101 | 112 | ||
| 102 | /* tmr buffer */ | 113 | /* tmr buffer */ |
| 103 | struct amdgpu_bo *tmr_bo; | 114 | struct amdgpu_bo *tmr_bo; |
| 104 | uint64_t tmr_mc_addr; | 115 | uint64_t tmr_mc_addr; |
| 105 | void *tmr_buf; | 116 | void *tmr_buf; |
| 106 | 117 | ||
| 107 | /* asd firmware and buffer */ | 118 | /* asd firmware and buffer */ |
| @@ -110,13 +121,13 @@ struct psp_context | |||
| 110 | uint32_t asd_feature_version; | 121 | uint32_t asd_feature_version; |
| 111 | uint32_t asd_ucode_size; | 122 | uint32_t asd_ucode_size; |
| 112 | uint8_t *asd_start_addr; | 123 | uint8_t *asd_start_addr; |
| 113 | struct amdgpu_bo *asd_shared_bo; | 124 | struct amdgpu_bo *asd_shared_bo; |
| 114 | uint64_t asd_shared_mc_addr; | 125 | uint64_t asd_shared_mc_addr; |
| 115 | void *asd_shared_buf; | 126 | void *asd_shared_buf; |
| 116 | 127 | ||
| 117 | /* fence buffer */ | 128 | /* fence buffer */ |
| 118 | struct amdgpu_bo *fence_buf_bo; | 129 | struct amdgpu_bo *fence_buf_bo; |
| 119 | uint64_t fence_buf_mc_addr; | 130 | uint64_t fence_buf_mc_addr; |
| 120 | void *fence_buf; | 131 | void *fence_buf; |
| 121 | 132 | ||
| 122 | /* cmd buffer */ | 133 | /* cmd buffer */ |
| @@ -130,6 +141,23 @@ struct amdgpu_psp_funcs { | |||
| 130 | enum AMDGPU_UCODE_ID); | 141 | enum AMDGPU_UCODE_ID); |
| 131 | }; | 142 | }; |
| 132 | 143 | ||
| 144 | struct psp_xgmi_topology_info { | ||
| 145 | /* Generated by PSP to identify the GPU instance within xgmi connection */ | ||
| 146 | uint64_t device_id; | ||
| 147 | /* | ||
| 148 | * If all bits set to 0 , driver indicates it wants to retrieve the xgmi | ||
| 149 | * connection vector topology, but not access enable the connections | ||
| 150 | * if some or all bits are set to 1, driver indicates it want to retrieve the | ||
| 151 | * current xgmi topology and access enable the link to GPU[i] associated | ||
| 152 | * with the bit position in the vector. | ||
| 153 | * On return,: bits indicated which xgmi links are present/active depending | ||
| 154 | * on the value passed in. The relative bit offset for the relative GPU index | ||
| 155 | * within the hive is always marked active. | ||
| 156 | */ | ||
| 157 | uint32_t connection_mask; | ||
| 158 | uint32_t reserved; /* must be 0 */ | ||
| 159 | }; | ||
| 160 | |||
| 133 | #define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type)) | 161 | #define psp_prep_cmd_buf(ucode, type) (psp)->funcs->prep_cmd_buf((ucode), (type)) |
| 134 | #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) | 162 | #define psp_ring_init(psp, type) (psp)->funcs->ring_init((psp), (type)) |
| 135 | #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) | 163 | #define psp_ring_create(psp, type) (psp)->funcs->ring_create((psp), (type)) |
| @@ -149,6 +177,18 @@ struct amdgpu_psp_funcs { | |||
| 149 | ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) | 177 | ((psp)->funcs->smu_reload_quirk ? (psp)->funcs->smu_reload_quirk((psp)) : false) |
| 150 | #define psp_mode1_reset(psp) \ | 178 | #define psp_mode1_reset(psp) \ |
| 151 | ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) | 179 | ((psp)->funcs->mode1_reset ? (psp)->funcs->mode1_reset((psp)) : false) |
| 180 | #define psp_xgmi_get_device_id(psp) \ | ||
| 181 | ((psp)->funcs->xgmi_get_device_id ? (psp)->funcs->xgmi_get_device_id((psp)) : 0) | ||
| 182 | #define psp_xgmi_get_hive_id(psp) \ | ||
| 183 | ((psp)->funcs->xgmi_get_hive_id ? (psp)->funcs->xgmi_get_hive_id((psp)) : 0) | ||
| 184 | #define psp_xgmi_get_topology_info(psp, num_device, topology) \ | ||
| 185 | ((psp)->funcs->xgmi_get_topology_info ? \ | ||
| 186 | (psp)->funcs->xgmi_get_topology_info((psp), (num_device), (topology)) : -EINVAL) | ||
| 187 | #define psp_xgmi_set_topology_info(psp, num_device, topology) \ | ||
| 188 | ((psp)->funcs->xgmi_set_topology_info ? \ | ||
| 189 | (psp)->funcs->xgmi_set_topology_info((psp), (num_device), (topology)) : -EINVAL) | ||
| 190 | |||
| 191 | #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i)) | ||
| 152 | 192 | ||
| 153 | extern const struct amd_ip_funcs psp_ip_funcs; | 193 | extern const struct amd_ip_funcs psp_ip_funcs; |
| 154 | 194 | ||
| @@ -159,5 +199,6 @@ extern int psp_wait_for(struct psp_context *psp, uint32_t reg_index, | |||
| 159 | extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; | 199 | extern const struct amdgpu_ip_block_version psp_v10_0_ip_block; |
| 160 | 200 | ||
| 161 | int psp_gpu_reset(struct amdgpu_device *adev); | 201 | int psp_gpu_reset(struct amdgpu_device *adev); |
| 202 | extern const struct amdgpu_ip_block_version psp_v11_0_ip_block; | ||
| 162 | 203 | ||
| 163 | #endif | 204 | #endif |
