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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c288
1 files changed, 0 insertions, 288 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
deleted file mode 100644
index 5c2e2d5dc1ee..000000000000
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c
+++ /dev/null
@@ -1,288 +0,0 @@
1/*
2 * Copyright 2015 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25#include "atom.h"
26#include "amdgpu.h"
27#include "amd_shared.h"
28#include <linux/module.h>
29#include <linux/moduleparam.h>
30#include "amdgpu_pm.h"
31#include <drm/amdgpu_drm.h>
32#include "amdgpu_powerplay.h"
33#include "si_dpm.h"
34#include "cik_dpm.h"
35#include "vi_dpm.h"
36
37static int amdgpu_pp_early_init(void *handle)
38{
39 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
40 struct amd_powerplay *amd_pp;
41 int ret = 0;
42
43 amd_pp = &(adev->powerplay);
44 amd_pp->pp_handle = (void *)adev;
45
46 switch (adev->asic_type) {
47 case CHIP_POLARIS11:
48 case CHIP_POLARIS10:
49 case CHIP_POLARIS12:
50 case CHIP_TONGA:
51 case CHIP_FIJI:
52 case CHIP_TOPAZ:
53 case CHIP_CARRIZO:
54 case CHIP_STONEY:
55 case CHIP_VEGA10:
56 case CHIP_RAVEN:
57 amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
58 amd_pp->ip_funcs = &pp_ip_funcs;
59 amd_pp->pp_funcs = &pp_dpm_funcs;
60 break;
61 /* These chips don't have powerplay implemenations */
62#ifdef CONFIG_DRM_AMDGPU_SI
63 case CHIP_TAHITI:
64 case CHIP_PITCAIRN:
65 case CHIP_VERDE:
66 case CHIP_OLAND:
67 case CHIP_HAINAN:
68 amd_pp->ip_funcs = &si_dpm_ip_funcs;
69 amd_pp->pp_funcs = &si_dpm_funcs;
70 break;
71#endif
72#ifdef CONFIG_DRM_AMDGPU_CIK
73 case CHIP_BONAIRE:
74 case CHIP_HAWAII:
75 if (amdgpu_dpm == -1) {
76 amd_pp->ip_funcs = &ci_dpm_ip_funcs;
77 amd_pp->pp_funcs = &ci_dpm_funcs;
78 } else {
79 amd_pp->cgs_device = amdgpu_cgs_create_device(adev);
80 amd_pp->ip_funcs = &pp_ip_funcs;
81 amd_pp->pp_funcs = &pp_dpm_funcs;
82 }
83 break;
84 case CHIP_KABINI:
85 case CHIP_MULLINS:
86 case CHIP_KAVERI:
87 amd_pp->ip_funcs = &kv_dpm_ip_funcs;
88 amd_pp->pp_funcs = &kv_dpm_funcs;
89 break;
90#endif
91 default:
92 ret = -EINVAL;
93 break;
94 }
95
96 if (adev->powerplay.ip_funcs->early_init)
97 ret = adev->powerplay.ip_funcs->early_init(adev);
98
99 return ret;
100}
101
102
103static int amdgpu_pp_late_init(void *handle)
104{
105 int ret = 0;
106 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
107
108 if (adev->powerplay.ip_funcs->late_init)
109 ret = adev->powerplay.ip_funcs->late_init(
110 adev->powerplay.pp_handle);
111
112 return ret;
113}
114
115static int amdgpu_pp_sw_init(void *handle)
116{
117 int ret = 0;
118 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
119
120 if (adev->powerplay.ip_funcs->sw_init)
121 ret = adev->powerplay.ip_funcs->sw_init(
122 adev->powerplay.pp_handle);
123
124 return ret;
125}
126
127static int amdgpu_pp_sw_fini(void *handle)
128{
129 int ret = 0;
130 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
131
132 if (adev->powerplay.ip_funcs->sw_fini)
133 ret = adev->powerplay.ip_funcs->sw_fini(
134 adev->powerplay.pp_handle);
135 if (ret)
136 return ret;
137
138 return ret;
139}
140
141static int amdgpu_pp_hw_init(void *handle)
142{
143 int ret = 0;
144 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
145
146 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
147 amdgpu_ucode_init_bo(adev);
148
149 if (adev->powerplay.ip_funcs->hw_init)
150 ret = adev->powerplay.ip_funcs->hw_init(
151 adev->powerplay.pp_handle);
152
153 return ret;
154}
155
156static int amdgpu_pp_hw_fini(void *handle)
157{
158 int ret = 0;
159 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
160
161 if (adev->powerplay.ip_funcs->hw_fini)
162 ret = adev->powerplay.ip_funcs->hw_fini(
163 adev->powerplay.pp_handle);
164
165 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU)
166 amdgpu_ucode_fini_bo(adev);
167
168 return ret;
169}
170
171static void amdgpu_pp_late_fini(void *handle)
172{
173 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
174
175 if (adev->powerplay.ip_funcs->late_fini)
176 adev->powerplay.ip_funcs->late_fini(
177 adev->powerplay.pp_handle);
178
179 if (adev->powerplay.cgs_device)
180 amdgpu_cgs_destroy_device(adev->powerplay.cgs_device);
181}
182
183static int amdgpu_pp_suspend(void *handle)
184{
185 int ret = 0;
186 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
187
188 if (adev->powerplay.ip_funcs->suspend)
189 ret = adev->powerplay.ip_funcs->suspend(
190 adev->powerplay.pp_handle);
191 return ret;
192}
193
194static int amdgpu_pp_resume(void *handle)
195{
196 int ret = 0;
197 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
198
199 if (adev->powerplay.ip_funcs->resume)
200 ret = adev->powerplay.ip_funcs->resume(
201 adev->powerplay.pp_handle);
202 return ret;
203}
204
205static int amdgpu_pp_set_clockgating_state(void *handle,
206 enum amd_clockgating_state state)
207{
208 int ret = 0;
209 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
210
211 if (adev->powerplay.ip_funcs->set_clockgating_state)
212 ret = adev->powerplay.ip_funcs->set_clockgating_state(
213 adev->powerplay.pp_handle, state);
214 return ret;
215}
216
217static int amdgpu_pp_set_powergating_state(void *handle,
218 enum amd_powergating_state state)
219{
220 int ret = 0;
221 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
222
223 if (adev->powerplay.ip_funcs->set_powergating_state)
224 ret = adev->powerplay.ip_funcs->set_powergating_state(
225 adev->powerplay.pp_handle, state);
226 return ret;
227}
228
229
230static bool amdgpu_pp_is_idle(void *handle)
231{
232 bool ret = true;
233 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
234
235 if (adev->powerplay.ip_funcs->is_idle)
236 ret = adev->powerplay.ip_funcs->is_idle(
237 adev->powerplay.pp_handle);
238 return ret;
239}
240
241static int amdgpu_pp_wait_for_idle(void *handle)
242{
243 int ret = 0;
244 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
245
246 if (adev->powerplay.ip_funcs->wait_for_idle)
247 ret = adev->powerplay.ip_funcs->wait_for_idle(
248 adev->powerplay.pp_handle);
249 return ret;
250}
251
252static int amdgpu_pp_soft_reset(void *handle)
253{
254 int ret = 0;
255 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
256
257 if (adev->powerplay.ip_funcs->soft_reset)
258 ret = adev->powerplay.ip_funcs->soft_reset(
259 adev->powerplay.pp_handle);
260 return ret;
261}
262
263static const struct amd_ip_funcs amdgpu_pp_ip_funcs = {
264 .name = "amdgpu_powerplay",
265 .early_init = amdgpu_pp_early_init,
266 .late_init = amdgpu_pp_late_init,
267 .sw_init = amdgpu_pp_sw_init,
268 .sw_fini = amdgpu_pp_sw_fini,
269 .hw_init = amdgpu_pp_hw_init,
270 .hw_fini = amdgpu_pp_hw_fini,
271 .late_fini = amdgpu_pp_late_fini,
272 .suspend = amdgpu_pp_suspend,
273 .resume = amdgpu_pp_resume,
274 .is_idle = amdgpu_pp_is_idle,
275 .wait_for_idle = amdgpu_pp_wait_for_idle,
276 .soft_reset = amdgpu_pp_soft_reset,
277 .set_clockgating_state = amdgpu_pp_set_clockgating_state,
278 .set_powergating_state = amdgpu_pp_set_powergating_state,
279};
280
281const struct amdgpu_ip_block_version amdgpu_pp_ip_block =
282{
283 .type = AMD_IP_BLOCK_TYPE_SMC,
284 .major = 1,
285 .minor = 0,
286 .rev = 0,
287 .funcs = &amdgpu_pp_ip_funcs,
288};
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-12 20:58:03 -0400