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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c35
1 files changed, 0 insertions, 35 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
index 3e51e9c89f04..b7b16cb5ff0f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c
@@ -1720,18 +1720,6 @@ void amdgpu_dpm_enable_uvd(struct amdgpu_device *adev, bool enable)
1720 mutex_lock(&adev->pm.mutex); 1720 mutex_lock(&adev->pm.mutex);
1721 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable); 1721 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_UVD, !enable);
1722 mutex_unlock(&adev->pm.mutex); 1722 mutex_unlock(&adev->pm.mutex);
1723 } else {
1724 if (enable) {
1725 mutex_lock(&adev->pm.mutex);
1726 adev->pm.dpm.uvd_active = true;
1727 adev->pm.dpm.state = POWER_STATE_TYPE_INTERNAL_UVD;
1728 mutex_unlock(&adev->pm.mutex);
1729 } else {
1730 mutex_lock(&adev->pm.mutex);
1731 adev->pm.dpm.uvd_active = false;
1732 mutex_unlock(&adev->pm.mutex);
1733 }
1734 amdgpu_pm_compute_clocks(adev);
1735 } 1723 }
1736} 1724}
1737 1725
@@ -1742,29 +1730,6 @@ void amdgpu_dpm_enable_vce(struct amdgpu_device *adev, bool enable)
1742 mutex_lock(&adev->pm.mutex); 1730 mutex_lock(&adev->pm.mutex);
1743 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable); 1731 amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_VCE, !enable);
1744 mutex_unlock(&adev->pm.mutex); 1732 mutex_unlock(&adev->pm.mutex);
1745 } else {
1746 if (enable) {
1747 mutex_lock(&adev->pm.mutex);
1748 adev->pm.dpm.vce_active = true;
1749 /* XXX select vce level based on ring/task */
1750 adev->pm.dpm.vce_level = AMD_VCE_LEVEL_AC_ALL;
1751 mutex_unlock(&adev->pm.mutex);
1752 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1753 AMD_CG_STATE_UNGATE);
1754 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1755 AMD_PG_STATE_UNGATE);
1756 amdgpu_pm_compute_clocks(adev);
1757 } else {
1758 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1759 AMD_PG_STATE_GATE);
1760 amdgpu_device_ip_set_clockgating_state(adev, AMD_IP_BLOCK_TYPE_VCE,
1761 AMD_CG_STATE_GATE);
1762 mutex_lock(&adev->pm.mutex);
1763 adev->pm.dpm.vce_active = false;
1764 mutex_unlock(&adev->pm.mutex);
1765 amdgpu_pm_compute_clocks(adev);
1766 }
1767
1768 } 1733 }
1769} 1734}
1770 1735