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-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h586
1 files changed, 586 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
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index 000000000000..64efe5b52e65
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+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -0,0 +1,586 @@
1/*
2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Original Authors:
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
26 *
27 * Kernel port Author: Dave Airlie
28 */
29
30#ifndef AMDGPU_MODE_H
31#define AMDGPU_MODE_H
32
33#include <drm/drm_crtc.h>
34#include <drm/drm_edid.h>
35#include <drm/drm_dp_helper.h>
36#include <drm/drm_fixed.h>
37#include <drm/drm_crtc_helper.h>
38#include <drm/drm_plane_helper.h>
39#include <linux/i2c.h>
40#include <linux/i2c-algo-bit.h>
41
42struct amdgpu_bo;
43struct amdgpu_device;
44struct amdgpu_encoder;
45struct amdgpu_router;
46struct amdgpu_hpd;
47
48#define to_amdgpu_crtc(x) container_of(x, struct amdgpu_crtc, base)
49#define to_amdgpu_connector(x) container_of(x, struct amdgpu_connector, base)
50#define to_amdgpu_encoder(x) container_of(x, struct amdgpu_encoder, base)
51#define to_amdgpu_framebuffer(x) container_of(x, struct amdgpu_framebuffer, base)
52
53#define AMDGPU_MAX_HPD_PINS 6
54#define AMDGPU_MAX_CRTCS 6
55#define AMDGPU_MAX_AFMT_BLOCKS 7
56
57enum amdgpu_rmx_type {
58 RMX_OFF,
59 RMX_FULL,
60 RMX_CENTER,
61 RMX_ASPECT
62};
63
64enum amdgpu_underscan_type {
65 UNDERSCAN_OFF,
66 UNDERSCAN_ON,
67 UNDERSCAN_AUTO,
68};
69
70#define AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS 50
71#define AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS 10
72
73enum amdgpu_hpd_id {
74 AMDGPU_HPD_1 = 0,
75 AMDGPU_HPD_2,
76 AMDGPU_HPD_3,
77 AMDGPU_HPD_4,
78 AMDGPU_HPD_5,
79 AMDGPU_HPD_6,
80 AMDGPU_HPD_LAST,
81 AMDGPU_HPD_NONE = 0xff,
82};
83
84enum amdgpu_crtc_irq {
85 AMDGPU_CRTC_IRQ_VBLANK1 = 0,
86 AMDGPU_CRTC_IRQ_VBLANK2,
87 AMDGPU_CRTC_IRQ_VBLANK3,
88 AMDGPU_CRTC_IRQ_VBLANK4,
89 AMDGPU_CRTC_IRQ_VBLANK5,
90 AMDGPU_CRTC_IRQ_VBLANK6,
91 AMDGPU_CRTC_IRQ_VLINE1,
92 AMDGPU_CRTC_IRQ_VLINE2,
93 AMDGPU_CRTC_IRQ_VLINE3,
94 AMDGPU_CRTC_IRQ_VLINE4,
95 AMDGPU_CRTC_IRQ_VLINE5,
96 AMDGPU_CRTC_IRQ_VLINE6,
97 AMDGPU_CRTC_IRQ_LAST,
98 AMDGPU_CRTC_IRQ_NONE = 0xff
99};
100
101enum amdgpu_pageflip_irq {
102 AMDGPU_PAGEFLIP_IRQ_D1 = 0,
103 AMDGPU_PAGEFLIP_IRQ_D2,
104 AMDGPU_PAGEFLIP_IRQ_D3,
105 AMDGPU_PAGEFLIP_IRQ_D4,
106 AMDGPU_PAGEFLIP_IRQ_D5,
107 AMDGPU_PAGEFLIP_IRQ_D6,
108 AMDGPU_PAGEFLIP_IRQ_LAST,
109 AMDGPU_PAGEFLIP_IRQ_NONE = 0xff
110};
111
112enum amdgpu_flip_status {
113 AMDGPU_FLIP_NONE,
114 AMDGPU_FLIP_PENDING,
115 AMDGPU_FLIP_SUBMITTED
116};
117
118#define AMDGPU_MAX_I2C_BUS 16
119
120/* amdgpu gpio-based i2c
121 * 1. "mask" reg and bits
122 * grabs the gpio pins for software use
123 * 0=not held 1=held
124 * 2. "a" reg and bits
125 * output pin value
126 * 0=low 1=high
127 * 3. "en" reg and bits
128 * sets the pin direction
129 * 0=input 1=output
130 * 4. "y" reg and bits
131 * input pin value
132 * 0=low 1=high
133 */
134struct amdgpu_i2c_bus_rec {
135 bool valid;
136 /* id used by atom */
137 uint8_t i2c_id;
138 /* id used by atom */
139 enum amdgpu_hpd_id hpd;
140 /* can be used with hw i2c engine */
141 bool hw_capable;
142 /* uses multi-media i2c engine */
143 bool mm_i2c;
144 /* regs and bits */
145 uint32_t mask_clk_reg;
146 uint32_t mask_data_reg;
147 uint32_t a_clk_reg;
148 uint32_t a_data_reg;
149 uint32_t en_clk_reg;
150 uint32_t en_data_reg;
151 uint32_t y_clk_reg;
152 uint32_t y_data_reg;
153 uint32_t mask_clk_mask;
154 uint32_t mask_data_mask;
155 uint32_t a_clk_mask;
156 uint32_t a_data_mask;
157 uint32_t en_clk_mask;
158 uint32_t en_data_mask;
159 uint32_t y_clk_mask;
160 uint32_t y_data_mask;
161};
162
163#define AMDGPU_MAX_BIOS_CONNECTOR 16
164
165/* pll flags */
166#define AMDGPU_PLL_USE_BIOS_DIVS (1 << 0)
167#define AMDGPU_PLL_NO_ODD_POST_DIV (1 << 1)
168#define AMDGPU_PLL_USE_REF_DIV (1 << 2)
169#define AMDGPU_PLL_LEGACY (1 << 3)
170#define AMDGPU_PLL_PREFER_LOW_REF_DIV (1 << 4)
171#define AMDGPU_PLL_PREFER_HIGH_REF_DIV (1 << 5)
172#define AMDGPU_PLL_PREFER_LOW_FB_DIV (1 << 6)
173#define AMDGPU_PLL_PREFER_HIGH_FB_DIV (1 << 7)
174#define AMDGPU_PLL_PREFER_LOW_POST_DIV (1 << 8)
175#define AMDGPU_PLL_PREFER_HIGH_POST_DIV (1 << 9)
176#define AMDGPU_PLL_USE_FRAC_FB_DIV (1 << 10)
177#define AMDGPU_PLL_PREFER_CLOSEST_LOWER (1 << 11)
178#define AMDGPU_PLL_USE_POST_DIV (1 << 12)
179#define AMDGPU_PLL_IS_LCD (1 << 13)
180#define AMDGPU_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
181
182struct amdgpu_pll {
183 /* reference frequency */
184 uint32_t reference_freq;
185
186 /* fixed dividers */
187 uint32_t reference_div;
188 uint32_t post_div;
189
190 /* pll in/out limits */
191 uint32_t pll_in_min;
192 uint32_t pll_in_max;
193 uint32_t pll_out_min;
194 uint32_t pll_out_max;
195 uint32_t lcd_pll_out_min;
196 uint32_t lcd_pll_out_max;
197 uint32_t best_vco;
198
199 /* divider limits */
200 uint32_t min_ref_div;
201 uint32_t max_ref_div;
202 uint32_t min_post_div;
203 uint32_t max_post_div;
204 uint32_t min_feedback_div;
205 uint32_t max_feedback_div;
206 uint32_t min_frac_feedback_div;
207 uint32_t max_frac_feedback_div;
208
209 /* flags for the current clock */
210 uint32_t flags;
211
212 /* pll id */
213 uint32_t id;
214};
215
216struct amdgpu_i2c_chan {
217 struct i2c_adapter adapter;
218 struct drm_device *dev;
219 struct i2c_algo_bit_data bit;
220 struct amdgpu_i2c_bus_rec rec;
221 struct drm_dp_aux aux;
222 bool has_aux;
223 struct mutex mutex;
224};
225
226struct amdgpu_fbdev;
227
228struct amdgpu_afmt {
229 bool enabled;
230 int offset;
231 bool last_buffer_filled_status;
232 int id;
233 struct amdgpu_audio_pin *pin;
234};
235
236/*
237 * Audio
238 */
239struct amdgpu_audio_pin {
240 int channels;
241 int rate;
242 int bits_per_sample;
243 u8 status_bits;
244 u8 category_code;
245 u32 offset;
246 bool connected;
247 u32 id;
248};
249
250struct amdgpu_audio {
251 bool enabled;
252 struct amdgpu_audio_pin pin[AMDGPU_MAX_AFMT_BLOCKS];
253 int num_pins;
254};
255
256struct amdgpu_mode_mc_save {
257 u32 vga_render_control;
258 u32 vga_hdp_control;
259 bool crtc_enabled[AMDGPU_MAX_CRTCS];
260};
261
262struct amdgpu_display_funcs {
263 /* vga render */
264 void (*set_vga_render_state)(struct amdgpu_device *adev, bool render);
265 /* display watermarks */
266 void (*bandwidth_update)(struct amdgpu_device *adev);
267 /* get frame count */
268 u32 (*vblank_get_counter)(struct amdgpu_device *adev, int crtc);
269 /* wait for vblank */
270 void (*vblank_wait)(struct amdgpu_device *adev, int crtc);
271 /* is dce hung */
272 bool (*is_display_hung)(struct amdgpu_device *adev);
273 /* set backlight level */
274 void (*backlight_set_level)(struct amdgpu_encoder *amdgpu_encoder,
275 u8 level);
276 /* get backlight level */
277 u8 (*backlight_get_level)(struct amdgpu_encoder *amdgpu_encoder);
278 /* hotplug detect */
279 bool (*hpd_sense)(struct amdgpu_device *adev, enum amdgpu_hpd_id hpd);
280 void (*hpd_set_polarity)(struct amdgpu_device *adev,
281 enum amdgpu_hpd_id hpd);
282 u32 (*hpd_get_gpio_reg)(struct amdgpu_device *adev);
283 /* pageflipping */
284 void (*page_flip)(struct amdgpu_device *adev,
285 int crtc_id, u64 crtc_base);
286 int (*page_flip_get_scanoutpos)(struct amdgpu_device *adev, int crtc,
287 u32 *vbl, u32 *position);
288 /* display topology setup */
289 void (*add_encoder)(struct amdgpu_device *adev,
290 uint32_t encoder_enum,
291 uint32_t supported_device,
292 u16 caps);
293 void (*add_connector)(struct amdgpu_device *adev,
294 uint32_t connector_id,
295 uint32_t supported_device,
296 int connector_type,
297 struct amdgpu_i2c_bus_rec *i2c_bus,
298 uint16_t connector_object_id,
299 struct amdgpu_hpd *hpd,
300 struct amdgpu_router *router);
301 void (*stop_mc_access)(struct amdgpu_device *adev,
302 struct amdgpu_mode_mc_save *save);
303 void (*resume_mc_access)(struct amdgpu_device *adev,
304 struct amdgpu_mode_mc_save *save);
305};
306
307struct amdgpu_mode_info {
308 struct atom_context *atom_context;
309 struct card_info *atom_card_info;
310 bool mode_config_initialized;
311 struct amdgpu_crtc *crtcs[6];
312 struct amdgpu_afmt *afmt[7];
313 /* DVI-I properties */
314 struct drm_property *coherent_mode_property;
315 /* DAC enable load detect */
316 struct drm_property *load_detect_property;
317 /* underscan */
318 struct drm_property *underscan_property;
319 struct drm_property *underscan_hborder_property;
320 struct drm_property *underscan_vborder_property;
321 /* audio */
322 struct drm_property *audio_property;
323 /* FMT dithering */
324 struct drm_property *dither_property;
325 /* hardcoded DFP edid from BIOS */
326 struct edid *bios_hardcoded_edid;
327 int bios_hardcoded_edid_size;
328
329 /* pointer to fbdev info structure */
330 struct amdgpu_fbdev *rfbdev;
331 /* firmware flags */
332 u16 firmware_flags;
333 /* pointer to backlight encoder */
334 struct amdgpu_encoder *bl_encoder;
335 struct amdgpu_audio audio; /* audio stuff */
336 int num_crtc; /* number of crtcs */
337 int num_hpd; /* number of hpd pins */
338 int num_dig; /* number of dig blocks */
339 int disp_priority;
340 const struct amdgpu_display_funcs *funcs;
341};
342
343#define AMDGPU_MAX_BL_LEVEL 0xFF
344
345#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
346
347struct amdgpu_backlight_privdata {
348 struct amdgpu_encoder *encoder;
349 uint8_t negative;
350};
351
352#endif
353
354struct amdgpu_atom_ss {
355 uint16_t percentage;
356 uint16_t percentage_divider;
357 uint8_t type;
358 uint16_t step;
359 uint8_t delay;
360 uint8_t range;
361 uint8_t refdiv;
362 /* asic_ss */
363 uint16_t rate;
364 uint16_t amount;
365};
366
367struct amdgpu_crtc {
368 struct drm_crtc base;
369 int crtc_id;
370 u16 lut_r[256], lut_g[256], lut_b[256];
371 bool enabled;
372 bool can_tile;
373 uint32_t crtc_offset;
374 struct drm_gem_object *cursor_bo;
375 uint64_t cursor_addr;
376 int cursor_width;
377 int cursor_height;
378 int max_cursor_width;
379 int max_cursor_height;
380 enum amdgpu_rmx_type rmx_type;
381 u8 h_border;
382 u8 v_border;
383 fixed20_12 vsc;
384 fixed20_12 hsc;
385 struct drm_display_mode native_mode;
386 u32 pll_id;
387 /* page flipping */
388 struct workqueue_struct *pflip_queue;
389 struct amdgpu_flip_work *pflip_works;
390 enum amdgpu_flip_status pflip_status;
391 int deferred_flip_completion;
392 /* pll sharing */
393 struct amdgpu_atom_ss ss;
394 bool ss_enabled;
395 u32 adjusted_clock;
396 int bpc;
397 u32 pll_reference_div;
398 u32 pll_post_div;
399 u32 pll_flags;
400 struct drm_encoder *encoder;
401 struct drm_connector *connector;
402 /* for dpm */
403 u32 line_time;
404 u32 wm_low;
405 u32 wm_high;
406 struct drm_display_mode hw_mode;
407};
408
409struct amdgpu_encoder_atom_dig {
410 bool linkb;
411 /* atom dig */
412 bool coherent_mode;
413 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
414 /* atom lvds/edp */
415 uint32_t lcd_misc;
416 uint16_t panel_pwr_delay;
417 uint32_t lcd_ss_id;
418 /* panel mode */
419 struct drm_display_mode native_mode;
420 struct backlight_device *bl_dev;
421 int dpms_mode;
422 uint8_t backlight_level;
423 int panel_mode;
424 struct amdgpu_afmt *afmt;
425};
426
427struct amdgpu_encoder {
428 struct drm_encoder base;
429 uint32_t encoder_enum;
430 uint32_t encoder_id;
431 uint32_t devices;
432 uint32_t active_device;
433 uint32_t flags;
434 uint32_t pixel_clock;
435 enum amdgpu_rmx_type rmx_type;
436 enum amdgpu_underscan_type underscan_type;
437 uint32_t underscan_hborder;
438 uint32_t underscan_vborder;
439 struct drm_display_mode native_mode;
440 void *enc_priv;
441 int audio_polling_active;
442 bool is_ext_encoder;
443 u16 caps;
444};
445
446struct amdgpu_connector_atom_dig {
447 /* displayport */
448 u8 dpcd[DP_RECEIVER_CAP_SIZE];
449 u8 dp_sink_type;
450 int dp_clock;
451 int dp_lane_count;
452 bool edp_on;
453};
454
455struct amdgpu_gpio_rec {
456 bool valid;
457 u8 id;
458 u32 reg;
459 u32 mask;
460 u32 shift;
461};
462
463struct amdgpu_hpd {
464 enum amdgpu_hpd_id hpd;
465 u8 plugged_state;
466 struct amdgpu_gpio_rec gpio;
467};
468
469struct amdgpu_router {
470 u32 router_id;
471 struct amdgpu_i2c_bus_rec i2c_info;
472 u8 i2c_addr;
473 /* i2c mux */
474 bool ddc_valid;
475 u8 ddc_mux_type;
476 u8 ddc_mux_control_pin;
477 u8 ddc_mux_state;
478 /* clock/data mux */
479 bool cd_valid;
480 u8 cd_mux_type;
481 u8 cd_mux_control_pin;
482 u8 cd_mux_state;
483};
484
485enum amdgpu_connector_audio {
486 AMDGPU_AUDIO_DISABLE = 0,
487 AMDGPU_AUDIO_ENABLE = 1,
488 AMDGPU_AUDIO_AUTO = 2
489};
490
491enum amdgpu_connector_dither {
492 AMDGPU_FMT_DITHER_DISABLE = 0,
493 AMDGPU_FMT_DITHER_ENABLE = 1,
494};
495
496struct amdgpu_connector {
497 struct drm_connector base;
498 uint32_t connector_id;
499 uint32_t devices;
500 struct amdgpu_i2c_chan *ddc_bus;
501 /* some systems have an hdmi and vga port with a shared ddc line */
502 bool shared_ddc;
503 bool use_digital;
504 /* we need to mind the EDID between detect
505 and get modes due to analog/digital/tvencoder */
506 struct edid *edid;
507 void *con_priv;
508 bool dac_load_detect;
509 bool detected_by_load; /* if the connection status was determined by load */
510 uint16_t connector_object_id;
511 struct amdgpu_hpd hpd;
512 struct amdgpu_router router;
513 struct amdgpu_i2c_chan *router_bus;
514 enum amdgpu_connector_audio audio;
515 enum amdgpu_connector_dither dither;
516 unsigned pixelclock_for_modeset;
517};
518
519struct amdgpu_framebuffer {
520 struct drm_framebuffer base;
521 struct drm_gem_object *obj;
522};
523
524#define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
525 ((em) == ATOM_ENCODER_MODE_DP_MST))
526
527void amdgpu_link_encoder_connector(struct drm_device *dev);
528
529struct drm_connector *
530amdgpu_get_connector_for_encoder(struct drm_encoder *encoder);
531struct drm_connector *
532amdgpu_get_connector_for_encoder_init(struct drm_encoder *encoder);
533bool amdgpu_dig_monitor_is_duallink(struct drm_encoder *encoder,
534 u32 pixel_clock);
535
536u16 amdgpu_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
537struct drm_encoder *amdgpu_get_external_encoder(struct drm_encoder *encoder);
538
539bool amdgpu_ddc_probe(struct amdgpu_connector *amdgpu_connector, bool use_aux);
540
541void amdgpu_encoder_set_active_device(struct drm_encoder *encoder);
542
543int amdgpu_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
544 unsigned int flags,
545 int *vpos, int *hpos, ktime_t *stime,
546 ktime_t *etime);
547
548int amdgpu_framebuffer_init(struct drm_device *dev,
549 struct amdgpu_framebuffer *rfb,
550 struct drm_mode_fb_cmd2 *mode_cmd,
551 struct drm_gem_object *obj);
552
553int amdgpufb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
554
555void amdgpu_enc_destroy(struct drm_encoder *encoder);
556void amdgpu_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
557bool amdgpu_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
558 const struct drm_display_mode *mode,
559 struct drm_display_mode *adjusted_mode);
560void amdgpu_panel_mode_fixup(struct drm_encoder *encoder,
561 struct drm_display_mode *adjusted_mode);
562int amdgpu_crtc_idx_to_irq_type(struct amdgpu_device *adev, int crtc);
563
564/* fbdev layer */
565int amdgpu_fbdev_init(struct amdgpu_device *adev);
566void amdgpu_fbdev_fini(struct amdgpu_device *adev);
567void amdgpu_fbdev_set_suspend(struct amdgpu_device *adev, int state);
568int amdgpu_fbdev_total_size(struct amdgpu_device *adev);
569bool amdgpu_fbdev_robj_is_fb(struct amdgpu_device *adev, struct amdgpu_bo *robj);
570
571void amdgpu_fb_output_poll_changed(struct amdgpu_device *adev);
572
573
574int amdgpu_align_pitch(struct amdgpu_device *adev, int width, int bpp, bool tiled);
575
576/* amdgpu_display.c */
577void amdgpu_print_display_setup(struct drm_device *dev);
578int amdgpu_modeset_create_props(struct amdgpu_device *adev);
579int amdgpu_crtc_set_config(struct drm_mode_set *set);
580int amdgpu_crtc_page_flip(struct drm_crtc *crtc,
581 struct drm_framebuffer *fb,
582 struct drm_pending_vblank_event *event,
583 uint32_t page_flip_flags);
584extern const struct drm_mode_config_funcs amdgpu_mode_funcs;
585
586#endif
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