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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c19
1 files changed, 15 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index bc0fac618a3f..5104e64e9ad8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -88,6 +88,7 @@ int amdgpu_ib_get(struct amdgpu_ring *ring, struct amdgpu_vm *vm,
88 ib->fence = NULL; 88 ib->fence = NULL;
89 ib->user = NULL; 89 ib->user = NULL;
90 ib->vm = vm; 90 ib->vm = vm;
91 ib->ctx = NULL;
91 ib->gds_base = 0; 92 ib->gds_base = 0;
92 ib->gds_size = 0; 93 ib->gds_size = 0;
93 ib->gws_base = 0; 94 ib->gws_base = 0;
@@ -142,6 +143,7 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
142 struct amdgpu_ring *ring; 143 struct amdgpu_ring *ring;
143 struct amdgpu_ctx *ctx, *old_ctx; 144 struct amdgpu_ctx *ctx, *old_ctx;
144 struct amdgpu_vm *vm; 145 struct amdgpu_vm *vm;
146 uint64_t sequence;
145 unsigned i; 147 unsigned i;
146 int r = 0; 148 int r = 0;
147 149
@@ -165,9 +167,11 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
165 167
166 if (vm) { 168 if (vm) {
167 /* grab a vm id if necessary */ 169 /* grab a vm id if necessary */
168 struct amdgpu_fence *vm_id_fence = NULL; 170 r = amdgpu_vm_grab_id(ibs->vm, ibs->ring, &ibs->sync);
169 vm_id_fence = amdgpu_vm_grab_id(ibs->ring, ibs->vm); 171 if (r) {
170 amdgpu_sync_fence(&ibs->sync, vm_id_fence); 172 amdgpu_ring_unlock_undo(ring);
173 return r;
174 }
171 } 175 }
172 176
173 r = amdgpu_sync_rings(&ibs->sync, ring); 177 r = amdgpu_sync_rings(&ibs->sync, ring);
@@ -212,11 +216,18 @@ int amdgpu_ib_schedule(struct amdgpu_device *adev, unsigned num_ibs,
212 return r; 216 return r;
213 } 217 }
214 218
219 sequence = amdgpu_enable_scheduler ? ib->sequence : 0;
220
221 if (!amdgpu_enable_scheduler && ib->ctx)
222 ib->sequence = amdgpu_ctx_add_fence(ib->ctx, ring,
223 &ib->fence->base,
224 sequence);
225
215 /* wrap the last IB with fence */ 226 /* wrap the last IB with fence */
216 if (ib->user) { 227 if (ib->user) {
217 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo); 228 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
218 addr += ib->user->offset; 229 addr += ib->user->offset;
219 amdgpu_ring_emit_fence(ring, addr, ib->fence->seq, 230 amdgpu_ring_emit_fence(ring, addr, ib->sequence,
220 AMDGPU_FENCE_FLAG_64BIT); 231 AMDGPU_FENCE_FLAG_64BIT);
221 } 232 }
222 233