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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index ff3e9beb7d19..17a3ef297fd6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -38,6 +38,8 @@
38 38
39#include <linux/vga_switcheroo.h> 39#include <linux/vga_switcheroo.h>
40 40
41#include "amdgpu_display.h"
42
41/* object hierarchy - 43/* object hierarchy -
42 this contains a helper + a amdgpu fb 44 this contains a helper + a amdgpu fb
43 the helper contains a pointer to amdgpu framebuffer baseclass. 45 the helper contains a pointer to amdgpu framebuffer baseclass.
@@ -124,7 +126,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
124 struct drm_gem_object *gobj = NULL; 126 struct drm_gem_object *gobj = NULL;
125 struct amdgpu_bo *abo = NULL; 127 struct amdgpu_bo *abo = NULL;
126 bool fb_tiled = false; /* useful for testing */ 128 bool fb_tiled = false; /* useful for testing */
127 u32 tiling_flags = 0; 129 u32 tiling_flags = 0, domain;
128 int ret; 130 int ret;
129 int aligned_size, size; 131 int aligned_size, size;
130 int height = mode_cmd->height; 132 int height = mode_cmd->height;
@@ -135,12 +137,12 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
135 /* need to align pitch with crtc limits */ 137 /* need to align pitch with crtc limits */
136 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, 138 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
137 fb_tiled); 139 fb_tiled);
140 domain = amdgpu_display_framebuffer_domains(adev);
138 141
139 height = ALIGN(mode_cmd->height, 8); 142 height = ALIGN(mode_cmd->height, 8);
140 size = mode_cmd->pitches[0] * height; 143 size = mode_cmd->pitches[0] * height;
141 aligned_size = ALIGN(size, PAGE_SIZE); 144 aligned_size = ALIGN(size, PAGE_SIZE);
142 ret = amdgpu_gem_object_create(adev, aligned_size, 0, 145 ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
143 AMDGPU_GEM_DOMAIN_VRAM,
144 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 146 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
145 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | 147 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
146 AMDGPU_GEM_CREATE_VRAM_CLEARED, 148 AMDGPU_GEM_CREATE_VRAM_CLEARED,
@@ -166,7 +168,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
166 } 168 }
167 169
168 170
169 ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL); 171 ret = amdgpu_bo_pin(abo, domain, NULL);
170 if (ret) { 172 if (ret) {
171 amdgpu_bo_unreserve(abo); 173 amdgpu_bo_unreserve(abo);
172 goto out_unref; 174 goto out_unref;