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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c23
1 files changed, 13 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
index ff3e9beb7d19..12063019751b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_fb.c
@@ -38,6 +38,8 @@
38 38
39#include <linux/vga_switcheroo.h> 39#include <linux/vga_switcheroo.h>
40 40
41#include "amdgpu_display.h"
42
41/* object hierarchy - 43/* object hierarchy -
42 this contains a helper + a amdgpu fb 44 this contains a helper + a amdgpu fb
43 the helper contains a pointer to amdgpu framebuffer baseclass. 45 the helper contains a pointer to amdgpu framebuffer baseclass.
@@ -124,7 +126,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
124 struct drm_gem_object *gobj = NULL; 126 struct drm_gem_object *gobj = NULL;
125 struct amdgpu_bo *abo = NULL; 127 struct amdgpu_bo *abo = NULL;
126 bool fb_tiled = false; /* useful for testing */ 128 bool fb_tiled = false; /* useful for testing */
127 u32 tiling_flags = 0; 129 u32 tiling_flags = 0, domain;
128 int ret; 130 int ret;
129 int aligned_size, size; 131 int aligned_size, size;
130 int height = mode_cmd->height; 132 int height = mode_cmd->height;
@@ -135,12 +137,12 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
135 /* need to align pitch with crtc limits */ 137 /* need to align pitch with crtc limits */
136 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, 138 mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp,
137 fb_tiled); 139 fb_tiled);
140 domain = amdgpu_display_framebuffer_domains(adev);
138 141
139 height = ALIGN(mode_cmd->height, 8); 142 height = ALIGN(mode_cmd->height, 8);
140 size = mode_cmd->pitches[0] * height; 143 size = mode_cmd->pitches[0] * height;
141 aligned_size = ALIGN(size, PAGE_SIZE); 144 aligned_size = ALIGN(size, PAGE_SIZE);
142 ret = amdgpu_gem_object_create(adev, aligned_size, 0, 145 ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain,
143 AMDGPU_GEM_DOMAIN_VRAM,
144 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | 146 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
145 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | 147 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
146 AMDGPU_GEM_CREATE_VRAM_CLEARED, 148 AMDGPU_GEM_CREATE_VRAM_CLEARED,
@@ -166,7 +168,7 @@ static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev,
166 } 168 }
167 169
168 170
169 ret = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, NULL); 171 ret = amdgpu_bo_pin(abo, domain, NULL);
170 if (ret) { 172 if (ret) {
171 amdgpu_bo_unreserve(abo); 173 amdgpu_bo_unreserve(abo);
172 goto out_unref; 174 goto out_unref;
@@ -225,7 +227,8 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
225 info->par = rfbdev; 227 info->par = rfbdev;
226 info->skip_vt_switch = true; 228 info->skip_vt_switch = true;
227 229
228 ret = amdgpu_framebuffer_init(adev->ddev, &rfbdev->rfb, &mode_cmd, gobj); 230 ret = amdgpu_display_framebuffer_init(adev->ddev, &rfbdev->rfb,
231 &mode_cmd, gobj);
229 if (ret) { 232 if (ret) {
230 DRM_ERROR("failed to initialize framebuffer %d\n", ret); 233 DRM_ERROR("failed to initialize framebuffer %d\n", ret);
231 goto out; 234 goto out;
@@ -242,8 +245,8 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
242 245
243 info->fbops = &amdgpufb_ops; 246 info->fbops = &amdgpufb_ops;
244 247
245 tmp = amdgpu_bo_gpu_offset(abo) - adev->mc.vram_start; 248 tmp = amdgpu_bo_gpu_offset(abo) - adev->gmc.vram_start;
246 info->fix.smem_start = adev->mc.aper_base + tmp; 249 info->fix.smem_start = adev->gmc.aper_base + tmp;
247 info->fix.smem_len = amdgpu_bo_size(abo); 250 info->fix.smem_len = amdgpu_bo_size(abo);
248 info->screen_base = amdgpu_bo_kptr(abo); 251 info->screen_base = amdgpu_bo_kptr(abo);
249 info->screen_size = amdgpu_bo_size(abo); 252 info->screen_size = amdgpu_bo_size(abo);
@@ -252,7 +255,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
252 255
253 /* setup aperture base/size for vesafb takeover */ 256 /* setup aperture base/size for vesafb takeover */
254 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base; 257 info->apertures->ranges[0].base = adev->ddev->mode_config.fb_base;
255 info->apertures->ranges[0].size = adev->mc.aper_size; 258 info->apertures->ranges[0].size = adev->gmc.aper_size;
256 259
257 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */ 260 /* Use default scratch pixmap (info->pixmap.flags = FB_PIXMAP_SYSTEM) */
258 261
@@ -262,7 +265,7 @@ static int amdgpufb_create(struct drm_fb_helper *helper,
262 } 265 }
263 266
264 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start); 267 DRM_INFO("fb mappable at 0x%lX\n", info->fix.smem_start);
265 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->mc.aper_base); 268 DRM_INFO("vram apper at 0x%lX\n", (unsigned long)adev->gmc.aper_base);
266 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo)); 269 DRM_INFO("size %lu\n", (unsigned long)amdgpu_bo_size(abo));
267 DRM_INFO("fb depth is %d\n", fb->format->depth); 270 DRM_INFO("fb depth is %d\n", fb->format->depth);
268 DRM_INFO(" pitch is %d\n", fb->pitches[0]); 271 DRM_INFO(" pitch is %d\n", fb->pitches[0]);
@@ -319,7 +322,7 @@ int amdgpu_fbdev_init(struct amdgpu_device *adev)
319 return 0; 322 return 0;
320 323
321 /* select 8 bpp console on low vram cards */ 324 /* select 8 bpp console on low vram cards */
322 if (adev->mc.real_vram_size <= (32*1024*1024)) 325 if (adev->gmc.real_vram_size <= (32*1024*1024))
323 bpp_sel = 8; 326 bpp_sel = 8;
324 327
325 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL); 328 rfbdev = kzalloc(sizeof(struct amdgpu_fbdev), GFP_KERNEL);