1 files changed, 443 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 3738a96c2619..bd85e35998e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -23,6 +23,446 @@
 #ifndef __AMDGPU_DPM_H__
 #define __AMDGPU_DPM_H__
+enum amdgpu_int_thermal_type {
+        THERMAL_TYPE_NONE,
+        THERMAL_TYPE_EXTERNAL,
+        THERMAL_TYPE_EXTERNAL_GPIO,
+        THERMAL_TYPE_RV6XX,
+        THERMAL_TYPE_RV770,
+        THERMAL_TYPE_ADT7473_WITH_INTERNAL,
+        THERMAL_TYPE_EVERGREEN,
+        THERMAL_TYPE_SUMO,
+        THERMAL_TYPE_NI,
+        THERMAL_TYPE_SI,
+        THERMAL_TYPE_EMC2103_WITH_INTERNAL,
+        THERMAL_TYPE_CI,
+        THERMAL_TYPE_KV,
+};
+enum amdgpu_dpm_auto_throttle_src {
+        AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
+        AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
+};
+enum amdgpu_dpm_event_src {
+        AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
+        AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
+        AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
+        AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
+        AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
+};
+struct amdgpu_ps {
+        u32 caps; /* vbios flags */
+        u32 class; /* vbios flags */
+        u32 class2; /* vbios flags */
+        /* UVD clocks */
+        u32 vclk;
+        u32 dclk;
+        /* VCE clocks */
+        u32 evclk;
+        u32 ecclk;
+        bool vce_active;
+        enum amd_vce_level vce_level;
+        /* asic priv */
+        void *ps_priv;
+};
+struct amdgpu_dpm_thermal {
+        /* thermal interrupt work */
+        struct work_struct work;
+        /* low temperature threshold */
+        int                min_temp;
+        /* high temperature threshold */
+        int                max_temp;
+        /* was last interrupt low to high or high to low */
+        bool               high_to_low;
+        /* interrupt source */
+        struct amdgpu_irq_src   irq;
+};
+enum amdgpu_clk_action
+{
+        AMDGPU_SCLK_UP = 1,
+        AMDGPU_SCLK_DOWN
+};
+struct amdgpu_blacklist_clocks
+{
+        u32 sclk;
+        u32 mclk;
+        enum amdgpu_clk_action action;
+};
+struct amdgpu_clock_and_voltage_limits {
+        u32 sclk;
+        u32 mclk;
+        u16 vddc;
+        u16 vddci;
+};
+struct amdgpu_clock_array {
+        u32 count;
+        u32 *values;
+};
+struct amdgpu_clock_voltage_dependency_entry {
+        u32 clk;
+        u16 v;
+};
+struct amdgpu_clock_voltage_dependency_table {
+        u32 count;
+        struct amdgpu_clock_voltage_dependency_entry *entries;
+};
+union amdgpu_cac_leakage_entry {
+        struct {
+                u16 vddc;
+                u32 leakage;
+        };
+        struct {
+                u16 vddc1;
+                u16 vddc2;
+                u16 vddc3;
+        };
+};
+struct amdgpu_cac_leakage_table {
+        u32 count;
+        union amdgpu_cac_leakage_entry *entries;
+};
+struct amdgpu_phase_shedding_limits_entry {
+        u16 voltage;
+        u32 sclk;
+        u32 mclk;
+};
+struct amdgpu_phase_shedding_limits_table {
+        u32 count;
+        struct amdgpu_phase_shedding_limits_entry *entries;
+};
+struct amdgpu_uvd_clock_voltage_dependency_entry {
+        u32 vclk;
+        u32 dclk;
+        u16 v;
+};
+struct amdgpu_uvd_clock_voltage_dependency_table {
+        u8 count;
+        struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
+};
+struct amdgpu_vce_clock_voltage_dependency_entry {
+        u32 ecclk;
+        u32 evclk;
+        u16 v;
+};
+struct amdgpu_vce_clock_voltage_dependency_table {
+        u8 count;
+        struct amdgpu_vce_clock_voltage_dependency_entry *entries;
+};
+struct amdgpu_ppm_table {
+        u8 ppm_design;
+        u16 cpu_core_number;
+        u32 platform_tdp;
+        u32 small_ac_platform_tdp;
+        u32 platform_tdc;
+        u32 small_ac_platform_tdc;
+        u32 apu_tdp;
+        u32 dgpu_tdp;
+        u32 dgpu_ulv_power;
+        u32 tj_max;
+};
+struct amdgpu_cac_tdp_table {
+        u16 tdp;
+        u16 configurable_tdp;
+        u16 tdc;
+        u16 battery_power_limit;
+        u16 small_power_limit;
+        u16 low_cac_leakage;
+        u16 high_cac_leakage;
+        u16 maximum_power_delivery_limit;
+};
+struct amdgpu_dpm_dynamic_state {
+        struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
+        struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
+        struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
+        struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
+        struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
+        struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
+        struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
+        struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
+        struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
+        struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
+        struct amdgpu_clock_array valid_sclk_values;
+        struct amdgpu_clock_array valid_mclk_values;
+        struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
+        struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
+        u32 mclk_sclk_ratio;
+        u32 sclk_mclk_delta;
+        u16 vddc_vddci_delta;
+        u16 min_vddc_for_pcie_gen2;
+        struct amdgpu_cac_leakage_table cac_leakage_table;
+        struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
+        struct amdgpu_ppm_table *ppm_table;
+        struct amdgpu_cac_tdp_table *cac_tdp_table;
+};
+struct amdgpu_dpm_fan {
+        u16 t_min;
+        u16 t_med;
+        u16 t_high;
+        u16 pwm_min;
+        u16 pwm_med;
+        u16 pwm_high;
+        u8 t_hyst;
+        u32 cycle_delay;
+        u16 t_max;
+        u8 control_mode;
+        u16 default_max_fan_pwm;
+        u16 default_fan_output_sensitivity;
+        u16 fan_output_sensitivity;
+        bool ucode_fan_control;
+};
+enum amdgpu_pcie_gen {
+        AMDGPU_PCIE_GEN1 = 0,
+        AMDGPU_PCIE_GEN2 = 1,
+        AMDGPU_PCIE_GEN3 = 2,
+        AMDGPU_PCIE_GEN_INVALID = 0xffff
+};
+enum amdgpu_dpm_forced_level {
+        AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
+        AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
+        AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
+        AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
+};
+struct amdgpu_dpm_funcs {
+        int (*get_temperature)(struct amdgpu_device *adev);
+        int (*pre_set_power_state)(struct amdgpu_device *adev);
+        int (*set_power_state)(struct amdgpu_device *adev);
+        void (*post_set_power_state)(struct amdgpu_device *adev);
+        void (*display_configuration_changed)(struct amdgpu_device *adev);
+        u32 (*get_sclk)(struct amdgpu_device *adev, bool low);
+        u32 (*get_mclk)(struct amdgpu_device *adev, bool low);
+        void (*print_power_state)(struct amdgpu_device *adev, struct amdgpu_ps *ps);
+        void (*debugfs_print_current_performance_level)(struct amdgpu_device *adev, struct seq_file *m);
+        int (*force_performance_level)(struct amdgpu_device *adev, enum amdgpu_dpm_forced_level level);
+        bool (*vblank_too_short)(struct amdgpu_device *adev);
+        void (*powergate_uvd)(struct amdgpu_device *adev, bool gate);
+        void (*powergate_vce)(struct amdgpu_device *adev, bool gate);
+        void (*enable_bapm)(struct amdgpu_device *adev, bool enable);
+        void (*set_fan_control_mode)(struct amdgpu_device *adev, u32 mode);
+        u32 (*get_fan_control_mode)(struct amdgpu_device *adev);
+        int (*set_fan_speed_percent)(struct amdgpu_device *adev, u32 speed);
+        int (*get_fan_speed_percent)(struct amdgpu_device *adev, u32 *speed);
+        int (*force_clock_level)(struct amdgpu_device *adev, enum pp_clock_type type, uint32_t mask);
+        int (*print_clock_levels)(struct amdgpu_device *adev, enum pp_clock_type type, char *buf);
+        int (*get_sclk_od)(struct amdgpu_device *adev);
+        int (*set_sclk_od)(struct amdgpu_device *adev, uint32_t value);
+        int (*get_mclk_od)(struct amdgpu_device *adev);
+        int (*set_mclk_od)(struct amdgpu_device *adev, uint32_t value);
+        int (*check_state_equal)(struct amdgpu_device *adev,
+                                struct amdgpu_ps *cps,
+                                struct amdgpu_ps *rps,
+                                bool *equal);
+        struct amd_vce_state* (*get_vce_clock_state)(struct amdgpu_device *adev, unsigned idx);
+};
+#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
+#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
+#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
+#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
+#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
+#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
+#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
+#define amdgpu_dpm_read_sensor(adev, idx, value) \
+        ((adev)->pp_enabled ? \
+                (adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
+                -EINVAL)
+#define amdgpu_dpm_get_temperature(adev) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
+              (adev)->pm.funcs->get_temperature((adev)))
+#define amdgpu_dpm_set_fan_control_mode(adev, m) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
+              (adev)->pm.funcs->set_fan_control_mode((adev), (m)))
+#define amdgpu_dpm_get_fan_control_mode(adev) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
+              (adev)->pm.funcs->get_fan_control_mode((adev)))
+#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
+              (adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
+#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
+              (adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
+#define amdgpu_dpm_get_sclk(adev, l) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
+                (adev)->pm.funcs->get_sclk((adev), (l)))
+#define amdgpu_dpm_get_mclk(adev, l)  \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
+              (adev)->pm.funcs->get_mclk((adev), (l)))
+#define amdgpu_dpm_force_performance_level(adev, l) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
+              (adev)->pm.funcs->force_performance_level((adev), (l)))
+#define amdgpu_dpm_powergate_uvd(adev, g) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
+              (adev)->pm.funcs->powergate_uvd((adev), (g)))
+#define amdgpu_dpm_powergate_vce(adev, g) \
+        ((adev)->pp_enabled ?                                           \
+              (adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
+              (adev)->pm.funcs->powergate_vce((adev), (g)))
+#define amdgpu_dpm_get_current_power_state(adev) \
+        (adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
+#define amdgpu_dpm_get_performance_level(adev) \
+        (adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
+#define amdgpu_dpm_get_pp_num_states(adev, data) \
+        (adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
+#define amdgpu_dpm_get_pp_table(adev, table) \
+        (adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
+#define amdgpu_dpm_set_pp_table(adev, buf, size) \
+        (adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
+#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
+        (adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
+#define amdgpu_dpm_force_clock_level(adev, type, level) \
+                (adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
+#define amdgpu_dpm_get_sclk_od(adev) \
+        (adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
+#define amdgpu_dpm_set_sclk_od(adev, value) \
+        (adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
+#define amdgpu_dpm_get_mclk_od(adev) \
+        ((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
+#define amdgpu_dpm_set_mclk_od(adev, value) \
+        ((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
+#define amdgpu_dpm_dispatch_task(adev, event_id, input, output)         \
+        (adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
+#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal))
+#define amdgpu_dpm_get_vce_clock_state(adev, i)                         \
+        ((adev)->pp_enabled ?                                           \
+         (adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
+         (adev)->pm.funcs->get_vce_clock_state((adev), (i)))
+struct amdgpu_dpm {
+        struct amdgpu_ps        *ps;
+        /* number of valid power states */
+        int                     num_ps;
+        /* current power state that is active */
+        struct amdgpu_ps        *current_ps;
+        /* requested power state */
+        struct amdgpu_ps        *requested_ps;
+        /* boot up power state */
+        struct amdgpu_ps        *boot_ps;
+        /* default uvd power state */
+        struct amdgpu_ps        *uvd_ps;
+        /* vce requirements */
+        u32                  num_of_vce_states;
+        struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
+        enum amd_vce_level vce_level;
+        enum amd_pm_state_type state;
+        enum amd_pm_state_type user_state;
+        enum amd_pm_state_type last_state;
+        enum amd_pm_state_type last_user_state;
+        u32                     platform_caps;
+        u32                     voltage_response_time;
+        u32                     backbias_response_time;
+        void                    *priv;
+        u32                     new_active_crtcs;
+        int                     new_active_crtc_count;
+        u32                     current_active_crtcs;
+        int                     current_active_crtc_count;
+        struct amdgpu_dpm_dynamic_state dyn_state;
+        struct amdgpu_dpm_fan fan;
+        u32 tdp_limit;
+        u32 near_tdp_limit;
+        u32 near_tdp_limit_adjusted;
+        u32 sq_ramping_threshold;
+        u32 cac_leakage;
+        u16 tdp_od_limit;
+        u32 tdp_adjustment;
+        u16 load_line_slope;
+        bool power_control;
+        bool ac_power;
+        /* special states active */
+        bool                    thermal_active;
+        bool                    uvd_active;
+        bool                    vce_active;
+        /* thermal handling */
+        struct amdgpu_dpm_thermal thermal;
+        /* forced levels */
+        enum amdgpu_dpm_forced_level forced_level;
+};
+struct amdgpu_pm {
+        struct mutex            mutex;
+        u32                     current_sclk;
+        u32                     current_mclk;
+        u32                     default_sclk;
+        u32                     default_mclk;
+        struct amdgpu_i2c_chan *i2c_bus;
+        /* internal thermal controller on rv6xx+ */
+        enum amdgpu_int_thermal_type int_thermal_type;
+        struct device           *int_hwmon_dev;
+        /* fan control parameters */
+        bool                    no_fan;
+        u8                      fan_pulses_per_revolution;
+        u8                      fan_min_rpm;
+        u8                      fan_max_rpm;
+        /* dpm */
+        bool                    dpm_enabled;
+        bool                    sysfs_initialized;
+        struct amdgpu_dpm       dpm;
+        const struct firmware   *fw;    /* SMC firmware */
+        uint32_t                fw_version;
+        const struct amdgpu_dpm_funcs *funcs;
+        uint32_t                pcie_gen_mask;
+        uint32_t                pcie_mlw_mask;
+        struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
+};
 #define R600_SSTU_DFLT                               0
 #define R600_SST_DFLT                                0x00C8
@@ -82,4 +522,7 @@ u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
                                 u16 default_lanes);
 u8 amdgpu_encode_pci_lane_width(u32 lanes);
+struct amd_vce_state*
+amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx);
 #endif

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h index 3738a96c2619..bd85e35998e7 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -23,6 +23,446 @@
23	#ifndef __AMDGPU_DPM_H__	23	#ifndef __AMDGPU_DPM_H__
24	#define __AMDGPU_DPM_H__	24	#define __AMDGPU_DPM_H__
25		25
		26	enum amdgpu_int_thermal_type {
		27	THERMAL_TYPE_NONE,
		28	THERMAL_TYPE_EXTERNAL,
		29	THERMAL_TYPE_EXTERNAL_GPIO,
		30	THERMAL_TYPE_RV6XX,
		31	THERMAL_TYPE_RV770,
		32	THERMAL_TYPE_ADT7473_WITH_INTERNAL,
		33	THERMAL_TYPE_EVERGREEN,
		34	THERMAL_TYPE_SUMO,
		35	THERMAL_TYPE_NI,
		36	THERMAL_TYPE_SI,
		37	THERMAL_TYPE_EMC2103_WITH_INTERNAL,
		38	THERMAL_TYPE_CI,
		39	THERMAL_TYPE_KV,
		40	};
		41
		42	enum amdgpu_dpm_auto_throttle_src {
		43	AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL,
		44	AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL
		45	};
		46
		47	enum amdgpu_dpm_event_src {
		48	AMDGPU_DPM_EVENT_SRC_ANALOG = 0,
		49	AMDGPU_DPM_EVENT_SRC_EXTERNAL = 1,
		50	AMDGPU_DPM_EVENT_SRC_DIGITAL = 2,
		51	AMDGPU_DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3,
		52	AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL = 4
		53	};
		54
		55	struct amdgpu_ps {
		56	u32 caps; /* vbios flags */
		57	u32 class; /* vbios flags */
		58	u32 class2; /* vbios flags */
		59	/* UVD clocks */
		60	u32 vclk;
		61	u32 dclk;
		62	/* VCE clocks */
		63	u32 evclk;
		64	u32 ecclk;
		65	bool vce_active;
		66	enum amd_vce_level vce_level;
		67	/* asic priv */
		68	void *ps_priv;
		69	};
		70
		71	struct amdgpu_dpm_thermal {
		72	/* thermal interrupt work */
		73	struct work_struct work;
		74	/* low temperature threshold */
		75	int min_temp;
		76	/* high temperature threshold */
		77	int max_temp;
		78	/* was last interrupt low to high or high to low */
		79	bool high_to_low;
		80	/* interrupt source */
		81	struct amdgpu_irq_src irq;
		82	};
		83
		84	enum amdgpu_clk_action
		85	{
		86	AMDGPU_SCLK_UP = 1,
		87	AMDGPU_SCLK_DOWN
		88	};
		89
		90	struct amdgpu_blacklist_clocks
		91	{
		92	u32 sclk;
		93	u32 mclk;
		94	enum amdgpu_clk_action action;
		95	};
		96
		97	struct amdgpu_clock_and_voltage_limits {
		98	u32 sclk;
		99	u32 mclk;
		100	u16 vddc;
		101	u16 vddci;
		102	};
		103
		104	struct amdgpu_clock_array {
		105	u32 count;
		106	u32 *values;
		107	};
		108
		109	struct amdgpu_clock_voltage_dependency_entry {
		110	u32 clk;
		111	u16 v;
		112	};
		113
		114	struct amdgpu_clock_voltage_dependency_table {
		115	u32 count;
		116	struct amdgpu_clock_voltage_dependency_entry *entries;
		117	};
		118
		119	union amdgpu_cac_leakage_entry {
		120	struct {
		121	u16 vddc;
		122	u32 leakage;
		123	};
		124	struct {
		125	u16 vddc1;
		126	u16 vddc2;
		127	u16 vddc3;
		128	};
		129	};
		130
		131	struct amdgpu_cac_leakage_table {
		132	u32 count;
		133	union amdgpu_cac_leakage_entry *entries;
		134	};
		135
		136	struct amdgpu_phase_shedding_limits_entry {
		137	u16 voltage;
		138	u32 sclk;
		139	u32 mclk;
		140	};
		141
		142	struct amdgpu_phase_shedding_limits_table {
		143	u32 count;
		144	struct amdgpu_phase_shedding_limits_entry *entries;
		145	};
		146
		147	struct amdgpu_uvd_clock_voltage_dependency_entry {
		148	u32 vclk;
		149	u32 dclk;
		150	u16 v;
		151	};
		152
		153	struct amdgpu_uvd_clock_voltage_dependency_table {
		154	u8 count;
		155	struct amdgpu_uvd_clock_voltage_dependency_entry *entries;
		156	};
		157
		158	struct amdgpu_vce_clock_voltage_dependency_entry {
		159	u32 ecclk;
		160	u32 evclk;
		161	u16 v;
		162	};
		163
		164	struct amdgpu_vce_clock_voltage_dependency_table {
		165	u8 count;
		166	struct amdgpu_vce_clock_voltage_dependency_entry *entries;
		167	};
		168
		169	struct amdgpu_ppm_table {
		170	u8 ppm_design;
		171	u16 cpu_core_number;
		172	u32 platform_tdp;
		173	u32 small_ac_platform_tdp;
		174	u32 platform_tdc;
		175	u32 small_ac_platform_tdc;
		176	u32 apu_tdp;
		177	u32 dgpu_tdp;
		178	u32 dgpu_ulv_power;
		179	u32 tj_max;
		180	};
		181
		182	struct amdgpu_cac_tdp_table {
		183	u16 tdp;
		184	u16 configurable_tdp;
		185	u16 tdc;
		186	u16 battery_power_limit;
		187	u16 small_power_limit;
		188	u16 low_cac_leakage;
		189	u16 high_cac_leakage;
		190	u16 maximum_power_delivery_limit;
		191	};
		192
		193	struct amdgpu_dpm_dynamic_state {
		194	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_sclk;
		195	struct amdgpu_clock_voltage_dependency_table vddci_dependency_on_mclk;
		196	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_mclk;
		197	struct amdgpu_clock_voltage_dependency_table mvdd_dependency_on_mclk;
		198	struct amdgpu_clock_voltage_dependency_table vddc_dependency_on_dispclk;
		199	struct amdgpu_uvd_clock_voltage_dependency_table uvd_clock_voltage_dependency_table;
		200	struct amdgpu_vce_clock_voltage_dependency_table vce_clock_voltage_dependency_table;
		201	struct amdgpu_clock_voltage_dependency_table samu_clock_voltage_dependency_table;
		202	struct amdgpu_clock_voltage_dependency_table acp_clock_voltage_dependency_table;
		203	struct amdgpu_clock_voltage_dependency_table vddgfx_dependency_on_sclk;
		204	struct amdgpu_clock_array valid_sclk_values;
		205	struct amdgpu_clock_array valid_mclk_values;
		206	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_dc;
		207	struct amdgpu_clock_and_voltage_limits max_clock_voltage_on_ac;
		208	u32 mclk_sclk_ratio;
		209	u32 sclk_mclk_delta;
		210	u16 vddc_vddci_delta;
		211	u16 min_vddc_for_pcie_gen2;
		212	struct amdgpu_cac_leakage_table cac_leakage_table;
		213	struct amdgpu_phase_shedding_limits_table phase_shedding_limits_table;
		214	struct amdgpu_ppm_table *ppm_table;
		215	struct amdgpu_cac_tdp_table *cac_tdp_table;
		216	};
		217
		218	struct amdgpu_dpm_fan {
		219	u16 t_min;
		220	u16 t_med;
		221	u16 t_high;
		222	u16 pwm_min;
		223	u16 pwm_med;
		224	u16 pwm_high;
		225	u8 t_hyst;
		226	u32 cycle_delay;
		227	u16 t_max;
		228	u8 control_mode;
		229	u16 default_max_fan_pwm;
		230	u16 default_fan_output_sensitivity;
		231	u16 fan_output_sensitivity;
		232	bool ucode_fan_control;
		233	};
		234
		235	enum amdgpu_pcie_gen {
		236	AMDGPU_PCIE_GEN1 = 0,
		237	AMDGPU_PCIE_GEN2 = 1,
		238	AMDGPU_PCIE_GEN3 = 2,
		239	AMDGPU_PCIE_GEN_INVALID = 0xffff
		240	};
		241
		242	enum amdgpu_dpm_forced_level {
		243	AMDGPU_DPM_FORCED_LEVEL_AUTO = 0,
		244	AMDGPU_DPM_FORCED_LEVEL_LOW = 1,
		245	AMDGPU_DPM_FORCED_LEVEL_HIGH = 2,
		246	AMDGPU_DPM_FORCED_LEVEL_MANUAL = 3,
		247	};
		248
		249	struct amdgpu_dpm_funcs {
		250	int (get_temperature)(struct amdgpu_device adev);
		251	int (pre_set_power_state)(struct amdgpu_device adev);
		252	int (set_power_state)(struct amdgpu_device adev);
		253	void (post_set_power_state)(struct amdgpu_device adev);
		254	void (display_configuration_changed)(struct amdgpu_device adev);
		255	u32 (get_sclk)(struct amdgpu_device adev, bool low);
		256	u32 (get_mclk)(struct amdgpu_device adev, bool low);
		257	void (print_power_state)(struct amdgpu_device adev, struct amdgpu_ps *ps);
		258	void (debugfs_print_current_performance_level)(struct amdgpu_device adev, struct seq_file *m);
		259	int (force_performance_level)(struct amdgpu_device adev, enum amdgpu_dpm_forced_level level);
		260	bool (vblank_too_short)(struct amdgpu_device adev);
		261	void (powergate_uvd)(struct amdgpu_device adev, bool gate);
		262	void (powergate_vce)(struct amdgpu_device adev, bool gate);
		263	void (enable_bapm)(struct amdgpu_device adev, bool enable);
		264	void (set_fan_control_mode)(struct amdgpu_device adev, u32 mode);
		265	u32 (get_fan_control_mode)(struct amdgpu_device adev);
		266	int (set_fan_speed_percent)(struct amdgpu_device adev, u32 speed);
		267	int (get_fan_speed_percent)(struct amdgpu_device adev, u32 *speed);
		268	int (force_clock_level)(struct amdgpu_device adev, enum pp_clock_type type, uint32_t mask);
		269	int (print_clock_levels)(struct amdgpu_device adev, enum pp_clock_type type, char *buf);
		270	int (get_sclk_od)(struct amdgpu_device adev);
		271	int (set_sclk_od)(struct amdgpu_device adev, uint32_t value);
		272	int (get_mclk_od)(struct amdgpu_device adev);
		273	int (set_mclk_od)(struct amdgpu_device adev, uint32_t value);
		274	int (check_state_equal)(struct amdgpu_device adev,
		275	struct amdgpu_ps *cps,
		276	struct amdgpu_ps *rps,
		277	bool *equal);
		278
		279	struct amd_vce_state* (get_vce_clock_state)(struct amdgpu_device adev, unsigned idx);
		280	};
		281
		282	#define amdgpu_dpm_pre_set_power_state(adev) (adev)->pm.funcs->pre_set_power_state((adev))
		283	#define amdgpu_dpm_set_power_state(adev) (adev)->pm.funcs->set_power_state((adev))
		284	#define amdgpu_dpm_post_set_power_state(adev) (adev)->pm.funcs->post_set_power_state((adev))
		285	#define amdgpu_dpm_display_configuration_changed(adev) (adev)->pm.funcs->display_configuration_changed((adev))
		286	#define amdgpu_dpm_print_power_state(adev, ps) (adev)->pm.funcs->print_power_state((adev), (ps))
		287	#define amdgpu_dpm_vblank_too_short(adev) (adev)->pm.funcs->vblank_too_short((adev))
		288	#define amdgpu_dpm_enable_bapm(adev, e) (adev)->pm.funcs->enable_bapm((adev), (e))
		289
		290	#define amdgpu_dpm_read_sensor(adev, idx, value) \
		291	((adev)->pp_enabled ? \
		292	(adev)->powerplay.pp_funcs->read_sensor(adev->powerplay.pp_handle, (idx), (value)) : \
		293	-EINVAL)
		294
		295	#define amdgpu_dpm_get_temperature(adev) \
		296	((adev)->pp_enabled ? \
		297	(adev)->powerplay.pp_funcs->get_temperature((adev)->powerplay.pp_handle) : \
		298	(adev)->pm.funcs->get_temperature((adev)))
		299
		300	#define amdgpu_dpm_set_fan_control_mode(adev, m) \
		301	((adev)->pp_enabled ? \
		302	(adev)->powerplay.pp_funcs->set_fan_control_mode((adev)->powerplay.pp_handle, (m)) : \
		303	(adev)->pm.funcs->set_fan_control_mode((adev), (m)))
		304
		305	#define amdgpu_dpm_get_fan_control_mode(adev) \
		306	((adev)->pp_enabled ? \
		307	(adev)->powerplay.pp_funcs->get_fan_control_mode((adev)->powerplay.pp_handle) : \
		308	(adev)->pm.funcs->get_fan_control_mode((adev)))
		309
		310	#define amdgpu_dpm_set_fan_speed_percent(adev, s) \
		311	((adev)->pp_enabled ? \
		312	(adev)->powerplay.pp_funcs->set_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
		313	(adev)->pm.funcs->set_fan_speed_percent((adev), (s)))
		314
		315	#define amdgpu_dpm_get_fan_speed_percent(adev, s) \
		316	((adev)->pp_enabled ? \
		317	(adev)->powerplay.pp_funcs->get_fan_speed_percent((adev)->powerplay.pp_handle, (s)) : \
		318	(adev)->pm.funcs->get_fan_speed_percent((adev), (s)))
		319
		320	#define amdgpu_dpm_get_sclk(adev, l) \
		321	((adev)->pp_enabled ? \
		322	(adev)->powerplay.pp_funcs->get_sclk((adev)->powerplay.pp_handle, (l)) : \
		323	(adev)->pm.funcs->get_sclk((adev), (l)))
		324
		325	#define amdgpu_dpm_get_mclk(adev, l) \
		326	((adev)->pp_enabled ? \
		327	(adev)->powerplay.pp_funcs->get_mclk((adev)->powerplay.pp_handle, (l)) : \
		328	(adev)->pm.funcs->get_mclk((adev), (l)))
		329
		330
		331	#define amdgpu_dpm_force_performance_level(adev, l) \
		332	((adev)->pp_enabled ? \
		333	(adev)->powerplay.pp_funcs->force_performance_level((adev)->powerplay.pp_handle, (l)) : \
		334	(adev)->pm.funcs->force_performance_level((adev), (l)))
		335
		336	#define amdgpu_dpm_powergate_uvd(adev, g) \
		337	((adev)->pp_enabled ? \
		338	(adev)->powerplay.pp_funcs->powergate_uvd((adev)->powerplay.pp_handle, (g)) : \
		339	(adev)->pm.funcs->powergate_uvd((adev), (g)))
		340
		341	#define amdgpu_dpm_powergate_vce(adev, g) \
		342	((adev)->pp_enabled ? \
		343	(adev)->powerplay.pp_funcs->powergate_vce((adev)->powerplay.pp_handle, (g)) : \
		344	(adev)->pm.funcs->powergate_vce((adev), (g)))
		345
		346	#define amdgpu_dpm_get_current_power_state(adev) \
		347	(adev)->powerplay.pp_funcs->get_current_power_state((adev)->powerplay.pp_handle)
		348
		349	#define amdgpu_dpm_get_performance_level(adev) \
		350	(adev)->powerplay.pp_funcs->get_performance_level((adev)->powerplay.pp_handle)
		351
		352	#define amdgpu_dpm_get_pp_num_states(adev, data) \
		353	(adev)->powerplay.pp_funcs->get_pp_num_states((adev)->powerplay.pp_handle, data)
		354
		355	#define amdgpu_dpm_get_pp_table(adev, table) \
		356	(adev)->powerplay.pp_funcs->get_pp_table((adev)->powerplay.pp_handle, table)
		357
		358	#define amdgpu_dpm_set_pp_table(adev, buf, size) \
		359	(adev)->powerplay.pp_funcs->set_pp_table((adev)->powerplay.pp_handle, buf, size)
		360
		361	#define amdgpu_dpm_print_clock_levels(adev, type, buf) \
		362	(adev)->powerplay.pp_funcs->print_clock_levels((adev)->powerplay.pp_handle, type, buf)
		363
		364	#define amdgpu_dpm_force_clock_level(adev, type, level) \
		365	(adev)->powerplay.pp_funcs->force_clock_level((adev)->powerplay.pp_handle, type, level)
		366
		367	#define amdgpu_dpm_get_sclk_od(adev) \
		368	(adev)->powerplay.pp_funcs->get_sclk_od((adev)->powerplay.pp_handle)
		369
		370	#define amdgpu_dpm_set_sclk_od(adev, value) \
		371	(adev)->powerplay.pp_funcs->set_sclk_od((adev)->powerplay.pp_handle, value)
		372
		373	#define amdgpu_dpm_get_mclk_od(adev) \
		374	((adev)->powerplay.pp_funcs->get_mclk_od((adev)->powerplay.pp_handle))
		375
		376	#define amdgpu_dpm_set_mclk_od(adev, value) \
		377	((adev)->powerplay.pp_funcs->set_mclk_od((adev)->powerplay.pp_handle, value))
		378
		379	#define amdgpu_dpm_dispatch_task(adev, event_id, input, output) \
		380	(adev)->powerplay.pp_funcs->dispatch_tasks((adev)->powerplay.pp_handle, (event_id), (input), (output))
		381
		382	#define amgdpu_dpm_check_state_equal(adev, cps, rps, equal) (adev)->pm.funcs->check_state_equal((adev), (cps),(rps),(equal))
		383
		384	#define amdgpu_dpm_get_vce_clock_state(adev, i) \
		385	((adev)->pp_enabled ? \
		386	(adev)->powerplay.pp_funcs->get_vce_clock_state((adev)->powerplay.pp_handle, (i)) : \
		387	(adev)->pm.funcs->get_vce_clock_state((adev), (i)))
		388
		389	struct amdgpu_dpm {
		390	struct amdgpu_ps *ps;
		391	/* number of valid power states */
		392	int num_ps;
		393	/* current power state that is active */
		394	struct amdgpu_ps *current_ps;
		395	/* requested power state */
		396	struct amdgpu_ps *requested_ps;
		397	/* boot up power state */
		398	struct amdgpu_ps *boot_ps;
		399	/* default uvd power state */
		400	struct amdgpu_ps *uvd_ps;
		401	/* vce requirements */
		402	u32 num_of_vce_states;
		403	struct amd_vce_state vce_states[AMD_MAX_VCE_LEVELS];
		404	enum amd_vce_level vce_level;
		405	enum amd_pm_state_type state;
		406	enum amd_pm_state_type user_state;
		407	enum amd_pm_state_type last_state;
		408	enum amd_pm_state_type last_user_state;
		409	u32 platform_caps;
		410	u32 voltage_response_time;
		411	u32 backbias_response_time;
		412	void *priv;
		413	u32 new_active_crtcs;
		414	int new_active_crtc_count;
		415	u32 current_active_crtcs;
		416	int current_active_crtc_count;
		417	struct amdgpu_dpm_dynamic_state dyn_state;
		418	struct amdgpu_dpm_fan fan;
		419	u32 tdp_limit;
		420	u32 near_tdp_limit;
		421	u32 near_tdp_limit_adjusted;
		422	u32 sq_ramping_threshold;
		423	u32 cac_leakage;
		424	u16 tdp_od_limit;
		425	u32 tdp_adjustment;
		426	u16 load_line_slope;
		427	bool power_control;
		428	bool ac_power;
		429	/* special states active */
		430	bool thermal_active;
		431	bool uvd_active;
		432	bool vce_active;
		433	/* thermal handling */
		434	struct amdgpu_dpm_thermal thermal;
		435	/* forced levels */
		436	enum amdgpu_dpm_forced_level forced_level;
		437	};
		438
		439	struct amdgpu_pm {
		440	struct mutex mutex;
		441	u32 current_sclk;
		442	u32 current_mclk;
		443	u32 default_sclk;
		444	u32 default_mclk;
		445	struct amdgpu_i2c_chan *i2c_bus;
		446	/* internal thermal controller on rv6xx+ */
		447	enum amdgpu_int_thermal_type int_thermal_type;
		448	struct device *int_hwmon_dev;
		449	/* fan control parameters */
		450	bool no_fan;
		451	u8 fan_pulses_per_revolution;
		452	u8 fan_min_rpm;
		453	u8 fan_max_rpm;
		454	/* dpm */
		455	bool dpm_enabled;
		456	bool sysfs_initialized;
		457	struct amdgpu_dpm dpm;
		458	const struct firmware fw; / SMC firmware */
		459	uint32_t fw_version;
		460	const struct amdgpu_dpm_funcs *funcs;
		461	uint32_t pcie_gen_mask;
		462	uint32_t pcie_mlw_mask;
		463	struct amd_pp_display_configuration pm_display_cfg;/* set by DAL */
		464	};
		465
26	#define R600_SSTU_DFLT 0	466	#define R600_SSTU_DFLT 0
27	#define R600_SST_DFLT 0x00C8	467	#define R600_SST_DFLT 0x00C8
28		468
@@ -82,4 +522,7 @@ u16 amdgpu_get_pcie_lane_support(struct amdgpu_device *adev,
82	u16 default_lanes);	522	u16 default_lanes);
83	u8 amdgpu_encode_pci_lane_width(u32 lanes);	523	u8 amdgpu_encode_pci_lane_width(u32 lanes);
84		524
		525	struct amd_vce_state*
		526	amdgpu_get_vce_clock_state(struct amdgpu_device *adev, unsigned idx);
		527
85	#endif	528	#endif