aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_device.c231
1 files changed, 0 insertions, 231 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 79869827985f..a3632c757ca4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -898,237 +898,6 @@ void amdgpu_dummy_page_fini(struct amdgpu_device *adev)
898 adev->dummy_page.page = NULL; 898 adev->dummy_page.page = NULL;
899} 899}
900 900
901
902/* ATOM accessor methods */
903/*
904 * ATOM is an interpreted byte code stored in tables in the vbios. The
905 * driver registers callbacks to access registers and the interpreter
906 * in the driver parses the tables and executes then to program specific
907 * actions (set display modes, asic init, etc.). See amdgpu_atombios.c,
908 * atombios.h, and atom.c
909 */
910
911/**
912 * cail_pll_read - read PLL register
913 *
914 * @info: atom card_info pointer
915 * @reg: PLL register offset
916 *
917 * Provides a PLL register accessor for the atom interpreter (r4xx+).
918 * Returns the value of the PLL register.
919 */
920static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
921{
922 return 0;
923}
924
925/**
926 * cail_pll_write - write PLL register
927 *
928 * @info: atom card_info pointer
929 * @reg: PLL register offset
930 * @val: value to write to the pll register
931 *
932 * Provides a PLL register accessor for the atom interpreter (r4xx+).
933 */
934static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
935{
936
937}
938
939/**
940 * cail_mc_read - read MC (Memory Controller) register
941 *
942 * @info: atom card_info pointer
943 * @reg: MC register offset
944 *
945 * Provides an MC register accessor for the atom interpreter (r4xx+).
946 * Returns the value of the MC register.
947 */
948static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
949{
950 return 0;
951}
952
953/**
954 * cail_mc_write - write MC (Memory Controller) register
955 *
956 * @info: atom card_info pointer
957 * @reg: MC register offset
958 * @val: value to write to the pll register
959 *
960 * Provides a MC register accessor for the atom interpreter (r4xx+).
961 */
962static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
963{
964
965}
966
967/**
968 * cail_reg_write - write MMIO register
969 *
970 * @info: atom card_info pointer
971 * @reg: MMIO register offset
972 * @val: value to write to the pll register
973 *
974 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
975 */
976static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
977{
978 struct amdgpu_device *adev = info->dev->dev_private;
979
980 WREG32(reg, val);
981}
982
983/**
984 * cail_reg_read - read MMIO register
985 *
986 * @info: atom card_info pointer
987 * @reg: MMIO register offset
988 *
989 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
990 * Returns the value of the MMIO register.
991 */
992static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
993{
994 struct amdgpu_device *adev = info->dev->dev_private;
995 uint32_t r;
996
997 r = RREG32(reg);
998 return r;
999}
1000
1001/**
1002 * cail_ioreg_write - write IO register
1003 *
1004 * @info: atom card_info pointer
1005 * @reg: IO register offset
1006 * @val: value to write to the pll register
1007 *
1008 * Provides a IO register accessor for the atom interpreter (r4xx+).
1009 */
1010static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
1011{
1012 struct amdgpu_device *adev = info->dev->dev_private;
1013
1014 WREG32_IO(reg, val);
1015}
1016
1017/**
1018 * cail_ioreg_read - read IO register
1019 *
1020 * @info: atom card_info pointer
1021 * @reg: IO register offset
1022 *
1023 * Provides an IO register accessor for the atom interpreter (r4xx+).
1024 * Returns the value of the IO register.
1025 */
1026static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
1027{
1028 struct amdgpu_device *adev = info->dev->dev_private;
1029 uint32_t r;
1030
1031 r = RREG32_IO(reg);
1032 return r;
1033}
1034
1035static ssize_t amdgpu_atombios_get_vbios_version(struct device *dev,
1036 struct device_attribute *attr,
1037 char *buf)
1038{
1039 struct drm_device *ddev = dev_get_drvdata(dev);
1040 struct amdgpu_device *adev = ddev->dev_private;
1041 struct atom_context *ctx = adev->mode_info.atom_context;
1042
1043 return snprintf(buf, PAGE_SIZE, "%s\n", ctx->vbios_version);
1044}
1045
1046static DEVICE_ATTR(vbios_version, 0444, amdgpu_atombios_get_vbios_version,
1047 NULL);
1048
1049/**
1050 * amdgpu_atombios_fini - free the driver info and callbacks for atombios
1051 *
1052 * @adev: amdgpu_device pointer
1053 *
1054 * Frees the driver info and register access callbacks for the ATOM
1055 * interpreter (r4xx+).
1056 * Called at driver shutdown.
1057 */
1058static void amdgpu_atombios_fini(struct amdgpu_device *adev)
1059{
1060 if (adev->mode_info.atom_context) {
1061 kfree(adev->mode_info.atom_context->scratch);
1062 kfree(adev->mode_info.atom_context->iio);
1063 }
1064 kfree(adev->mode_info.atom_context);
1065 adev->mode_info.atom_context = NULL;
1066 kfree(adev->mode_info.atom_card_info);
1067 adev->mode_info.atom_card_info = NULL;
1068 device_remove_file(adev->dev, &dev_attr_vbios_version);
1069}
1070
1071/**
1072 * amdgpu_atombios_init - init the driver info and callbacks for atombios
1073 *
1074 * @adev: amdgpu_device pointer
1075 *
1076 * Initializes the driver info and register access callbacks for the
1077 * ATOM interpreter (r4xx+).
1078 * Returns 0 on sucess, -ENOMEM on failure.
1079 * Called at driver startup.
1080 */
1081static int amdgpu_atombios_init(struct amdgpu_device *adev)
1082{
1083 struct card_info *atom_card_info =
1084 kzalloc(sizeof(struct card_info), GFP_KERNEL);
1085 int ret;
1086
1087 if (!atom_card_info)
1088 return -ENOMEM;
1089
1090 adev->mode_info.atom_card_info = atom_card_info;
1091 atom_card_info->dev = adev->ddev;
1092 atom_card_info->reg_read = cail_reg_read;
1093 atom_card_info->reg_write = cail_reg_write;
1094 /* needed for iio ops */
1095 if (adev->rio_mem) {
1096 atom_card_info->ioreg_read = cail_ioreg_read;
1097 atom_card_info->ioreg_write = cail_ioreg_write;
1098 } else {
1099 DRM_DEBUG("PCI I/O BAR is not found. Using MMIO to access ATOM BIOS\n");
1100 atom_card_info->ioreg_read = cail_reg_read;
1101 atom_card_info->ioreg_write = cail_reg_write;
1102 }
1103 atom_card_info->mc_read = cail_mc_read;
1104 atom_card_info->mc_write = cail_mc_write;
1105 atom_card_info->pll_read = cail_pll_read;
1106 atom_card_info->pll_write = cail_pll_write;
1107
1108 adev->mode_info.atom_context = amdgpu_atom_parse(atom_card_info, adev->bios);
1109 if (!adev->mode_info.atom_context) {
1110 amdgpu_atombios_fini(adev);
1111 return -ENOMEM;
1112 }
1113
1114 mutex_init(&adev->mode_info.atom_context->mutex);
1115 if (adev->is_atom_fw) {
1116 amdgpu_atomfirmware_scratch_regs_init(adev);
1117 amdgpu_atomfirmware_allocate_fb_scratch(adev);
1118 } else {
1119 amdgpu_atombios_scratch_regs_init(adev);
1120 amdgpu_atombios_allocate_fb_scratch(adev);
1121 }
1122
1123 ret = device_create_file(adev->dev, &dev_attr_vbios_version);
1124 if (ret) {
1125 DRM_ERROR("Failed to create device file for VBIOS version\n");
1126 return ret;
1127 }
1128
1129 return 0;
1130}
1131
1132/* if we get transitioned to only one device, take VGA back */ 901/* if we get transitioned to only one device, take VGA back */
1133/** 902/**
1134 * amdgpu_vga_set_decode - enable/disable vga decode 903 * amdgpu_vga_set_decode - enable/disable vga decode