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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c59
1 files changed, 34 insertions, 25 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index a7afe553e0a1..f2b72c7c6857 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -911,10 +911,6 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
911 struct cgs_display_info *info) 911 struct cgs_display_info *info)
912{ 912{
913 CGS_FUNC_ADEV; 913 CGS_FUNC_ADEV;
914 struct amdgpu_crtc *amdgpu_crtc;
915 struct drm_device *ddev = adev->ddev;
916 struct drm_crtc *crtc;
917 uint32_t line_time_us, vblank_lines;
918 struct cgs_mode_info *mode_info; 914 struct cgs_mode_info *mode_info;
919 915
920 if (info == NULL) 916 if (info == NULL)
@@ -928,30 +924,43 @@ static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
928 mode_info->ref_clock = adev->clock.spll.reference_freq; 924 mode_info->ref_clock = adev->clock.spll.reference_freq;
929 } 925 }
930 926
931 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) { 927 if (!amdgpu_device_has_dc_support(adev)) {
932 list_for_each_entry(crtc, 928 struct amdgpu_crtc *amdgpu_crtc;
933 &ddev->mode_config.crtc_list, head) { 929 struct drm_device *ddev = adev->ddev;
934 amdgpu_crtc = to_amdgpu_crtc(crtc); 930 struct drm_crtc *crtc;
935 if (crtc->enabled) { 931 uint32_t line_time_us, vblank_lines;
936 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id); 932
937 info->display_count++; 933 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
938 } 934 list_for_each_entry(crtc,
939 if (mode_info != NULL && 935 &ddev->mode_config.crtc_list, head) {
940 crtc->enabled && amdgpu_crtc->enabled && 936 amdgpu_crtc = to_amdgpu_crtc(crtc);
941 amdgpu_crtc->hw_mode.clock) { 937 if (crtc->enabled) {
942 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) / 938 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
943 amdgpu_crtc->hw_mode.clock; 939 info->display_count++;
944 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end - 940 }
945 amdgpu_crtc->hw_mode.crtc_vdisplay + 941 if (mode_info != NULL &&
946 (amdgpu_crtc->v_border * 2); 942 crtc->enabled && amdgpu_crtc->enabled &&
947 mode_info->vblank_time_us = vblank_lines * line_time_us; 943 amdgpu_crtc->hw_mode.clock) {
948 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode); 944 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
949 mode_info->ref_clock = adev->clock.spll.reference_freq; 945 amdgpu_crtc->hw_mode.clock;
950 mode_info = NULL; 946 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
947 amdgpu_crtc->hw_mode.crtc_vdisplay +
948 (amdgpu_crtc->v_border * 2);
949 mode_info->vblank_time_us = vblank_lines * line_time_us;
950 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
951 mode_info->ref_clock = adev->clock.spll.reference_freq;
952 mode_info = NULL;
953 }
951 } 954 }
952 } 955 }
956 } else {
957 info->display_count = adev->pm.pm_display_cfg.num_display;
958 if (mode_info != NULL) {
959 mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
960 mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
961 mode_info->ref_clock = adev->clock.spll.reference_freq;
962 }
953 } 963 }
954
955 return 0; 964 return 0;
956} 965}
957 966