aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c23
1 files changed, 23 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 383204e911a4..a7afe553e0a1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -42,6 +42,28 @@ struct amdgpu_cgs_device {
42 struct amdgpu_device *adev = \ 42 struct amdgpu_device *adev = \
43 ((struct amdgpu_cgs_device *)cgs_device)->adev 43 ((struct amdgpu_cgs_device *)cgs_device)->adev
44 44
45static void *amdgpu_cgs_register_pp_handle(struct cgs_device *cgs_device,
46 int (*call_back_func)(struct amd_pp_init *, void **))
47{
48 CGS_FUNC_ADEV;
49 struct amd_pp_init pp_init;
50 struct amd_powerplay *amd_pp;
51
52 if (call_back_func == NULL)
53 return NULL;
54
55 amd_pp = &(adev->powerplay);
56 pp_init.chip_family = adev->family;
57 pp_init.chip_id = adev->asic_type;
58 pp_init.pm_en = (amdgpu_dpm != 0 && !amdgpu_sriov_vf(adev)) ? true : false;
59 pp_init.feature_mask = amdgpu_pp_feature_mask;
60 pp_init.device = cgs_device;
61 if (call_back_func(&pp_init, &(amd_pp->pp_handle)))
62 return NULL;
63
64 return adev->powerplay.pp_handle;
65}
66
45static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device, 67static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
46 enum cgs_gpu_mem_type type, 68 enum cgs_gpu_mem_type type,
47 uint64_t size, uint64_t align, 69 uint64_t size, uint64_t align,
@@ -1179,6 +1201,7 @@ static const struct cgs_ops amdgpu_cgs_ops = {
1179 .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled, 1201 .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
1180 .enter_safe_mode = amdgpu_cgs_enter_safe_mode, 1202 .enter_safe_mode = amdgpu_cgs_enter_safe_mode,
1181 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx, 1203 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
1204 .register_pp_handle = amdgpu_cgs_register_pp_handle,
1182}; 1205};
1183 1206
1184static const struct cgs_os_ops amdgpu_cgs_os_ops = { 1207static const struct cgs_os_ops amdgpu_cgs_os_ops = {