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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c131
1 files changed, 0 insertions, 131 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 76f4758ead3e..f2dd98d3f5e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -42,131 +42,6 @@ struct amdgpu_cgs_device {
42 ((struct amdgpu_cgs_device *)cgs_device)->adev 42 ((struct amdgpu_cgs_device *)cgs_device)->adev
43 43
44 44
45static int amdgpu_cgs_alloc_gpu_mem(struct cgs_device *cgs_device,
46 enum cgs_gpu_mem_type type,
47 uint64_t size, uint64_t align,
48 cgs_handle_t *handle)
49{
50 CGS_FUNC_ADEV;
51 uint16_t flags = 0;
52 int ret = 0;
53 uint32_t domain = 0;
54 struct amdgpu_bo *obj;
55
56 /* fail if the alignment is not a power of 2 */
57 if (((align != 1) && (align & (align - 1)))
58 || size == 0 || align == 0)
59 return -EINVAL;
60
61
62 switch(type) {
63 case CGS_GPU_MEM_TYPE__VISIBLE_CONTIG_FB:
64 case CGS_GPU_MEM_TYPE__VISIBLE_FB:
65 flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
66 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
67 domain = AMDGPU_GEM_DOMAIN_VRAM;
68 break;
69 case CGS_GPU_MEM_TYPE__INVISIBLE_CONTIG_FB:
70 case CGS_GPU_MEM_TYPE__INVISIBLE_FB:
71 flags = AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
72 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
73 domain = AMDGPU_GEM_DOMAIN_VRAM;
74 break;
75 case CGS_GPU_MEM_TYPE__GART_CACHEABLE:
76 domain = AMDGPU_GEM_DOMAIN_GTT;
77 break;
78 case CGS_GPU_MEM_TYPE__GART_WRITECOMBINE:
79 flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
80 domain = AMDGPU_GEM_DOMAIN_GTT;
81 break;
82 default:
83 return -EINVAL;
84 }
85
86
87 *handle = 0;
88
89 ret = amdgpu_bo_create(adev, size, align, true, domain, flags,
90 NULL, NULL, &obj);
91 if (ret) {
92 DRM_ERROR("(%d) bo create failed\n", ret);
93 return ret;
94 }
95 *handle = (cgs_handle_t)obj;
96
97 return ret;
98}
99
100static int amdgpu_cgs_free_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
101{
102 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
103
104 if (obj) {
105 int r = amdgpu_bo_reserve(obj, true);
106 if (likely(r == 0)) {
107 amdgpu_bo_kunmap(obj);
108 amdgpu_bo_unpin(obj);
109 amdgpu_bo_unreserve(obj);
110 }
111 amdgpu_bo_unref(&obj);
112
113 }
114 return 0;
115}
116
117static int amdgpu_cgs_gmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
118 uint64_t *mcaddr)
119{
120 int r;
121 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
122
123 WARN_ON_ONCE(obj->placement.num_placement > 1);
124
125 r = amdgpu_bo_reserve(obj, true);
126 if (unlikely(r != 0))
127 return r;
128 r = amdgpu_bo_pin(obj, obj->preferred_domains, mcaddr);
129 amdgpu_bo_unreserve(obj);
130 return r;
131}
132
133static int amdgpu_cgs_gunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
134{
135 int r;
136 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
137 r = amdgpu_bo_reserve(obj, true);
138 if (unlikely(r != 0))
139 return r;
140 r = amdgpu_bo_unpin(obj);
141 amdgpu_bo_unreserve(obj);
142 return r;
143}
144
145static int amdgpu_cgs_kmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle,
146 void **map)
147{
148 int r;
149 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
150 r = amdgpu_bo_reserve(obj, true);
151 if (unlikely(r != 0))
152 return r;
153 r = amdgpu_bo_kmap(obj, map);
154 amdgpu_bo_unreserve(obj);
155 return r;
156}
157
158static int amdgpu_cgs_kunmap_gpu_mem(struct cgs_device *cgs_device, cgs_handle_t handle)
159{
160 int r;
161 struct amdgpu_bo *obj = (struct amdgpu_bo *)handle;
162 r = amdgpu_bo_reserve(obj, true);
163 if (unlikely(r != 0))
164 return r;
165 amdgpu_bo_kunmap(obj);
166 amdgpu_bo_unreserve(obj);
167 return r;
168}
169
170static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset) 45static uint32_t amdgpu_cgs_read_register(struct cgs_device *cgs_device, unsigned offset)
171{ 46{
172 CGS_FUNC_ADEV; 47 CGS_FUNC_ADEV;
@@ -906,12 +781,6 @@ static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool ena
906} 781}
907 782
908static const struct cgs_ops amdgpu_cgs_ops = { 783static const struct cgs_ops amdgpu_cgs_ops = {
909 .alloc_gpu_mem = amdgpu_cgs_alloc_gpu_mem,
910 .free_gpu_mem = amdgpu_cgs_free_gpu_mem,
911 .gmap_gpu_mem = amdgpu_cgs_gmap_gpu_mem,
912 .gunmap_gpu_mem = amdgpu_cgs_gunmap_gpu_mem,
913 .kmap_gpu_mem = amdgpu_cgs_kmap_gpu_mem,
914 .kunmap_gpu_mem = amdgpu_cgs_kunmap_gpu_mem,
915 .read_register = amdgpu_cgs_read_register, 784 .read_register = amdgpu_cgs_read_register,
916 .write_register = amdgpu_cgs_write_register, 785 .write_register = amdgpu_cgs_write_register,
917 .read_ind_register = amdgpu_cgs_read_ind_register, 786 .read_ind_register = amdgpu_cgs_read_ind_register,
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-25 11:06:55 -0400