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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c197
1 files changed, 0 insertions, 197 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
index 71a57b2f7f04..dc28fa63bf51 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c
@@ -23,7 +23,6 @@
23 */ 23 */
24#include <linux/list.h> 24#include <linux/list.h>
25#include <linux/slab.h> 25#include <linux/slab.h>
26#include <linux/pci.h>
27#include <drm/drmP.h> 26#include <drm/drmP.h>
28#include <linux/firmware.h> 27#include <linux/firmware.h>
29#include <drm/amdgpu_drm.h> 28#include <drm/amdgpu_drm.h>
@@ -109,78 +108,6 @@ static void amdgpu_cgs_write_ind_register(struct cgs_device *cgs_device,
109 WARN(1, "Invalid indirect register space"); 108 WARN(1, "Invalid indirect register space");
110} 109}
111 110
112static int amdgpu_cgs_get_pci_resource(struct cgs_device *cgs_device,
113 enum cgs_resource_type resource_type,
114 uint64_t size,
115 uint64_t offset,
116 uint64_t *resource_base)
117{
118 CGS_FUNC_ADEV;
119
120 if (resource_base == NULL)
121 return -EINVAL;
122
123 switch (resource_type) {
124 case CGS_RESOURCE_TYPE_MMIO:
125 if (adev->rmmio_size == 0)
126 return -ENOENT;
127 if ((offset + size) > adev->rmmio_size)
128 return -EINVAL;
129 *resource_base = adev->rmmio_base;
130 return 0;
131 case CGS_RESOURCE_TYPE_DOORBELL:
132 if (adev->doorbell.size == 0)
133 return -ENOENT;
134 if ((offset + size) > adev->doorbell.size)
135 return -EINVAL;
136 *resource_base = adev->doorbell.base;
137 return 0;
138 case CGS_RESOURCE_TYPE_FB:
139 case CGS_RESOURCE_TYPE_IO:
140 case CGS_RESOURCE_TYPE_ROM:
141 default:
142 return -EINVAL;
143 }
144}
145
146static const void *amdgpu_cgs_atom_get_data_table(struct cgs_device *cgs_device,
147 unsigned table, uint16_t *size,
148 uint8_t *frev, uint8_t *crev)
149{
150 CGS_FUNC_ADEV;
151 uint16_t data_start;
152
153 if (amdgpu_atom_parse_data_header(
154 adev->mode_info.atom_context, table, size,
155 frev, crev, &data_start))
156 return (uint8_t*)adev->mode_info.atom_context->bios +
157 data_start;
158
159 return NULL;
160}
161
162static int amdgpu_cgs_atom_get_cmd_table_revs(struct cgs_device *cgs_device, unsigned table,
163 uint8_t *frev, uint8_t *crev)
164{
165 CGS_FUNC_ADEV;
166
167 if (amdgpu_atom_parse_cmd_header(
168 adev->mode_info.atom_context, table,
169 frev, crev))
170 return 0;
171
172 return -EINVAL;
173}
174
175static int amdgpu_cgs_atom_exec_cmd_table(struct cgs_device *cgs_device, unsigned table,
176 void *args)
177{
178 CGS_FUNC_ADEV;
179
180 return amdgpu_atom_execute_table(
181 adev->mode_info.atom_context, table, args);
182}
183
184static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device, 111static int amdgpu_cgs_set_clockgating_state(struct cgs_device *cgs_device,
185 enum amd_ip_block_type block_type, 112 enum amd_ip_block_type block_type,
186 enum amd_clockgating_state state) 113 enum amd_clockgating_state state)
@@ -223,7 +150,6 @@ static int amdgpu_cgs_set_powergating_state(struct cgs_device *cgs_device,
223 return r; 150 return r;
224} 151}
225 152
226
227static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) 153static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
228{ 154{
229 CGS_FUNC_ADEV; 155 CGS_FUNC_ADEV;
@@ -271,18 +197,6 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type)
271 return result; 197 return result;
272} 198}
273 199
274static int amdgpu_cgs_rel_firmware(struct cgs_device *cgs_device, enum cgs_ucode_id type)
275{
276 CGS_FUNC_ADEV;
277 if ((CGS_UCODE_ID_SMU == type) || (CGS_UCODE_ID_SMU_SK == type)) {
278 release_firmware(adev->pm.fw);
279 adev->pm.fw = NULL;
280 return 0;
281 }
282 /* cannot release other firmware because they are not created by cgs */
283 return -EINVAL;
284}
285
286static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device, 200static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
287 enum cgs_ucode_id type) 201 enum cgs_ucode_id type)
288{ 202{
@@ -326,34 +240,6 @@ static uint16_t amdgpu_get_firmware_version(struct cgs_device *cgs_device,
326 return fw_version; 240 return fw_version;
327} 241}
328 242
329static int amdgpu_cgs_enter_safe_mode(struct cgs_device *cgs_device,
330 bool en)
331{
332 CGS_FUNC_ADEV;
333
334 if (adev->gfx.rlc.funcs->enter_safe_mode == NULL ||
335 adev->gfx.rlc.funcs->exit_safe_mode == NULL)
336 return 0;
337
338 if (en)
339 adev->gfx.rlc.funcs->enter_safe_mode(adev);
340 else
341 adev->gfx.rlc.funcs->exit_safe_mode(adev);
342
343 return 0;
344}
345
346static void amdgpu_cgs_lock_grbm_idx(struct cgs_device *cgs_device,
347 bool lock)
348{
349 CGS_FUNC_ADEV;
350
351 if (lock)
352 mutex_lock(&adev->grbm_idx_mutex);
353 else
354 mutex_unlock(&adev->grbm_idx_mutex);
355}
356
357static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, 243static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
358 enum cgs_ucode_id type, 244 enum cgs_ucode_id type,
359 struct cgs_firmware_info *info) 245 struct cgs_firmware_info *info)
@@ -598,97 +484,14 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device,
598 return 0; 484 return 0;
599} 485}
600 486
601static int amdgpu_cgs_is_virtualization_enabled(void *cgs_device)
602{
603 CGS_FUNC_ADEV;
604 return amdgpu_sriov_vf(adev);
605}
606
607static int amdgpu_cgs_get_active_displays_info(struct cgs_device *cgs_device,
608 struct cgs_display_info *info)
609{
610 CGS_FUNC_ADEV;
611 struct cgs_mode_info *mode_info;
612
613 if (info == NULL)
614 return -EINVAL;
615
616 mode_info = info->mode_info;
617 if (mode_info)
618 /* if the displays are off, vblank time is max */
619 mode_info->vblank_time_us = 0xffffffff;
620
621 if (!amdgpu_device_has_dc_support(adev)) {
622 struct amdgpu_crtc *amdgpu_crtc;
623 struct drm_device *ddev = adev->ddev;
624 struct drm_crtc *crtc;
625 uint32_t line_time_us, vblank_lines;
626
627 if (adev->mode_info.num_crtc && adev->mode_info.mode_config_initialized) {
628 list_for_each_entry(crtc,
629 &ddev->mode_config.crtc_list, head) {
630 amdgpu_crtc = to_amdgpu_crtc(crtc);
631 if (crtc->enabled) {
632 info->active_display_mask |= (1 << amdgpu_crtc->crtc_id);
633 info->display_count++;
634 }
635 if (mode_info != NULL &&
636 crtc->enabled && amdgpu_crtc->enabled &&
637 amdgpu_crtc->hw_mode.clock) {
638 line_time_us = (amdgpu_crtc->hw_mode.crtc_htotal * 1000) /
639 amdgpu_crtc->hw_mode.clock;
640 vblank_lines = amdgpu_crtc->hw_mode.crtc_vblank_end -
641 amdgpu_crtc->hw_mode.crtc_vdisplay +
642 (amdgpu_crtc->v_border * 2);
643 mode_info->vblank_time_us = vblank_lines * line_time_us;
644 mode_info->refresh_rate = drm_mode_vrefresh(&amdgpu_crtc->hw_mode);
645 /* we have issues with mclk switching with refresh rates
646 * over 120 hz on the non-DC code.
647 */
648 if (mode_info->refresh_rate > 120)
649 mode_info->vblank_time_us = 0;
650 mode_info = NULL;
651 }
652 }
653 }
654 } else {
655 info->display_count = adev->pm.pm_display_cfg.num_display;
656 if (mode_info != NULL) {
657 mode_info->vblank_time_us = adev->pm.pm_display_cfg.min_vblank_time;
658 mode_info->refresh_rate = adev->pm.pm_display_cfg.vrefresh;
659 }
660 }
661 return 0;
662}
663
664
665static int amdgpu_cgs_notify_dpm_enabled(struct cgs_device *cgs_device, bool enabled)
666{
667 CGS_FUNC_ADEV;
668
669 adev->pm.dpm_enabled = enabled;
670
671 return 0;
672}
673
674static const struct cgs_ops amdgpu_cgs_ops = { 487static const struct cgs_ops amdgpu_cgs_ops = {
675 .read_register = amdgpu_cgs_read_register, 488 .read_register = amdgpu_cgs_read_register,
676 .write_register = amdgpu_cgs_write_register, 489 .write_register = amdgpu_cgs_write_register,
677 .read_ind_register = amdgpu_cgs_read_ind_register, 490 .read_ind_register = amdgpu_cgs_read_ind_register,
678 .write_ind_register = amdgpu_cgs_write_ind_register, 491 .write_ind_register = amdgpu_cgs_write_ind_register,
679 .get_pci_resource = amdgpu_cgs_get_pci_resource,
680 .atom_get_data_table = amdgpu_cgs_atom_get_data_table,
681 .atom_get_cmd_table_revs = amdgpu_cgs_atom_get_cmd_table_revs,
682 .atom_exec_cmd_table = amdgpu_cgs_atom_exec_cmd_table,
683 .get_firmware_info = amdgpu_cgs_get_firmware_info, 492 .get_firmware_info = amdgpu_cgs_get_firmware_info,
684 .rel_firmware = amdgpu_cgs_rel_firmware,
685 .set_powergating_state = amdgpu_cgs_set_powergating_state, 493 .set_powergating_state = amdgpu_cgs_set_powergating_state,
686 .set_clockgating_state = amdgpu_cgs_set_clockgating_state, 494 .set_clockgating_state = amdgpu_cgs_set_clockgating_state,
687 .get_active_displays_info = amdgpu_cgs_get_active_displays_info,
688 .notify_dpm_enabled = amdgpu_cgs_notify_dpm_enabled,
689 .is_virtualization_enabled = amdgpu_cgs_is_virtualization_enabled,
690 .enter_safe_mode = amdgpu_cgs_enter_safe_mode,
691 .lock_grbm_idx = amdgpu_cgs_lock_grbm_idx,
692}; 495};
693 496
694struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev) 497struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev)
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-29 10:00:33 -0400