1 files changed, 112 insertions, 0 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
new file mode 100644
index 000000000000..4b9abd68e04f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.c
@@ -0,0 +1,112 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include <drm/drmP.h>
+#include <drm/amdgpu_drm.h>
+#include "amdgpu.h"
+#include "atomfirmware.h"
+#include "amdgpu_atomfirmware.h"
+#include "atom.h"
+
+#define get_index_into_master_table(master_table, table_name) (offsetof(struct master_table, table_name) / sizeof(uint16_t))
+
+bool amdgpu_atomfirmware_gpu_supports_virtualization(struct amdgpu_device *adev)
+{
+        int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                                                firmwareinfo);
+        uint16_t data_offset;
+
+        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
+                                          NULL, NULL, &data_offset)) {
+                struct atom_firmware_info_v3_1 *firmware_info =
+                        (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
+                                                           data_offset);
+
+                if (le32_to_cpu(firmware_info->firmware_capability) &
+                    ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION)
+                        return true;
+        }
+        return false;
+}
+
+void amdgpu_atomfirmware_scratch_regs_init(struct amdgpu_device *adev)
+{
+        int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                                                firmwareinfo);
+        uint16_t data_offset;
+
+        if (amdgpu_atom_parse_data_header(adev->mode_info.atom_context, index, NULL,
+                                          NULL, NULL, &data_offset)) {
+                struct atom_firmware_info_v3_1 *firmware_info =
+                        (struct atom_firmware_info_v3_1 *)(adev->mode_info.atom_context->bios +
+                                                           data_offset);
+
+                adev->bios_scratch_reg_offset =
+                        le32_to_cpu(firmware_info->bios_scratch_reg_startaddr);
+        }
+}
+
+void amdgpu_atomfirmware_scratch_regs_save(struct amdgpu_device *adev)
+{
+        int i;
+
+        for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
+                adev->bios_scratch[i] = RREG32(adev->bios_scratch_reg_offset + i);
+}
+
+void amdgpu_atomfirmware_scratch_regs_restore(struct amdgpu_device *adev)
+{
+        int i;
+
+        for (i = 0; i < AMDGPU_BIOS_NUM_SCRATCH; i++)
+                WREG32(adev->bios_scratch_reg_offset + i, adev->bios_scratch[i]);
+}
+
+int amdgpu_atomfirmware_allocate_fb_scratch(struct amdgpu_device *adev)
+{
+        struct atom_context *ctx = adev->mode_info.atom_context;
+        int index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
+                                                vram_usagebyfirmware);
+        uint16_t data_offset;
+        int usage_bytes = 0;
+
+        if (amdgpu_atom_parse_data_header(ctx, index, NULL, NULL, NULL, &data_offset)) {
+                struct vram_usagebyfirmware_v2_1 *firmware_usage =
+                        (struct vram_usagebyfirmware_v2_1 *)(ctx->bios + data_offset);
+
+                DRM_DEBUG("atom firmware requested %08x %dkb fw %dkb drv\n",
+                          le32_to_cpu(firmware_usage->start_address_in_kb),
+                          le16_to_cpu(firmware_usage->used_by_firmware_in_kb),
+                          le16_to_cpu(firmware_usage->used_by_driver_in_kb));
+
+                usage_bytes = le16_to_cpu(firmware_usage->used_by_driver_in_kb) * 1024;
+        }
+        ctx->scratch_size_bytes = 0;
+        if (usage_bytes == 0)
+                usage_bytes = 20 * 1024;
+        /* allocate some scratch memory */
+        ctx->scratch = kzalloc(usage_bytes, GFP_KERNEL);
+        if (!ctx->scratch)
+                return -ENOMEM;
+        ctx->scratch_size_bytes = usage_bytes;
+        return 0;
+}