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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c47
1 files changed, 37 insertions, 10 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
index f4c474a95875..71efcf38f11b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_acp.c
@@ -57,6 +57,10 @@
57#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8 57#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
58#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c 58#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
59#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68 59#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
60#define ACP_BT_PLAY_REGS_START 0x14970
61#define ACP_BT_PLAY_REGS_END 0x14a24
62#define ACP_BT_COMP1_REG_OFFSET 0xac
63#define ACP_BT_COMP2_REG_OFFSET 0xa8
60 64
61#define mmACP_PGFSM_RETAIN_REG 0x51c9 65#define mmACP_PGFSM_RETAIN_REG 0x51c9
62#define mmACP_PGFSM_CONFIG_REG 0x51ca 66#define mmACP_PGFSM_CONFIG_REG 0x51ca
@@ -77,7 +81,7 @@
77#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF 81#define ACP_SOFT_RESET_DONE_TIME_OUT_VALUE 0x000000FF
78 82
79#define ACP_TIMEOUT_LOOP 0x000000FF 83#define ACP_TIMEOUT_LOOP 0x000000FF
80#define ACP_DEVS 3 84#define ACP_DEVS 4
81#define ACP_SRC_ID 162 85#define ACP_SRC_ID 162
82 86
83enum { 87enum {
@@ -316,14 +320,13 @@ static int acp_hw_init(void *handle)
316 if (adev->acp.acp_cell == NULL) 320 if (adev->acp.acp_cell == NULL)
317 return -ENOMEM; 321 return -ENOMEM;
318 322
319 adev->acp.acp_res = kcalloc(4, sizeof(struct resource), GFP_KERNEL); 323 adev->acp.acp_res = kcalloc(5, sizeof(struct resource), GFP_KERNEL);
320
321 if (adev->acp.acp_res == NULL) { 324 if (adev->acp.acp_res == NULL) {
322 kfree(adev->acp.acp_cell); 325 kfree(adev->acp.acp_cell);
323 return -ENOMEM; 326 return -ENOMEM;
324 } 327 }
325 328
326 i2s_pdata = kcalloc(2, sizeof(struct i2s_platform_data), GFP_KERNEL); 329 i2s_pdata = kcalloc(3, sizeof(struct i2s_platform_data), GFP_KERNEL);
327 if (i2s_pdata == NULL) { 330 if (i2s_pdata == NULL) {
328 kfree(adev->acp.acp_res); 331 kfree(adev->acp.acp_res);
329 kfree(adev->acp.acp_cell); 332 kfree(adev->acp.acp_cell);
@@ -358,6 +361,20 @@ static int acp_hw_init(void *handle)
358 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET; 361 i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
359 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET; 362 i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
360 363
364 i2s_pdata[2].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
365 switch (adev->asic_type) {
366 case CHIP_STONEY:
367 i2s_pdata[2].quirks |= DW_I2S_QUIRK_16BIT_IDX_OVERRIDE;
368 break;
369 default:
370 break;
371 }
372
373 i2s_pdata[2].cap = DWC_I2S_PLAY | DWC_I2S_RECORD;
374 i2s_pdata[2].snd_rates = SNDRV_PCM_RATE_8000_96000;
375 i2s_pdata[2].i2s_reg_comp1 = ACP_BT_COMP1_REG_OFFSET;
376 i2s_pdata[2].i2s_reg_comp2 = ACP_BT_COMP2_REG_OFFSET;
377
361 adev->acp.acp_res[0].name = "acp2x_dma"; 378 adev->acp.acp_res[0].name = "acp2x_dma";
362 adev->acp.acp_res[0].flags = IORESOURCE_MEM; 379 adev->acp.acp_res[0].flags = IORESOURCE_MEM;
363 adev->acp.acp_res[0].start = acp_base; 380 adev->acp.acp_res[0].start = acp_base;
@@ -373,13 +390,18 @@ static int acp_hw_init(void *handle)
373 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START; 390 adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
374 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END; 391 adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
375 392
376 adev->acp.acp_res[3].name = "acp2x_dma_irq"; 393 adev->acp.acp_res[3].name = "acp2x_dw_bt_i2s_play_cap";
377 adev->acp.acp_res[3].flags = IORESOURCE_IRQ; 394 adev->acp.acp_res[3].flags = IORESOURCE_MEM;
378 adev->acp.acp_res[3].start = amdgpu_irq_create_mapping(adev, 162); 395 adev->acp.acp_res[3].start = acp_base + ACP_BT_PLAY_REGS_START;
379 adev->acp.acp_res[3].end = adev->acp.acp_res[3].start; 396 adev->acp.acp_res[3].end = acp_base + ACP_BT_PLAY_REGS_END;
397
398 adev->acp.acp_res[4].name = "acp2x_dma_irq";
399 adev->acp.acp_res[4].flags = IORESOURCE_IRQ;
400 adev->acp.acp_res[4].start = amdgpu_irq_create_mapping(adev, 162);
401 adev->acp.acp_res[4].end = adev->acp.acp_res[4].start;
380 402
381 adev->acp.acp_cell[0].name = "acp_audio_dma"; 403 adev->acp.acp_cell[0].name = "acp_audio_dma";
382 adev->acp.acp_cell[0].num_resources = 4; 404 adev->acp.acp_cell[0].num_resources = 5;
383 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0]; 405 adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
384 adev->acp.acp_cell[0].platform_data = &adev->asic_type; 406 adev->acp.acp_cell[0].platform_data = &adev->asic_type;
385 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type); 407 adev->acp.acp_cell[0].pdata_size = sizeof(adev->asic_type);
@@ -396,6 +418,12 @@ static int acp_hw_init(void *handle)
396 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1]; 418 adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
397 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data); 419 adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
398 420
421 adev->acp.acp_cell[3].name = "designware-i2s";
422 adev->acp.acp_cell[3].num_resources = 1;
423 adev->acp.acp_cell[3].resources = &adev->acp.acp_res[3];
424 adev->acp.acp_cell[3].platform_data = &i2s_pdata[2];
425 adev->acp.acp_cell[3].pdata_size = sizeof(struct i2s_platform_data);
426
399 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell, 427 r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
400 ACP_DEVS); 428 ACP_DEVS);
401 if (r) 429 if (r)
@@ -451,7 +479,6 @@ static int acp_hw_init(void *handle)
451 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET); 479 val = cgs_read_register(adev->acp.cgs_device, mmACP_SOFT_RESET);
452 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK; 480 val &= ~ACP_SOFT_RESET__SoftResetAud_MASK;
453 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val); 481 cgs_write_register(adev->acp.cgs_device, mmACP_SOFT_RESET, val);
454
455 return 0; 482 return 0;
456} 483}
457 484