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path: root/drivers/gpu/drm/amd/amdgpu/amdgpu.h
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Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu.h')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/amdgpu.h37
1 files changed, 31 insertions, 6 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a23b8af95319..cbcb6a153aba 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -732,10 +732,14 @@ struct amdgpu_ctx {
732 struct amdgpu_device *adev; 732 struct amdgpu_device *adev;
733 struct amdgpu_queue_mgr queue_mgr; 733 struct amdgpu_queue_mgr queue_mgr;
734 unsigned reset_counter; 734 unsigned reset_counter;
735 uint32_t vram_lost_counter;
735 spinlock_t ring_lock; 736 spinlock_t ring_lock;
736 struct dma_fence **fences; 737 struct dma_fence **fences;
737 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS]; 738 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
738 bool preamble_presented; 739 bool preamble_presented;
740 enum amd_sched_priority init_priority;
741 enum amd_sched_priority override_priority;
742 struct mutex lock;
739}; 743};
740 744
741struct amdgpu_ctx_mgr { 745struct amdgpu_ctx_mgr {
@@ -752,13 +756,18 @@ int amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
752 struct dma_fence *fence, uint64_t *seq); 756 struct dma_fence *fence, uint64_t *seq);
753struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx, 757struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
754 struct amdgpu_ring *ring, uint64_t seq); 758 struct amdgpu_ring *ring, uint64_t seq);
759void amdgpu_ctx_priority_override(struct amdgpu_ctx *ctx,
760 enum amd_sched_priority priority);
755 761
756int amdgpu_ctx_ioctl(struct drm_device *dev, void *data, 762int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
757 struct drm_file *filp); 763 struct drm_file *filp);
758 764
765int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
766
759void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr); 767void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
760void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr); 768void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
761 769
770
762/* 771/*
763 * file private structure 772 * file private structure
764 */ 773 */
@@ -770,7 +779,6 @@ struct amdgpu_fpriv {
770 struct mutex bo_list_lock; 779 struct mutex bo_list_lock;
771 struct idr bo_list_handles; 780 struct idr bo_list_handles;
772 struct amdgpu_ctx_mgr ctx_mgr; 781 struct amdgpu_ctx_mgr ctx_mgr;
773 u32 vram_lost_counter;
774}; 782};
775 783
776/* 784/*
@@ -871,7 +879,7 @@ struct amdgpu_mec {
871struct amdgpu_kiq { 879struct amdgpu_kiq {
872 u64 eop_gpu_addr; 880 u64 eop_gpu_addr;
873 struct amdgpu_bo *eop_obj; 881 struct amdgpu_bo *eop_obj;
874 struct mutex ring_mutex; 882 spinlock_t ring_lock;
875 struct amdgpu_ring ring; 883 struct amdgpu_ring ring;
876 struct amdgpu_irq_src irq; 884 struct amdgpu_irq_src irq;
877}; 885};
@@ -1035,6 +1043,10 @@ struct amdgpu_gfx {
1035 bool in_suspend; 1043 bool in_suspend;
1036 /* NGG */ 1044 /* NGG */
1037 struct amdgpu_ngg ngg; 1045 struct amdgpu_ngg ngg;
1046
1047 /* pipe reservation */
1048 struct mutex pipe_reserve_mutex;
1049 DECLARE_BITMAP (pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1038}; 1050};
1039 1051
1040int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm, 1052int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
@@ -1113,6 +1125,7 @@ struct amdgpu_job {
1113 uint32_t gds_base, gds_size; 1125 uint32_t gds_base, gds_size;
1114 uint32_t gws_base, gws_size; 1126 uint32_t gws_base, gws_size;
1115 uint32_t oa_base, oa_size; 1127 uint32_t oa_base, oa_size;
1128 uint32_t vram_lost_counter;
1116 1129
1117 /* user fence handling */ 1130 /* user fence handling */
1118 uint64_t uf_addr; 1131 uint64_t uf_addr;
@@ -1138,7 +1151,7 @@ static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1138/* 1151/*
1139 * Writeback 1152 * Writeback
1140 */ 1153 */
1141#define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */ 1154#define AMDGPU_MAX_WB 512 /* Reserve at most 512 WB slots for amdgpu-owned rings. */
1142 1155
1143struct amdgpu_wb { 1156struct amdgpu_wb {
1144 struct amdgpu_bo *wb_obj; 1157 struct amdgpu_bo *wb_obj;
@@ -1379,6 +1392,18 @@ struct amdgpu_atcs {
1379}; 1392};
1380 1393
1381/* 1394/*
1395 * Firmware VRAM reservation
1396 */
1397struct amdgpu_fw_vram_usage {
1398 u64 start_offset;
1399 u64 size;
1400 struct amdgpu_bo *reserved_bo;
1401 void *va;
1402};
1403
1404int amdgpu_fw_reserve_vram_init(struct amdgpu_device *adev);
1405
1406/*
1382 * CGS 1407 * CGS
1383 */ 1408 */
1384struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev); 1409struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
@@ -1582,6 +1607,8 @@ struct amdgpu_device {
1582 struct delayed_work late_init_work; 1607 struct delayed_work late_init_work;
1583 1608
1584 struct amdgpu_virt virt; 1609 struct amdgpu_virt virt;
1610 /* firmware VRAM reservation */
1611 struct amdgpu_fw_vram_usage fw_vram_usage;
1585 1612
1586 /* link all shadow bo */ 1613 /* link all shadow bo */
1587 struct list_head shadow_list; 1614 struct list_head shadow_list;
@@ -1833,8 +1860,6 @@ static inline bool amdgpu_has_atpx(void) { return false; }
1833extern const struct drm_ioctl_desc amdgpu_ioctls_kms[]; 1860extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1834extern const int amdgpu_max_kms_ioctl; 1861extern const int amdgpu_max_kms_ioctl;
1835 1862
1836bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1837 struct amdgpu_fpriv *fpriv);
1838int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags); 1863int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1839void amdgpu_driver_unload_kms(struct drm_device *dev); 1864void amdgpu_driver_unload_kms(struct drm_device *dev);
1840void amdgpu_driver_lastclose_kms(struct drm_device *dev); 1865void amdgpu_driver_lastclose_kms(struct drm_device *dev);