1 files changed, 42 insertions, 3 deletions

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index c8b605f3dc05..a59c07590cee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -129,6 +129,7 @@ extern int amdgpu_lbpw;
 extern int amdgpu_compute_multipipe;
 extern int amdgpu_gpu_recovery;
 extern int amdgpu_emu_mode;
+extern uint amdgpu_smu_memory_pool_size;
 
 #ifdef CONFIG_DRM_AMDGPU_SI
 extern int amdgpu_si_support;
@@ -137,6 +138,7 @@ extern int amdgpu_si_support;
 extern int amdgpu_cik_support;
 #endif
 
+#define AMDGPU_SG_THRESHOLD                     (256*1024*1024)
 #define AMDGPU_DEFAULT_GTT_SIZE_MB              3072ULL /* 3GB by default */
 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS          3000
 #define AMDGPU_MAX_USEC_TIMEOUT                 100000  /* 100 ms */
@@ -222,10 +224,10 @@ enum amdgpu_kiq_irq {
         AMDGPU_CP_KIQ_IRQ_LAST
 };
 
-int amdgpu_device_ip_set_clockgating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_clockgating_state(void *dev,
                                            enum amd_ip_block_type block_type,
                                            enum amd_clockgating_state state);
-int amdgpu_device_ip_set_powergating_state(struct amdgpu_device *adev,
+int amdgpu_device_ip_set_powergating_state(void *dev,
                                            enum amd_ip_block_type block_type,
                                            enum amd_powergating_state state);
 void amdgpu_device_ip_get_clockgating_state(struct amdgpu_device *adev,
@@ -681,6 +683,8 @@ int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
 int amdgpu_ctx_wait_prev_fence(struct amdgpu_ctx *ctx, unsigned ring_id);
 
 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
+void amdgpu_ctx_mgr_entity_cleanup(struct amdgpu_ctx_mgr *mgr);
+void amdgpu_ctx_mgr_entity_fini(struct amdgpu_ctx_mgr *mgr);
 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
 
 
@@ -771,9 +775,18 @@ struct amdgpu_rlc {
         u32 starting_offsets_start;
         u32 reg_list_format_size_bytes;
         u32 reg_list_size_bytes;
+        u32 reg_list_format_direct_reg_list_length;
+        u32 save_restore_list_cntl_size_bytes;
+        u32 save_restore_list_gpm_size_bytes;
+        u32 save_restore_list_srm_size_bytes;
 
         u32 *register_list_format;
         u32 *register_restore;
+        u8 *save_restore_list_cntl;
+        u8 *save_restore_list_gpm;
+        u8 *save_restore_list_srm;
+
+        bool is_rlc_v2_1;
 };
 
 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
@@ -867,6 +880,8 @@ struct amdgpu_gfx_config {
 
         /* gfx configure feature */
         uint32_t double_offchip_lds_buf;
+        /* cached value of DB_DEBUG2 */
+        uint32_t db_debug2;
 };
 
 struct amdgpu_cu_info {
@@ -938,6 +953,12 @@ struct amdgpu_gfx {
         uint32_t                        ce_feature_version;
         uint32_t                        pfp_feature_version;
         uint32_t                        rlc_feature_version;
+        uint32_t                        rlc_srlc_fw_version;
+        uint32_t                        rlc_srlc_feature_version;
+        uint32_t                        rlc_srlg_fw_version;
+        uint32_t                        rlc_srlg_feature_version;
+        uint32_t                        rlc_srls_fw_version;
+        uint32_t                        rlc_srls_feature_version;
         uint32_t                        mec_feature_version;
         uint32_t                        mec2_feature_version;
         struct amdgpu_ring              gfx_ring[AMDGPU_MAX_GFX_RINGS];
@@ -1204,6 +1225,8 @@ struct amdgpu_asic_funcs {
         /* invalidate hdp read cache */
         void (*invalidate_hdp)(struct amdgpu_device *adev,
                                struct amdgpu_ring *ring);
+        /* check if the asic needs a full reset of if soft reset will work */
+        bool (*need_full_reset)(struct amdgpu_device *adev);
 };
 
 /*
@@ -1368,7 +1391,19 @@ struct amdgpu_nbio_funcs {
         void (*detect_hw_virt)(struct amdgpu_device *adev);
 };
 
-
+struct amdgpu_df_funcs {
+        void (*init)(struct amdgpu_device *adev);
+        void (*enable_broadcast_mode)(struct amdgpu_device *adev,
+                                      bool enable);
+        u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
+        u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
+        void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
+                                                 bool enable);
+        void (*get_clockgating_state)(struct amdgpu_device *adev,
+                                      u32 *flags);
+        void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev,
+                                            bool enable);
+};
 /* Define the HW IP blocks will be used in driver , add more if necessary */
 enum amd_hw_ip_block_type {
         GC_HWIP = 1,
@@ -1398,6 +1433,7 @@ enum amd_hw_ip_block_type {
 struct amd_powerplay {
         void *pp_handle;
         const struct amd_pm_funcs *pp_funcs;
+        uint32_t pp_feature;
 };
 
 #define AMDGPU_RESET_MAGIC_NUM 64
@@ -1590,6 +1626,7 @@ struct amdgpu_device {
         uint32_t                *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
 
         const struct amdgpu_nbio_funcs  *nbio_funcs;
+        const struct amdgpu_df_funcs    *df_funcs;
 
         /* delayed work_func for deferring clockgating during resume */
         struct delayed_work     late_init_work;
@@ -1764,6 +1801,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
 #define amdgpu_asic_flush_hdp(adev, r) (adev)->asic_funcs->flush_hdp((adev), (r))
 #define amdgpu_asic_invalidate_hdp(adev, r) (adev)->asic_funcs->invalidate_hdp((adev), (r))
+#define amdgpu_asic_need_full_reset(adev) (adev)->asic_funcs->need_full_reset((adev))
 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid) (adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid))
 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr))
 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid))
@@ -1790,6 +1828,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
 #define amdgpu_ring_emit_reg_wait(r, d, v, m) (r)->funcs->emit_reg_wait((r), (d), (v), (m))
+#define amdgpu_ring_emit_reg_write_reg_wait(r, d0, d1, v, m) (r)->funcs->emit_reg_write_reg_wait((r), (d0), (d1), (v), (m))
 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))