11 files changed, 33 insertions, 56 deletions

diff --git a/drivers/fpga/altera-cvp.c b/drivers/fpga/altera-cvp.c
index 35c3aa5792e2..770915fb97f9 100644
--- a/drivers/fpga/altera-cvp.c
+++ b/drivers/fpga/altera-cvp.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * FPGA Manager Driver for Altera Arria/Cyclone/Stratix CvP
  *
@@ -5,15 +6,6 @@
  *
  * Anatolij Gustschin <agust@denx.de>
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
  * Manage Altera FPGA firmware using PCIe CvP.
  * Firmware must be in binary "rbf" format.
  */
diff --git a/drivers/fpga/altera-ps-spi.c b/drivers/fpga/altera-ps-spi.c
index 678d0115f840..a13f224303c6 100644
--- a/drivers/fpga/altera-ps-spi.c
+++ b/drivers/fpga/altera-ps-spi.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Altera Passive Serial SPI Driver
  *
@@ -5,10 +6,6 @@
  *
  *  Joshua Clayton <stillcompiling@gmail.com>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
  * Manage Altera FPGA firmware that is loaded over SPI using the passive
  * serial configuration method.
  * Firmware must be in binary "rbf" format.
diff --git a/drivers/fpga/dfl-afu-dma-region.c b/drivers/fpga/dfl-afu-dma-region.c
index c438722bf4e1..dcd80b088c7b 100644
--- a/drivers/fpga/dfl-afu-dma-region.c
+++ b/drivers/fpga/dfl-afu-dma-region.c
@@ -399,7 +399,7 @@ int afu_dma_map_region(struct dfl_feature_platform_data *pdata,
                                     region->pages[0], 0,
                                     region->length,
                                     DMA_BIDIRECTIONAL);
-        if (dma_mapping_error(&pdata->dev->dev, region->iova)) {
+        if (dma_mapping_error(dfl_fpga_pdata_to_parent(pdata), region->iova)) {
                 dev_err(&pdata->dev->dev, "failed to map for dma\n");
                 ret = -EFAULT;
                 goto unpin_pages;
diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index 2c09e502e721..4b66aaa32b5a 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -40,6 +40,13 @@ enum dfl_fpga_devt_type {
         DFL_FPGA_DEVT_MAX,
 };
 
+static struct lock_class_key dfl_pdata_keys[DFL_ID_MAX];
+
+static const char *dfl_pdata_key_strings[DFL_ID_MAX] = {
+        "dfl-fme-pdata",
+        "dfl-port-pdata",
+};
+
 /**
  * dfl_dev_info - dfl feature device information.
  * @name: name string of the feature platform device.
@@ -315,7 +322,7 @@ static void dfl_chardev_uinit(void)
         for (i = 0; i < DFL_FPGA_DEVT_MAX; i++)
                 if (MAJOR(dfl_chrdevs[i].devt)) {
                         unregister_chrdev_region(dfl_chrdevs[i].devt,
-                                                 MINORMASK);
+                                                 MINORMASK + 1);
                         dfl_chrdevs[i].devt = MKDEV(0, 0);
                 }
 }
@@ -325,8 +332,8 @@ static int dfl_chardev_init(void)
         int i, ret;
 
         for (i = 0; i < DFL_FPGA_DEVT_MAX; i++) {
-                ret = alloc_chrdev_region(&dfl_chrdevs[i].devt, 0, MINORMASK,
-                                          dfl_chrdevs[i].name);
+                ret = alloc_chrdev_region(&dfl_chrdevs[i].devt, 0,
+                                          MINORMASK + 1, dfl_chrdevs[i].name);
                 if (ret)
                         goto exit;
         }
@@ -443,11 +450,16 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
         struct platform_device *fdev = binfo->feature_dev;
         struct dfl_feature_platform_data *pdata;
         struct dfl_feature_info *finfo, *p;
+        enum dfl_id_type type;
         int ret, index = 0;
 
         if (!fdev)
                 return 0;
 
+        type = feature_dev_id_type(fdev);
+        if (WARN_ON_ONCE(type >= DFL_ID_MAX))
+                return -EINVAL;
+
         /*
          * we do not need to care for the memory which is associated with
          * the platform device. After calling platform_device_unregister(),
@@ -463,6 +475,8 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
         pdata->num = binfo->feature_num;
         pdata->dfl_cdev = binfo->cdev;
         mutex_init(&pdata->lock);
+        lockdep_set_class_and_name(&pdata->lock, &dfl_pdata_keys[type],
+                                   dfl_pdata_key_strings[type]);
 
         /*
          * the count should be initialized to 0 to make sure
@@ -497,7 +511,7 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo)
 
         ret = platform_device_add(binfo->feature_dev);
         if (!ret) {
-                if (feature_dev_id_type(binfo->feature_dev) == PORT_ID)
+                if (type == PORT_ID)
                         dfl_fpga_cdev_add_port_dev(binfo->cdev,
                                                    binfo->feature_dev);
                 else
diff --git a/drivers/fpga/ice40-spi.c b/drivers/fpga/ice40-spi.c
index 6154661b8f76..56e112e14a10 100644
--- a/drivers/fpga/ice40-spi.c
+++ b/drivers/fpga/ice40-spi.c
@@ -1,12 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * FPGA Manager Driver for Lattice iCE40.
  *
  *  Copyright (c) 2016 Joel Holdsworth
  *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
  * This driver adds support to the FPGA manager for configuring the SRAM of
  * Lattice iCE40 FPGAs through slave SPI.
  */
diff --git a/drivers/fpga/stratix10-soc.c b/drivers/fpga/stratix10-soc.c
index 13851b3d1c56..215d33789c74 100644
--- a/drivers/fpga/stratix10-soc.c
+++ b/drivers/fpga/stratix10-soc.c
@@ -507,12 +507,16 @@ static int __init s10_init(void)
         if (!fw_np)
                 return -ENODEV;
 
+        of_node_get(fw_np);
         np = of_find_matching_node(fw_np, s10_of_match);
-        if (!np)
+        if (!np) {
+                of_node_put(fw_np);
                 return -ENODEV;
+        }
 
         of_node_put(np);
         ret = of_platform_populate(fw_np, s10_of_match, NULL, NULL);
+        of_node_put(fw_np);
         if (ret)
                 return ret;
 
diff --git a/drivers/fpga/ts73xx-fpga.c b/drivers/fpga/ts73xx-fpga.c
index dc22a5842609..9a17fe98c1b0 100644
--- a/drivers/fpga/ts73xx-fpga.c
+++ b/drivers/fpga/ts73xx-fpga.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Technologic Systems TS-73xx SBC FPGA loader
  *
@@ -5,15 +6,6 @@
  *
  * FPGA Manager Driver for the on-board Altera Cyclone II FPGA found on
  * TS-7300, heavily based on load_fpga.c in their vendor tree.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #include <linux/delay.h>
diff --git a/drivers/fpga/xilinx-pr-decoupler.c b/drivers/fpga/xilinx-pr-decoupler.c
index 641036135207..af9b387c56d3 100644
--- a/drivers/fpga/xilinx-pr-decoupler.c
+++ b/drivers/fpga/xilinx-pr-decoupler.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017, National Instruments Corp.
  * Copyright (c) 2017, Xilix Inc
  *
  * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
  * Decoupler IP Core.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/fpga/xilinx-spi.c b/drivers/fpga/xilinx-spi.c
index 469486be20c4..272ee0c22822 100644
--- a/drivers/fpga/xilinx-spi.c
+++ b/drivers/fpga/xilinx-spi.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Xilinx Spartan6 Slave Serial SPI Driver
  *
@@ -5,10 +6,6 @@
  *
  * Anatolij Gustschin <agust@denx.de>
  *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
  * Manage Xilinx FPGA firmware that is loaded over SPI using
  * the slave serial configuration interface.
  */
diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
index 57b0e6775958..31ef38e38537 100644
--- a/drivers/fpga/zynq-fpga.c
+++ b/drivers/fpga/zynq-fpga.c
@@ -1,18 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2011-2015 Xilinx Inc.
  * Copyright (c) 2015, National Instruments Corp.
  *
  * FPGA Manager Driver for Xilinx Zynq, heavily based on xdevcfg driver
  * in their vendor tree.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
  */
 
 #include <linux/clk.h>
diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c
index f7cbaadf49ab..b8a88d21d038 100644
--- a/drivers/fpga/zynqmp-fpga.c
+++ b/drivers/fpga/zynqmp-fpga.c
@@ -47,7 +47,7 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
         char *kbuf;
         int ret;
 
-        if (!eemi_ops || !eemi_ops->fpga_load)
+        if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_load)
                 return -ENXIO;
 
         priv = mgr->priv;
@@ -81,7 +81,7 @@ static enum fpga_mgr_states zynqmp_fpga_ops_state(struct fpga_manager *mgr)
         const struct zynqmp_eemi_ops *eemi_ops = zynqmp_pm_get_eemi_ops();
         u32 status;
 
-        if (!eemi_ops || !eemi_ops->fpga_get_status)
+        if (IS_ERR_OR_NULL(eemi_ops) || !eemi_ops->fpga_get_status)
                 return FPGA_MGR_STATE_UNKNOWN;
 
         eemi_ops->fpga_get_status(&status);