1 files changed, 100 insertions, 107 deletions

diff --git a/drivers/edac/i5000_edac.c b/drivers/edac/i5000_edac.c
index 11ea835f155a..39c63757c2a1 100644
--- a/drivers/edac/i5000_edac.c
+++ b/drivers/edac/i5000_edac.c
@@ -273,7 +273,7 @@
 #define CHANNELS_PER_BRANCH     2
 #define MAX_BRANCHES            2
 
-/* Defines to extract the vaious fields from the
+/* Defines to extract the various fields from the
  *      MTRx - Memory Technology Registers
  */
 #define MTR_DIMMS_PRESENT(mtr)          ((mtr) & (0x1 << 8))
@@ -287,22 +287,6 @@
 #define MTR_DIMM_COLS(mtr)              ((mtr) & 0x3)
 #define MTR_DIMM_COLS_ADDR_BITS(mtr)    (MTR_DIMM_COLS(mtr) + 10)
 
-#ifdef CONFIG_EDAC_DEBUG
-static char *numrow_toString[] = {
-        "8,192 - 13 rows",
-        "16,384 - 14 rows",
-        "32,768 - 15 rows",
-        "reserved"
-};
-
-static char *numcol_toString[] = {
-        "1,024 - 10 columns",
-        "2,048 - 11 columns",
-        "4,096 - 12 columns",
-        "reserved"
-};
-#endif
-
 /* enables the report of miscellaneous messages as CE errors - default off */
 static int misc_messages;
 
@@ -344,7 +328,13 @@ struct i5000_pvt {
         struct pci_dev *branch_1;       /* 22.0 */
 
         u16 tolm;               /* top of low memory */
-        u64 ambase;             /* AMB BAR */
+        union {
+                u64 ambase;             /* AMB BAR */
+                struct {
+                        u32 ambase_bottom;
+                        u32 ambase_top;
+                } u __packed;
+        };
 
         u16 mir0, mir1, mir2;
 
@@ -494,10 +484,9 @@ static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
         ras = NREC_RAS(info->nrecmemb);
         cas = NREC_CAS(info->nrecmemb);
 
-        debugf0("\t\tCSROW= %d  Channel= %d "
-                "(DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
-                rank, channel, bank,
-                rdwr ? "Write" : "Read", ras, cas);
+        edac_dbg(0, "\t\tCSROW= %d  Channel= %d (DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
+                 rank, channel, bank,
+                 rdwr ? "Write" : "Read", ras, cas);
 
         /* Only 1 bit will be on */
         switch (allErrors) {
@@ -536,10 +525,10 @@ static void i5000_process_fatal_error_info(struct mem_ctl_info *mci,
                  bank, ras, cas, allErrors, specific);
 
         /* Call the helper to output message */
-        edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 0, 0, 0,
+        edac_mc_handle_error(HW_EVENT_ERR_FATAL, mci, 1, 0, 0, 0,
                              channel >> 1, channel & 1, rank,
                              rdwr ? "Write error" : "Read error",
-                             msg, NULL);
+                             msg);
 }
 
 /*
@@ -574,7 +563,7 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
         /* ONLY ONE of the possible error bits will be set, as per the docs */
         ue_errors = allErrors & FERR_NF_UNCORRECTABLE;
         if (ue_errors) {
-                debugf0("\tUncorrected bits= 0x%x\n", ue_errors);
+                edac_dbg(0, "\tUncorrected bits= 0x%x\n", ue_errors);
 
                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 
@@ -590,11 +579,9 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
                 ras = NREC_RAS(info->nrecmemb);
                 cas = NREC_CAS(info->nrecmemb);
 
-                debugf0
-                        ("\t\tCSROW= %d  Channels= %d,%d  (Branch= %d "
-                        "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
-                        rank, channel, channel + 1, branch >> 1, bank,
-                        rdwr ? "Write" : "Read", ras, cas);
+                edac_dbg(0, "\t\tCSROW= %d  Channels= %d,%d  (Branch= %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
+                         rank, channel, channel + 1, branch >> 1, bank,
+                         rdwr ? "Write" : "Read", ras, cas);
 
                 switch (ue_errors) {
                 case FERR_NF_M12ERR:
@@ -637,16 +624,16 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
                          rank, bank, ras, cas, ue_errors, specific);
 
                 /* Call the helper to output message */
-                edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 0, 0, 0,
+                edac_mc_handle_error(HW_EVENT_ERR_UNCORRECTED, mci, 1, 0, 0, 0,
                                 channel >> 1, -1, rank,
                                 rdwr ? "Write error" : "Read error",
-                                msg, NULL);
+                                msg);
         }
 
         /* Check correctable errors */
         ce_errors = allErrors & FERR_NF_CORRECTABLE;
         if (ce_errors) {
-                debugf0("\tCorrected bits= 0x%x\n", ce_errors);
+                edac_dbg(0, "\tCorrected bits= 0x%x\n", ce_errors);
 
                 branch = EXTRACT_FBDCHAN_INDX(info->ferr_nf_fbd);
 
@@ -664,10 +651,9 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
                 ras = REC_RAS(info->recmemb);
                 cas = REC_CAS(info->recmemb);
 
-                debugf0("\t\tCSROW= %d Channel= %d  (Branch %d "
-                        "DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
-                        rank, channel, branch >> 1, bank,
-                        rdwr ? "Write" : "Read", ras, cas);
+                edac_dbg(0, "\t\tCSROW= %d Channel= %d  (Branch %d DRAM Bank= %d rdwr= %s ras= %d cas= %d)\n",
+                         rank, channel, branch >> 1, bank,
+                         rdwr ? "Write" : "Read", ras, cas);
 
                 switch (ce_errors) {
                 case FERR_NF_M17ERR:
@@ -692,10 +678,10 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
                          specific);
 
                 /* Call the helper to output message */
-                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
+                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
                                 channel >> 1, channel % 2, rank,
                                 rdwr ? "Write error" : "Read error",
-                                msg, NULL);
+                                msg);
         }
 
         if (!misc_messages)
@@ -738,9 +724,9 @@ static void i5000_process_nonfatal_error_info(struct mem_ctl_info *mci,
                          "Err=%#x (%s)", misc_errors, specific);
 
                 /* Call the helper to output message */
-                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 0, 0, 0,
+                edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, 1, 0, 0, 0,
                                 branch >> 1, -1, -1,
-                                "Misc error", msg, NULL);
+                                "Misc error", msg);
         }
 }
 
@@ -779,7 +765,7 @@ static void i5000_clear_error(struct mem_ctl_info *mci)
 static void i5000_check_error(struct mem_ctl_info *mci)
 {
         struct i5000_error_info info;
-        debugf4("MC%d: %s: %s()\n", mci->mc_idx, __FILE__, __func__);
+        edac_dbg(4, "MC%d\n", mci->mc_idx);
         i5000_get_error_info(mci, &info);
         i5000_process_error_info(mci, &info, 1);
 }
@@ -850,15 +836,16 @@ static int i5000_get_devices(struct mem_ctl_info *mci, int dev_idx)
 
         pvt->fsb_error_regs = pdev;
 
-        debugf1("System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
-                pci_name(pvt->system_address),
-                pvt->system_address->vendor, pvt->system_address->device);
-        debugf1("Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
-                pci_name(pvt->branchmap_werrors),
-                pvt->branchmap_werrors->vendor, pvt->branchmap_werrors->device);
-        debugf1("FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
-                pci_name(pvt->fsb_error_regs),
-                pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
+        edac_dbg(1, "System Address, processor bus- PCI Bus ID: %s  %x:%x\n",
+                 pci_name(pvt->system_address),
+                 pvt->system_address->vendor, pvt->system_address->device);
+        edac_dbg(1, "Branchmap, control and errors - PCI Bus ID: %s  %x:%x\n",
+                 pci_name(pvt->branchmap_werrors),
+                 pvt->branchmap_werrors->vendor,
+                 pvt->branchmap_werrors->device);
+        edac_dbg(1, "FSB Error Regs - PCI Bus ID: %s  %x:%x\n",
+                 pci_name(pvt->fsb_error_regs),
+                 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
 
         pdev = NULL;
         pdev = pci_get_device(PCI_VENDOR_ID_INTEL,
@@ -981,16 +968,25 @@ static void decode_mtr(int slot_row, u16 mtr)
 
         ans = MTR_DIMMS_PRESENT(mtr);
 
-        debugf2("\tMTR%d=0x%x:  DIMMs are %s\n", slot_row, mtr,
-                ans ? "Present" : "NOT Present");
+        edac_dbg(2, "\tMTR%d=0x%x:  DIMMs are %sPresent\n",
+                 slot_row, mtr, ans ? "" : "NOT ");
         if (!ans)
                 return;
 
-        debugf2("\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
-        debugf2("\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
-        debugf2("\t\tNUMRANK: %s\n", MTR_DIMM_RANK(mtr) ? "double" : "single");
-        debugf2("\t\tNUMROW: %s\n", numrow_toString[MTR_DIMM_ROWS(mtr)]);
-        debugf2("\t\tNUMCOL: %s\n", numcol_toString[MTR_DIMM_COLS(mtr)]);
+        edac_dbg(2, "\t\tWIDTH: x%d\n", MTR_DRAM_WIDTH(mtr));
+        edac_dbg(2, "\t\tNUMBANK: %d bank(s)\n", MTR_DRAM_BANKS(mtr));
+        edac_dbg(2, "\t\tNUMRANK: %s\n",
+                 MTR_DIMM_RANK(mtr) ? "double" : "single");
+        edac_dbg(2, "\t\tNUMROW: %s\n",
+                 MTR_DIMM_ROWS(mtr) == 0 ? "8,192 - 13 rows" :
+                 MTR_DIMM_ROWS(mtr) == 1 ? "16,384 - 14 rows" :
+                 MTR_DIMM_ROWS(mtr) == 2 ? "32,768 - 15 rows" :
+                 "reserved");
+        edac_dbg(2, "\t\tNUMCOL: %s\n",
+                 MTR_DIMM_COLS(mtr) == 0 ? "1,024 - 10 columns" :
+                 MTR_DIMM_COLS(mtr) == 1 ? "2,048 - 11 columns" :
+                 MTR_DIMM_COLS(mtr) == 2 ? "4,096 - 12 columns" :
+                 "reserved");
 }
 
 static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
@@ -1061,7 +1057,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
                                 "--------------------------------");
                         p += n;
                         space -= n;
-                        debugf2("%s\n", mem_buffer);
+                        edac_dbg(2, "%s\n", mem_buffer);
                         p = mem_buffer;
                         space = PAGE_SIZE;
                 }
@@ -1082,7 +1078,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
                 }
                 p += n;
                 space -= n;
-                debugf2("%s\n", mem_buffer);
+                edac_dbg(2, "%s\n", mem_buffer);
                 p = mem_buffer;
                 space = PAGE_SIZE;
         }
@@ -1092,7 +1088,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
                 "--------------------------------");
         p += n;
         space -= n;
-        debugf2("%s\n", mem_buffer);
+        edac_dbg(2, "%s\n", mem_buffer);
         p = mem_buffer;
         space = PAGE_SIZE;
 
@@ -1105,7 +1101,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
                 p += n;
                 space -= n;
         }
-        debugf2("%s\n", mem_buffer);
+        edac_dbg(2, "%s\n", mem_buffer);
         p = mem_buffer;
         space = PAGE_SIZE;
 
@@ -1118,7 +1114,7 @@ static void calculate_dimm_size(struct i5000_pvt *pvt)
         }
 
         /* output the last message and free buffer */
-        debugf2("%s\n", mem_buffer);
+        edac_dbg(2, "%s\n", mem_buffer);
         kfree(mem_buffer);
 }
 
@@ -1141,24 +1137,25 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
         pvt = mci->pvt_info;
 
         pci_read_config_dword(pvt->system_address, AMBASE,
-                        (u32 *) & pvt->ambase);
+                        &pvt->u.ambase_bottom);
         pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
-                        ((u32 *) & pvt->ambase) + sizeof(u32));
+                        &pvt->u.ambase_top);
 
         maxdimmperch = pvt->maxdimmperch;
         maxch = pvt->maxch;
 
-        debugf2("AMBASE= 0x%lx  MAXCH= %d  MAX-DIMM-Per-CH= %d\n",
-                (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
+        edac_dbg(2, "AMBASE= 0x%lx  MAXCH= %d  MAX-DIMM-Per-CH= %d\n",
+                 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
 
         /* Get the Branch Map regs */
         pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
         pvt->tolm >>= 12;
-        debugf2("\nTOLM (number of 256M regions) =%u (0x%x)\n", pvt->tolm,
-                pvt->tolm);
+        edac_dbg(2, "TOLM (number of 256M regions) =%u (0x%x)\n",
+                 pvt->tolm, pvt->tolm);
 
         actual_tolm = pvt->tolm << 28;
-        debugf2("Actual TOLM byte addr=%u (0x%x)\n", actual_tolm, actual_tolm);
+        edac_dbg(2, "Actual TOLM byte addr=%u (0x%x)\n",
+                 actual_tolm, actual_tolm);
 
         pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
         pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
@@ -1168,15 +1165,18 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
         limit = (pvt->mir0 >> 4) & 0x0FFF;
         way0 = pvt->mir0 & 0x1;
         way1 = pvt->mir0 & 0x2;
-        debugf2("MIR0: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
+        edac_dbg(2, "MIR0: limit= 0x%x  WAY1= %u  WAY0= %x\n",
+                 limit, way1, way0);
         limit = (pvt->mir1 >> 4) & 0x0FFF;
         way0 = pvt->mir1 & 0x1;
         way1 = pvt->mir1 & 0x2;
-        debugf2("MIR1: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
+        edac_dbg(2, "MIR1: limit= 0x%x  WAY1= %u  WAY0= %x\n",
+                 limit, way1, way0);
         limit = (pvt->mir2 >> 4) & 0x0FFF;
         way0 = pvt->mir2 & 0x1;
         way1 = pvt->mir2 & 0x2;
-        debugf2("MIR2: limit= 0x%x  WAY1= %u  WAY0= %x\n", limit, way1, way0);
+        edac_dbg(2, "MIR2: limit= 0x%x  WAY1= %u  WAY0= %x\n",
+                 limit, way1, way0);
 
         /* Get the MTR[0-3] regs */
         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
@@ -1185,31 +1185,31 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
                 pci_read_config_word(pvt->branch_0, where,
                                 &pvt->b0_mtr[slot_row]);
 
-                debugf2("MTR%d where=0x%x B0 value=0x%x\n", slot_row, where,
-                        pvt->b0_mtr[slot_row]);
+                edac_dbg(2, "MTR%d where=0x%x B0 value=0x%x\n",
+                         slot_row, where, pvt->b0_mtr[slot_row]);
 
                 if (pvt->maxch >= CHANNELS_PER_BRANCH) {
                         pci_read_config_word(pvt->branch_1, where,
                                         &pvt->b1_mtr[slot_row]);
-                        debugf2("MTR%d where=0x%x B1 value=0x%x\n", slot_row,
-                                where, pvt->b1_mtr[slot_row]);
+                        edac_dbg(2, "MTR%d where=0x%x B1 value=0x%x\n",
+                                 slot_row, where, pvt->b1_mtr[slot_row]);
                 } else {
                         pvt->b1_mtr[slot_row] = 0;
                 }
         }
 
         /* Read and dump branch 0's MTRs */
-        debugf2("\nMemory Technology Registers:\n");
-        debugf2("   Branch 0:\n");
+        edac_dbg(2, "Memory Technology Registers:\n");
+        edac_dbg(2, "   Branch 0:\n");
         for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
                 decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
         }
         pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
                         &pvt->b0_ambpresent0);
-        debugf2("\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
+        edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
         pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
                         &pvt->b0_ambpresent1);
-        debugf2("\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
+        edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
 
         /* Only if we have 2 branchs (4 channels) */
         if (pvt->maxch < CHANNELS_PER_BRANCH) {
@@ -1217,18 +1217,18 @@ static void i5000_get_mc_regs(struct mem_ctl_info *mci)
                 pvt->b1_ambpresent1 = 0;
         } else {
                 /* Read and dump  branch 1's MTRs */
-                debugf2("   Branch 1:\n");
+                edac_dbg(2, "   Branch 1:\n");
                 for (slot_row = 0; slot_row < NUM_MTRS; slot_row++) {
                         decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
                 }
                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
                                 &pvt->b1_ambpresent0);
-                debugf2("\t\tAMB-Branch 1-present0 0x%x:\n",
-                        pvt->b1_ambpresent0);
+                edac_dbg(2, "\t\tAMB-Branch 1-present0 0x%x:\n",
+                         pvt->b1_ambpresent0);
                 pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
                                 &pvt->b1_ambpresent1);
-                debugf2("\t\tAMB-Branch 1-present1 0x%x:\n",
-                        pvt->b1_ambpresent1);
+                edac_dbg(2, "\t\tAMB-Branch 1-present1 0x%x:\n",
+                         pvt->b1_ambpresent1);
         }
 
         /* Go and determine the size of each DIMM and place in an
@@ -1363,10 +1363,9 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
         int num_channels;
         int num_dimms_per_channel;
 
-        debugf0("MC: %s: %s(), pdev bus %u dev=0x%x fn=0x%x\n",
-                __FILE__, __func__,
-                pdev->bus->number,
-                PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
+        edac_dbg(0, "MC: pdev bus %u dev=0x%x fn=0x%x\n",
+                 pdev->bus->number,
+                 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));
 
         /* We only are looking for func 0 of the set */
         if (PCI_FUNC(pdev->devfn) != 0)
@@ -1388,8 +1387,8 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
         i5000_get_dimm_and_channel_counts(pdev, &num_dimms_per_channel,
                                         &num_channels);
 
-        debugf0("MC: %s(): Number of Branches=2 Channels= %d  DIMMS= %d\n",
-                __func__, num_channels, num_dimms_per_channel);
+        edac_dbg(0, "MC: Number of Branches=2 Channels= %d  DIMMS= %d\n",
+                 num_channels, num_dimms_per_channel);
 
         /* allocate a new MC control structure */
 
@@ -1406,10 +1405,9 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
         if (mci == NULL)
                 return -ENOMEM;
 
-        kobject_get(&mci->edac_mci_kobj);
-        debugf0("MC: %s: %s(): mci = %p\n", __FILE__, __func__, mci);
+        edac_dbg(0, "MC: mci = %p\n", mci);
 
-        mci->dev = &pdev->dev;  /* record ptr  to the generic device */
+        mci->pdev = &pdev->dev; /* record ptr  to the generic device */
 
         pvt = mci->pvt_info;
         pvt->system_address = pdev;     /* Record this device in our private */
@@ -1439,19 +1437,16 @@ static int i5000_probe1(struct pci_dev *pdev, int dev_idx)
         /* initialize the MC control structure 'csrows' table
          * with the mapping and control information */
         if (i5000_init_csrows(mci)) {
-                debugf0("MC: Setting mci->edac_cap to EDAC_FLAG_NONE\n"
-                        "    because i5000_init_csrows() returned nonzero "
-                        "value\n");
+                edac_dbg(0, "MC: Setting mci->edac_cap to EDAC_FLAG_NONE because i5000_init_csrows() returned nonzero value\n");
                 mci->edac_cap = EDAC_FLAG_NONE; /* no csrows found */
         } else {
-                debugf1("MC: Enable error reporting now\n");
+                edac_dbg(1, "MC: Enable error reporting now\n");
                 i5000_enable_error_reporting(mci);
         }
 
         /* add this new MC control structure to EDAC's list of MCs */
         if (edac_mc_add_mc(mci)) {
-                debugf0("MC: %s: %s(): failed edac_mc_add_mc()\n",
-                        __FILE__, __func__);
+                edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
                 /* FIXME: perhaps some code should go here that disables error
                  * reporting if we just enabled it
                  */
@@ -1479,7 +1474,6 @@ fail1:
         i5000_put_devices(mci);
 
 fail0:
-        kobject_put(&mci->edac_mci_kobj);
         edac_mc_free(mci);
         return -ENODEV;
 }
@@ -1496,7 +1490,7 @@ static int __devinit i5000_init_one(struct pci_dev *pdev,
 {
         int rc;
 
-        debugf0("MC: %s: %s()\n", __FILE__, __func__);
+        edac_dbg(0, "MC:\n");
 
         /* wake up device */
         rc = pci_enable_device(pdev);
@@ -1515,7 +1509,7 @@ static void __devexit i5000_remove_one(struct pci_dev *pdev)
 {
         struct mem_ctl_info *mci;
 
-        debugf0("%s: %s()\n", __FILE__, __func__);
+        edac_dbg(0, "\n");
 
         if (i5000_pci)
                 edac_pci_release_generic_ctl(i5000_pci);
@@ -1525,7 +1519,6 @@ static void __devexit i5000_remove_one(struct pci_dev *pdev)
 
         /* retrieve references to resources, and free those resources */
         i5000_put_devices(mci);
-        kobject_put(&mci->edac_mci_kobj);
         edac_mc_free(mci);
 }
 
@@ -1562,7 +1555,7 @@ static int __init i5000_init(void)
 {
         int pci_rc;
 
-        debugf2("MC: %s: %s()\n", __FILE__, __func__);
+        edac_dbg(2, "MC:\n");
 
        /* Ensure that the OPSTATE is set correctly for POLL or NMI */
        opstate_init();
@@ -1578,7 +1571,7 @@ static int __init i5000_init(void)
  */
 static void __exit i5000_exit(void)
 {
-        debugf2("MC: %s: %s()\n", __FILE__, __func__);
+        edac_dbg(2, "MC:\n");
         pci_unregister_driver(&i5000_driver);
 }