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path: root/drivers/crypto/ccree/cc_cipher.c
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Diffstat (limited to 'drivers/crypto/ccree/cc_cipher.c')
-rw-r--r--drivers/crypto/ccree/cc_cipher.c42
1 files changed, 22 insertions, 20 deletions
diff --git a/drivers/crypto/ccree/cc_cipher.c b/drivers/crypto/ccree/cc_cipher.c
index 8acedbafbcb3..4c7231d24631 100644
--- a/drivers/crypto/ccree/cc_cipher.c
+++ b/drivers/crypto/ccree/cc_cipher.c
@@ -546,6 +546,19 @@ static void cc_setup_state_desc(struct crypto_tfm *tfm,
546 } 546 }
547} 547}
548 548
549static int cc_out_flow_mode(struct cc_cipher_ctx *ctx_p)
550{
551 switch (ctx_p->flow_mode) {
552 case S_DIN_to_AES:
553 return DIN_AES_DOUT;
554 case S_DIN_to_DES:
555 return DIN_DES_DOUT;
556 case S_DIN_to_SM4:
557 return DIN_SM4_DOUT;
558 default:
559 return ctx_p->flow_mode;
560 }
561}
549 562
550static void cc_setup_key_desc(struct crypto_tfm *tfm, 563static void cc_setup_key_desc(struct crypto_tfm *tfm,
551 struct cipher_req_ctx *req_ctx, 564 struct cipher_req_ctx *req_ctx,
@@ -577,12 +590,15 @@ static void cc_setup_key_desc(struct crypto_tfm *tfm,
577 case DRV_CIPHER_ECB: 590 case DRV_CIPHER_ECB:
578 /* Load key */ 591 /* Load key */
579 hw_desc_init(&desc[*seq_size]); 592 hw_desc_init(&desc[*seq_size]);
593 set_cipher_mode(&desc[*seq_size], cipher_mode);
594 set_cipher_config0(&desc[*seq_size], direction);
595
580 if (cc_key_type(tfm) == CC_POLICY_PROTECTED_KEY) { 596 if (cc_key_type(tfm) == CC_POLICY_PROTECTED_KEY) {
581 set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.alg, 597 /* We use the AES key size coding for all CPP algs */
582 cipher_mode, ctx_p->cpp.slot); 598 set_key_size_aes(&desc[*seq_size], key_len);
599 set_cpp_crypto_key(&desc[*seq_size], ctx_p->cpp.slot);
600 flow_mode = cc_out_flow_mode(ctx_p);
583 } else { 601 } else {
584 set_cipher_mode(&desc[*seq_size], cipher_mode);
585 set_cipher_config0(&desc[*seq_size], direction);
586 if (flow_mode == S_DIN_to_AES) { 602 if (flow_mode == S_DIN_to_AES) {
587 if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) { 603 if (cc_key_type(tfm) == CC_HW_PROTECTED_KEY) {
588 set_hw_crypto_key(&desc[*seq_size], 604 set_hw_crypto_key(&desc[*seq_size],
@@ -606,9 +622,9 @@ static void cc_setup_key_desc(struct crypto_tfm *tfm,
606 key_dma_addr, key_len, NS_BIT); 622 key_dma_addr, key_len, NS_BIT);
607 set_key_size_des(&desc[*seq_size], key_len); 623 set_key_size_des(&desc[*seq_size], key_len);
608 } 624 }
609 set_flow_mode(&desc[*seq_size], flow_mode);
610 set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0); 625 set_setup_mode(&desc[*seq_size], SETUP_LOAD_KEY0);
611 } 626 }
627 set_flow_mode(&desc[*seq_size], flow_mode);
612 (*seq_size)++; 628 (*seq_size)++;
613 break; 629 break;
614 case DRV_CIPHER_XTS: 630 case DRV_CIPHER_XTS:
@@ -670,22 +686,8 @@ static void cc_setup_flow_desc(struct crypto_tfm *tfm,
670{ 686{
671 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm); 687 struct cc_cipher_ctx *ctx_p = crypto_tfm_ctx(tfm);
672 struct device *dev = drvdata_to_dev(ctx_p->drvdata); 688 struct device *dev = drvdata_to_dev(ctx_p->drvdata);
673 unsigned int flow_mode = ctx_p->flow_mode; 689 unsigned int flow_mode = cc_out_flow_mode(ctx_p);
674 690
675 switch (ctx_p->flow_mode) {
676 case S_DIN_to_AES:
677 flow_mode = DIN_AES_DOUT;
678 break;
679 case S_DIN_to_DES:
680 flow_mode = DIN_DES_DOUT;
681 break;
682 case S_DIN_to_SM4:
683 flow_mode = DIN_SM4_DOUT;
684 break;
685 default:
686 dev_err(dev, "invalid flow mode, flow_mode = %d\n", flow_mode);
687 return;
688 }
689 /* Process */ 691 /* Process */
690 if (req_ctx->dma_buf_type == CC_DMA_BUF_DLLI) { 692 if (req_ctx->dma_buf_type == CC_DMA_BUF_DLLI) {
691 dev_dbg(dev, " data params addr %pad length 0x%X\n", 693 dev_dbg(dev, " data params addr %pad length 0x%X\n",