12 files changed, 457 insertions, 36 deletions

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 6a78073c3808..7fdcbd3f4da5 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -22,6 +22,24 @@ config DW_APB_TIMER_OF
 config ARMADA_370_XP_TIMER
         bool
 
+config SUNXI_TIMER
+        bool
+
+config CLKSRC_NOMADIK_MTU
+        bool
+        depends on (ARCH_NOMADIK || ARCH_U8500)
+        select CLKSRC_MMIO
+        help
+          Support for Multi Timer Unit. MTU provides access
+          to multiple interrupt generating programmable
+          32-bit free running decrementing counters.
+
+config CLKSRC_NOMADIK_MTU_SCHED_CLOCK
+        bool
+        depends on CLKSRC_NOMADIK_MTU
+        help
+          Use the Multi Timer Unit as the sched_clock.
+
 config CLKSRC_DBX500_PRCMU
         bool "Clocksource PRCMU Timer"
         depends on UX500_SOC_DB8500
@@ -31,7 +49,7 @@ config CLKSRC_DBX500_PRCMU
 
 config CLKSRC_DBX500_PRCMU_SCHED_CLOCK
         bool "Clocksource PRCMU Timer sched_clock"
-        depends on (CLKSRC_DBX500_PRCMU && !NOMADIK_MTU_SCHED_CLOCK)
+        depends on (CLKSRC_DBX500_PRCMU && !CLKSRC_NOMADIK_MTU_SCHED_CLOCK)
         default y
         help
           Use the always on PRCMU Timer as sched_clock
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 603be366f762..f93453d01673 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -11,8 +11,10 @@ obj-$(CONFIG_CLKBLD_I8253)	+= i8253.o
 obj-$(CONFIG_CLKSRC_MMIO)       += mmio.o
 obj-$(CONFIG_DW_APB_TIMER)      += dw_apb_timer.o
 obj-$(CONFIG_DW_APB_TIMER_OF)   += dw_apb_timer_of.o
+obj-$(CONFIG_CLKSRC_NOMADIK_MTU)        += nomadik-mtu.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)       += time-armada-370-xp.o
 obj-$(CONFIG_ARCH_BCM2835)      += bcm2835_timer.o
+obj-$(CONFIG_SUNXI_TIMER)       += sunxi_timer.o
 
 obj-$(CONFIG_CLKSRC_ARM_GENERIC)        += arm_generic.o
diff --git a/drivers/clocksource/acpi_pm.c b/drivers/clocksource/acpi_pm.c
index 6b5cf02c35c8..6efe4d1ab3aa 100644
--- a/drivers/clocksource/acpi_pm.c
+++ b/drivers/clocksource/acpi_pm.c
@@ -73,7 +73,7 @@ static struct clocksource clocksource_acpi_pm = {
 
 
 #ifdef CONFIG_PCI
-static int __devinitdata acpi_pm_good;
+static int acpi_pm_good;
 static int __init acpi_pm_good_setup(char *__str)
 {
         acpi_pm_good = 1;
@@ -102,7 +102,7 @@ static inline void acpi_pm_need_workaround(void)
  * incorrect when read). As a result, the ACPI free running count up
  * timer specification is violated due to erroneous reads.
  */
-static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
+static void acpi_pm_check_blacklist(struct pci_dev *dev)
 {
         if (acpi_pm_good)
                 return;
@@ -120,7 +120,7 @@ static void __devinit acpi_pm_check_blacklist(struct pci_dev *dev)
 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3,
                         acpi_pm_check_blacklist);
 
-static void __devinit acpi_pm_check_graylist(struct pci_dev *dev)
+static void acpi_pm_check_graylist(struct pci_dev *dev)
 {
         if (acpi_pm_good)
                 return;
@@ -233,16 +233,15 @@ fs_initcall(init_acpi_pm_clocksource);
  */
 static int __init parse_pmtmr(char *arg)
 {
-        unsigned long base;
+        unsigned int base;
+        int ret;
 
-        if (strict_strtoul(arg, 16, &base))
-                return -EINVAL;
-#ifdef CONFIG_X86_64
-        if (base > UINT_MAX)
-                return -ERANGE;
-#endif
-        printk(KERN_INFO "PMTMR IOPort override: 0x%04x -> 0x%04lx\n",
-               pmtmr_ioport, base);
+        ret = kstrtouint(arg, 16, &base);
+        if (ret)
+                return ret;
+
+        pr_info("PMTMR IOPort override: 0x%04x -> 0x%04x\n", pmtmr_ioport,
+                base);
         pmtmr_ioport = base;
 
         return 1;
diff --git a/drivers/clocksource/arm_generic.c b/drivers/clocksource/arm_generic.c
index c4d9f9566c64..8ae1a61523ff 100644
--- a/drivers/clocksource/arm_generic.c
+++ b/drivers/clocksource/arm_generic.c
@@ -109,7 +109,7 @@ static void __cpuinit arch_timer_setup(struct clock_event_device *clk)
 
         enable_percpu_irq(clk->irq, 0);
 
-        /* Ensure the physical counter is visible to userspace for the vDSO. */
+        /* Ensure the virtual counter is visible to userspace for the vDSO. */
         arch_counter_enable_user_access();
 }
 
@@ -127,7 +127,7 @@ static void __init arch_timer_calibrate(void)
 
         /* Cache the sched_clock multiplier to save a divide in the hot path. */
 
-        sched_clock_mult = NSEC_PER_SEC / arch_timer_rate;
+        sched_clock_mult = DIV_ROUND_CLOSEST(NSEC_PER_SEC, arch_timer_rate);
 
         pr_info("Architected local timer running at %u.%02uMHz.\n",
                  arch_timer_rate / 1000000, (arch_timer_rate / 10000) % 100);
@@ -221,10 +221,10 @@ int __init arm_generic_timer_init(void)
         clocksource_register_hz(&clocksource_counter, arch_timer_rate);
 
         /* Calibrate the delay loop directly */
-        lpj_fine = arch_timer_rate / HZ;
+        lpj_fine = DIV_ROUND_CLOSEST(arch_timer_rate, HZ);
 
         /* Immediately configure the timer on the boot CPU */
-        arch_timer_setup(per_cpu_ptr(&arch_timer_evt, smp_processor_id()));
+        arch_timer_setup(this_cpu_ptr(&arch_timer_evt));
 
         register_cpu_notifier(&arch_timer_cpu_nb);
 
diff --git a/drivers/clocksource/em_sti.c b/drivers/clocksource/em_sti.c
index 372051d1bba8..e6a553cb73e8 100644
--- a/drivers/clocksource/em_sti.c
+++ b/drivers/clocksource/em_sti.c
@@ -311,7 +311,7 @@ static void em_sti_register_clockevent(struct em_sti_priv *p)
         clockevents_config_and_register(ced, 1, 2, 0xffffffff);
 }
 
-static int __devinit em_sti_probe(struct platform_device *pdev)
+static int em_sti_probe(struct platform_device *pdev)
 {
         struct em_sti_priv *p;
         struct resource *res;
@@ -379,12 +379,12 @@ err0:
         return ret;
 }
 
-static int __devexit em_sti_remove(struct platform_device *pdev)
+static int em_sti_remove(struct platform_device *pdev)
 {
         return -EBUSY; /* cannot unregister clockevent and clocksource */
 }
 
-static const struct of_device_id em_sti_dt_ids[] __devinitconst = {
+static const struct of_device_id em_sti_dt_ids[] = {
         { .compatible = "renesas,em-sti", },
         {},
 };
@@ -392,7 +392,7 @@ MODULE_DEVICE_TABLE(of, em_sti_dt_ids);
 
 static struct platform_driver em_sti_device_driver = {
         .probe          = em_sti_probe,
-        .remove         = __devexit_p(em_sti_remove),
+        .remove         = em_sti_remove,
         .driver         = {
                 .name   = "em_sti",
                 .of_match_table = em_sti_dt_ids,
diff --git a/drivers/clocksource/i8253.c b/drivers/clocksource/i8253.c
index e7cab2da910f..14ee3efcc404 100644
--- a/drivers/clocksource/i8253.c
+++ b/drivers/clocksource/i8253.c
@@ -35,7 +35,7 @@ static cycle_t i8253_read(struct clocksource *cs)
 
         raw_spin_lock_irqsave(&i8253_lock, flags);
         /*
-         * Although our caller may have the read side of xtime_lock,
+         * Although our caller may have the read side of jiffies_lock,
          * this is now a seqlock, and we are cheating in this routine
          * by having side effects on state that we cannot undo if
          * there is a collision on the seqlock and our caller has to
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
new file mode 100644
index 000000000000..8914c3c1c88b
--- /dev/null
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -0,0 +1,230 @@
+/*
+ * Copyright (C) 2008 STMicroelectronics
+ * Copyright (C) 2010 Alessandro Rubini
+ * Copyright (C) 2010 Linus Walleij for ST-Ericsson
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2, as
+ * published by the Free Software Foundation.
+ */
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/clk.h>
+#include <linux/jiffies.h>
+#include <linux/err.h>
+#include <linux/platform_data/clocksource-nomadik-mtu.h>
+#include <asm/mach/time.h>
+#include <asm/sched_clock.h>
+
+/*
+ * The MTU device hosts four different counters, with 4 set of
+ * registers. These are register names.
+ */
+
+#define MTU_IMSC        0x00    /* Interrupt mask set/clear */
+#define MTU_RIS         0x04    /* Raw interrupt status */
+#define MTU_MIS         0x08    /* Masked interrupt status */
+#define MTU_ICR         0x0C    /* Interrupt clear register */
+
+/* per-timer registers take 0..3 as argument */
+#define MTU_LR(x)       (0x10 + 0x10 * (x) + 0x00)      /* Load value */
+#define MTU_VAL(x)      (0x10 + 0x10 * (x) + 0x04)      /* Current value */
+#define MTU_CR(x)       (0x10 + 0x10 * (x) + 0x08)      /* Control reg */
+#define MTU_BGLR(x)     (0x10 + 0x10 * (x) + 0x0c)      /* At next overflow */
+
+/* bits for the control register */
+#define MTU_CRn_ENA             0x80
+#define MTU_CRn_PERIODIC        0x40    /* if 0 = free-running */
+#define MTU_CRn_PRESCALE_MASK   0x0c
+#define MTU_CRn_PRESCALE_1              0x00
+#define MTU_CRn_PRESCALE_16             0x04
+#define MTU_CRn_PRESCALE_256            0x08
+#define MTU_CRn_32BITS          0x02
+#define MTU_CRn_ONESHOT         0x01    /* if 0 = wraps reloading from BGLR*/
+
+/* Other registers are usual amba/primecell registers, currently not used */
+#define MTU_ITCR        0xff0
+#define MTU_ITOP        0xff4
+
+#define MTU_PERIPH_ID0  0xfe0
+#define MTU_PERIPH_ID1  0xfe4
+#define MTU_PERIPH_ID2  0xfe8
+#define MTU_PERIPH_ID3  0xfeC
+
+#define MTU_PCELL0      0xff0
+#define MTU_PCELL1      0xff4
+#define MTU_PCELL2      0xff8
+#define MTU_PCELL3      0xffC
+
+static void __iomem *mtu_base;
+static bool clkevt_periodic;
+static u32 clk_prescale;
+static u32 nmdk_cycle;          /* write-once */
+
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
+/*
+ * Override the global weak sched_clock symbol with this
+ * local implementation which uses the clocksource to get some
+ * better resolution when scheduling the kernel.
+ */
+static u32 notrace nomadik_read_sched_clock(void)
+{
+        if (unlikely(!mtu_base))
+                return 0;
+
+        return -readl(mtu_base + MTU_VAL(0));
+}
+#endif
+
+/* Clockevent device: use one-shot mode */
+static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
+{
+        writel(1 << 1, mtu_base + MTU_IMSC);
+        writel(evt, mtu_base + MTU_LR(1));
+        /* Load highest value, enable device, enable interrupts */
+        writel(MTU_CRn_ONESHOT | clk_prescale |
+               MTU_CRn_32BITS | MTU_CRn_ENA,
+               mtu_base + MTU_CR(1));
+
+        return 0;
+}
+
+void nmdk_clkevt_reset(void)
+{
+        if (clkevt_periodic) {
+                /* Timer: configure load and background-load, and fire it up */
+                writel(nmdk_cycle, mtu_base + MTU_LR(1));
+                writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
+
+                writel(MTU_CRn_PERIODIC | clk_prescale |
+                       MTU_CRn_32BITS | MTU_CRn_ENA,
+                       mtu_base + MTU_CR(1));
+                writel(1 << 1, mtu_base + MTU_IMSC);
+        } else {
+                /* Generate an interrupt to start the clockevent again */
+                (void) nmdk_clkevt_next(nmdk_cycle, NULL);
+        }
+}
+
+static void nmdk_clkevt_mode(enum clock_event_mode mode,
+                             struct clock_event_device *dev)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                clkevt_periodic = true;
+                nmdk_clkevt_reset();
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                clkevt_periodic = false;
+                break;
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_UNUSED:
+                writel(0, mtu_base + MTU_IMSC);
+                /* disable timer */
+                writel(0, mtu_base + MTU_CR(1));
+                /* load some high default value */
+                writel(0xffffffff, mtu_base + MTU_LR(1));
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                break;
+        }
+}
+
+static struct clock_event_device nmdk_clkevt = {
+        .name           = "mtu_1",
+        .features       = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
+        .rating         = 200,
+        .set_mode       = nmdk_clkevt_mode,
+        .set_next_event = nmdk_clkevt_next,
+};
+
+/*
+ * IRQ Handler for timer 1 of the MTU block.
+ */
+static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evdev = dev_id;
+
+        writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
+        evdev->event_handler(evdev);
+        return IRQ_HANDLED;
+}
+
+static struct irqaction nmdk_timer_irq = {
+        .name           = "Nomadik Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER,
+        .handler        = nmdk_timer_interrupt,
+        .dev_id         = &nmdk_clkevt,
+};
+
+void nmdk_clksrc_reset(void)
+{
+        /* Disable */
+        writel(0, mtu_base + MTU_CR(0));
+
+        /* ClockSource: configure load and background-load, and fire it up */
+        writel(nmdk_cycle, mtu_base + MTU_LR(0));
+        writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
+
+        writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
+               mtu_base + MTU_CR(0));
+}
+
+void __init nmdk_timer_init(void __iomem *base, int irq)
+{
+        unsigned long rate;
+        struct clk *clk0, *pclk0;
+
+        mtu_base = base;
+
+        pclk0 = clk_get_sys("mtu0", "apb_pclk");
+        BUG_ON(IS_ERR(pclk0));
+        BUG_ON(clk_prepare(pclk0) < 0);
+        BUG_ON(clk_enable(pclk0) < 0);
+
+        clk0 = clk_get_sys("mtu0", NULL);
+        BUG_ON(IS_ERR(clk0));
+        BUG_ON(clk_prepare(clk0) < 0);
+        BUG_ON(clk_enable(clk0) < 0);
+
+        /*
+         * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
+         * for ux500.
+         * Use a divide-by-16 counter if the tick rate is more than 32MHz.
+         * At 32 MHz, the timer (with 32 bit counter) can be programmed
+         * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
+         * with 16 gives too low timer resolution.
+         */
+        rate = clk_get_rate(clk0);
+        if (rate > 32000000) {
+                rate /= 16;
+                clk_prescale = MTU_CRn_PRESCALE_16;
+        } else {
+                clk_prescale = MTU_CRn_PRESCALE_1;
+        }
+
+        /* Cycles for periodic mode */
+        nmdk_cycle = DIV_ROUND_CLOSEST(rate, HZ);
+
+
+        /* Timer 0 is the free running clocksource */
+        nmdk_clksrc_reset();
+
+        if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
+                        rate, 200, 32, clocksource_mmio_readl_down))
+                pr_err("timer: failed to initialize clock source %s\n",
+                       "mtu_0");
+
+#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
+        setup_sched_clock(nomadik_read_sched_clock, 32, rate);
+#endif
+
+        /* Timer 1 is used for events, register irq and clockevents */
+        setup_irq(irq, &nmdk_timer_irq);
+        nmdk_clkevt.cpumask = cpumask_of(0);
+        clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU);
+}
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index a5f7829f2799..488c14cc8dbf 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -726,7 +726,7 @@ err0:
         return ret;
 }
 
-static int __devinit sh_cmt_probe(struct platform_device *pdev)
+static int sh_cmt_probe(struct platform_device *pdev)
 {
         struct sh_cmt_priv *p = platform_get_drvdata(pdev);
         struct sh_timer_config *cfg = pdev->dev.platform_data;
@@ -767,14 +767,14 @@ static int __devinit sh_cmt_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int __devexit sh_cmt_remove(struct platform_device *pdev)
+static int sh_cmt_remove(struct platform_device *pdev)
 {
         return -EBUSY; /* cannot unregister clockevent and clocksource */
 }
 
 static struct platform_driver sh_cmt_device_driver = {
         .probe          = sh_cmt_probe,
-        .remove         = __devexit_p(sh_cmt_remove),
+        .remove         = sh_cmt_remove,
         .driver         = {
                 .name   = "sh_cmt",
         }
diff --git a/drivers/clocksource/sh_mtu2.c b/drivers/clocksource/sh_mtu2.c
index c5eea858054a..83943e27cfac 100644
--- a/drivers/clocksource/sh_mtu2.c
+++ b/drivers/clocksource/sh_mtu2.c
@@ -321,7 +321,7 @@ static int sh_mtu2_setup(struct sh_mtu2_priv *p, struct platform_device *pdev)
         return ret;
 }
 
-static int __devinit sh_mtu2_probe(struct platform_device *pdev)
+static int sh_mtu2_probe(struct platform_device *pdev)
 {
         struct sh_mtu2_priv *p = platform_get_drvdata(pdev);
         struct sh_timer_config *cfg = pdev->dev.platform_data;
@@ -362,14 +362,14 @@ static int __devinit sh_mtu2_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int __devexit sh_mtu2_remove(struct platform_device *pdev)
+static int sh_mtu2_remove(struct platform_device *pdev)
 {
         return -EBUSY; /* cannot unregister clockevent */
 }
 
 static struct platform_driver sh_mtu2_device_driver = {
         .probe          = sh_mtu2_probe,
-        .remove         = __devexit_p(sh_mtu2_remove),
+        .remove         = sh_mtu2_remove,
         .driver         = {
                 .name   = "sh_mtu2",
         }
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 0cc4add88279..b4502edce2a1 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -484,7 +484,7 @@ static int sh_tmu_setup(struct sh_tmu_priv *p, struct platform_device *pdev)
         return ret;
 }
 
-static int __devinit sh_tmu_probe(struct platform_device *pdev)
+static int sh_tmu_probe(struct platform_device *pdev)
 {
         struct sh_tmu_priv *p = platform_get_drvdata(pdev);
         struct sh_timer_config *cfg = pdev->dev.platform_data;
@@ -525,14 +525,14 @@ static int __devinit sh_tmu_probe(struct platform_device *pdev)
         return 0;
 }
 
-static int __devexit sh_tmu_remove(struct platform_device *pdev)
+static int sh_tmu_remove(struct platform_device *pdev)
 {
         return -EBUSY; /* cannot unregister clockevent and clocksource */
 }
 
 static struct platform_driver sh_tmu_device_driver = {
         .probe          = sh_tmu_probe,
-        .remove         = __devexit_p(sh_tmu_remove),
+        .remove         = sh_tmu_remove,
         .driver         = {
                 .name   = "sh_tmu",
         }
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sunxi_timer.c
new file mode 100644
index 000000000000..3cd1bd3d7aee
--- /dev/null
+++ b/drivers/clocksource/sunxi_timer.c
@@ -0,0 +1,171 @@
+/*
+ * Allwinner A1X SoCs timer handling.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqreturn.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sunxi_timer.h>
+#include <linux/clk/sunxi.h>
+
+#define TIMER_CTL_REG           0x00
+#define TIMER_CTL_ENABLE                (1 << 0)
+#define TIMER_IRQ_ST_REG        0x04
+#define TIMER0_CTL_REG          0x10
+#define TIMER0_CTL_ENABLE               (1 << 0)
+#define TIMER0_CTL_AUTORELOAD           (1 << 1)
+#define TIMER0_CTL_ONESHOT              (1 << 7)
+#define TIMER0_INTVAL_REG       0x14
+#define TIMER0_CNTVAL_REG       0x18
+
+#define TIMER_SCAL              16
+
+static void __iomem *timer_base;
+
+static void sunxi_clkevt_mode(enum clock_event_mode mode,
+                              struct clock_event_device *clk)
+{
+        u32 u = readl(timer_base + TIMER0_CTL_REG);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                u &= ~(TIMER0_CTL_ONESHOT);
+                writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
+                break;
+
+        case CLOCK_EVT_MODE_ONESHOT:
+                writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        default:
+                writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
+                break;
+        }
+}
+
+static int sunxi_clkevt_next_event(unsigned long evt,
+                                   struct clock_event_device *unused)
+{
+        u32 u = readl(timer_base + TIMER0_CTL_REG);
+        writel(evt, timer_base + TIMER0_CNTVAL_REG);
+        writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
+               timer_base + TIMER0_CTL_REG);
+
+        return 0;
+}
+
+static struct clock_event_device sunxi_clockevent = {
+        .name = "sunxi_tick",
+        .shift = 32,
+        .rating = 300,
+        .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+        .set_mode = sunxi_clkevt_mode,
+        .set_next_event = sunxi_clkevt_next_event,
+};
+
+
+static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = (struct clock_event_device *)dev_id;
+
+        writel(0x1, timer_base + TIMER_IRQ_ST_REG);
+        evt->event_handler(evt);
+
+        return IRQ_HANDLED;
+}
+
+static struct irqaction sunxi_timer_irq = {
+        .name = "sunxi_timer0",
+        .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler = sunxi_timer_interrupt,
+        .dev_id = &sunxi_clockevent,
+};
+
+static struct of_device_id sunxi_timer_dt_ids[] = {
+        { .compatible = "allwinner,sunxi-timer" },
+        { }
+};
+
+static void __init sunxi_timer_init(void)
+{
+        struct device_node *node;
+        unsigned long rate = 0;
+        struct clk *clk;
+        int ret, irq;
+        u32 val;
+
+        node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
+        if (!node)
+                panic("No sunxi timer node");
+
+        timer_base = of_iomap(node, 0);
+        if (!timer_base)
+                panic("Can't map registers");
+
+        irq = irq_of_parse_and_map(node, 0);
+        if (irq <= 0)
+                panic("Can't parse IRQ");
+
+        sunxi_init_clocks();
+
+        clk = of_clk_get(node, 0);
+        if (IS_ERR(clk))
+                panic("Can't get timer clock");
+
+        rate = clk_get_rate(clk);
+
+        writel(rate / (TIMER_SCAL * HZ),
+               timer_base + TIMER0_INTVAL_REG);
+
+        /* set clock source to HOSC, 16 pre-division */
+        val = readl(timer_base + TIMER0_CTL_REG);
+        val &= ~(0x07 << 4);
+        val &= ~(0x03 << 2);
+        val |= (4 << 4) | (1 << 2);
+        writel(val, timer_base + TIMER0_CTL_REG);
+
+        /* set mode to auto reload */
+        val = readl(timer_base + TIMER0_CTL_REG);
+        writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
+
+        ret = setup_irq(irq, &sunxi_timer_irq);
+        if (ret)
+                pr_warn("failed to setup irq %d\n", irq);
+
+        /* Enable timer0 interrupt */
+        val = readl(timer_base + TIMER_CTL_REG);
+        writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
+
+        sunxi_clockevent.mult = div_sc(rate / TIMER_SCAL,
+                                NSEC_PER_SEC,
+                                sunxi_clockevent.shift);
+        sunxi_clockevent.max_delta_ns = clockevent_delta2ns(0xff,
+                                                            &sunxi_clockevent);
+        sunxi_clockevent.min_delta_ns = clockevent_delta2ns(0x1,
+                                                            &sunxi_clockevent);
+        sunxi_clockevent.cpumask = cpumask_of(0);
+
+        clockevents_register_device(&sunxi_clockevent);
+}
+
+struct sys_timer sunxi_timer = {
+        .init = sunxi_timer_init,
+};
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index 4674f94957cd..a4605fd7e303 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -18,6 +18,7 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/kernel.h>
+#include <linux/clk.h>
 #include <linux/timer.h>
 #include <linux/clockchips.h>
 #include <linux/interrupt.h>
@@ -167,7 +168,6 @@ void __init armada_370_xp_timer_init(void)
         u32 u;
         struct device_node *np;
         unsigned int timer_clk;
-        int ret;
         np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
         timer_base = of_iomap(np, 0);
         WARN_ON(!timer_base);
@@ -179,13 +179,14 @@ void __init armada_370_xp_timer_init(void)
                        timer_base + TIMER_CTRL_OFF);
                 timer_clk = 25000000;
         } else {
-                u32 clk = 0;
-                ret = of_property_read_u32(np, "clock-frequency", &clk);
-                WARN_ON(!clk || ret < 0);
+                unsigned long rate = 0;
+                struct clk *clk = of_clk_get(np, 0);
+                WARN_ON(IS_ERR(clk));
+                rate =  clk_get_rate(clk);
                 u = readl(timer_base + TIMER_CTRL_OFF);
                 writel(u & ~(TIMER0_25MHZ | TIMER1_25MHZ),
                        timer_base + TIMER_CTRL_OFF);
-                timer_clk = clk / TIMER_DIVIDER;
+                timer_clk = rate / TIMER_DIVIDER;
         }
 
         /* We use timer 0 as clocksource, and timer 1 for