10 files changed, 841 insertions, 63 deletions

diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index cd6950fd8caf..52e9329e3c51 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -140,3 +140,51 @@ config VF_PIT_TIMER
         bool
         help
           Support for Period Interrupt Timer on Freescale Vybrid Family SoCs.
+
+config SYS_SUPPORTS_SH_CMT
+        bool
+
+config SYS_SUPPORTS_SH_MTU2
+        bool
+
+config SYS_SUPPORTS_SH_TMU
+        bool
+
+config SYS_SUPPORTS_EM_STI
+        bool
+
+config SH_TIMER_CMT
+        bool "Renesas CMT timer driver" if COMPILE_TEST
+        depends on GENERIC_CLOCKEVENTS
+        default SYS_SUPPORTS_SH_CMT
+        help
+          This enables build of a clocksource and clockevent driver for
+          the Compare Match Timer (CMT) hardware available in 16/32/48-bit
+          variants on a wide range of Mobile and Automotive SoCs from Renesas.
+
+config SH_TIMER_MTU2
+        bool "Renesas MTU2 timer driver" if COMPILE_TEST
+        depends on GENERIC_CLOCKEVENTS
+        default SYS_SUPPORTS_SH_MTU2
+        help
+          This enables build of a clockevent driver for the Multi-Function
+          Timer Pulse Unit 2 (TMU2) hardware available on SoCs from Renesas.
+          This hardware comes with 16 bit-timer registers.
+
+config SH_TIMER_TMU
+        bool "Renesas TMU timer driver" if COMPILE_TEST
+        depends on GENERIC_CLOCKEVENTS
+        default SYS_SUPPORTS_SH_TMU
+        help
+          This enables build of a clocksource and clockevent driver for
+          the 32-bit Timer Unit (TMU) hardware available on a wide range
+          SoCs from Renesas.
+
+config EM_TIMER_STI
+        bool "Renesas STI timer driver" if COMPILE_TEST
+        depends on GENERIC_CLOCKEVENTS
+        default SYS_SUPPORTS_EM_STI
+        help
+          This enables build of a clocksource and clockevent driver for
+          the 48-bit System Timer (STI) hardware available on a SoCs
+          such as EMEV2 from former NEC Electronics.
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index c7ca50a9c232..aed3488d9426 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_ARCH_MARCO)	+= timer-marco.o
 obj-$(CONFIG_ARCH_MOXART)       += moxart_timer.o
 obj-$(CONFIG_ARCH_MXS)          += mxs_timer.o
 obj-$(CONFIG_ARCH_PRIMA2)       += timer-prima2.o
+obj-$(CONFIG_ARCH_U300)         += timer-u300.o
 obj-$(CONFIG_SUN4I_TIMER)       += sun4i_timer.o
 obj-$(CONFIG_SUN5I_HSTIMER)     += timer-sun5i.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
@@ -37,3 +38,4 @@ obj-$(CONFIG_ARM_ARCH_TIMER)		+= arm_arch_timer.o
 obj-$(CONFIG_ARM_GLOBAL_TIMER)          += arm_global_timer.o
 obj-$(CONFIG_CLKSRC_METAG_GENERIC)      += metag_generic.o
 obj-$(CONFIG_ARCH_HAS_TICK_BROADCAST)   += dummy_timer.o
+obj-$(CONFIG_ARCH_KEYSTONE)             += timer-keystone.o
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 95fb944e15ee..57e823c44d2a 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -277,6 +277,7 @@ static void __arch_timer_setup(unsigned type,
                         clk->set_next_event = arch_timer_set_next_event_phys;
                 }
         } else {
+                clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
                 clk->name = "arch_mem_timer";
                 clk->rating = 400;
                 clk->cpumask = cpu_all_mask;
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index 63f176de0d02..49fbe2847c84 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -16,6 +16,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/interrupt.h>
 #include <linux/clockchips.h>
 #include <linux/of_address.h>
@@ -52,6 +53,8 @@
 #define TTC_CNT_CNTRL_DISABLE_MASK      0x1
 
 #define TTC_CLK_CNTRL_CSRC_MASK         (1 << 5)        /* clock source */
+#define TTC_CLK_CNTRL_PSV_MASK          0x1e
+#define TTC_CLK_CNTRL_PSV_SHIFT         1
 
 /*
  * Setup the timers to use pre-scaling, using a fixed value for now that will
@@ -63,6 +66,8 @@
 #define CLK_CNTRL_PRESCALE_EN   1
 #define CNT_CNTRL_RESET         (1 << 4)
 
+#define MAX_F_ERR 50
+
 /**
  * struct ttc_timer - This definition defines local timer structure
  *
@@ -82,6 +87,8 @@ struct ttc_timer {
                 container_of(x, struct ttc_timer, clk_rate_change_nb)
 
 struct ttc_timer_clocksource {
+        u32                     scale_clk_ctrl_reg_old;
+        u32                     scale_clk_ctrl_reg_new;
         struct ttc_timer        ttc;
         struct clocksource      cs;
 };
@@ -229,32 +236,89 @@ static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
                         struct ttc_timer_clocksource, ttc);
 
         switch (event) {
-        case POST_RATE_CHANGE:
+        case PRE_RATE_CHANGE:
+        {
+                u32 psv;
+                unsigned long factor, rate_low, rate_high;
+
+                if (ndata->new_rate > ndata->old_rate) {
+                        factor = DIV_ROUND_CLOSEST(ndata->new_rate,
+                                        ndata->old_rate);
+                        rate_low = ndata->old_rate;
+                        rate_high = ndata->new_rate;
+                } else {
+                        factor = DIV_ROUND_CLOSEST(ndata->old_rate,
+                                        ndata->new_rate);
+                        rate_low = ndata->new_rate;
+                        rate_high = ndata->old_rate;
+                }
+
+                if (!is_power_of_2(factor))
+                                return NOTIFY_BAD;
+
+                if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
+                        return NOTIFY_BAD;
+
+                factor = __ilog2_u32(factor);
+
                 /*
-                 * Do whatever is necessary to maintain a proper time base
-                 *
-                 * I cannot find a way to adjust the currently used clocksource
-                 * to the new frequency. __clocksource_updatefreq_hz() sounds
-                 * good, but does not work. Not sure what's that missing.
-                 *
-                 * This approach works, but triggers two clocksource switches.
-                 * The first after unregister to clocksource jiffies. And
-                 * another one after the register to the newly registered timer.
-                 *
-                 * Alternatively we could 'waste' another HW timer to ping pong
-                 * between clock sources. That would also use one register and
-                 * one unregister call, but only trigger one clocksource switch
-                 * for the cost of another HW timer used by the OS.
+                 * store timer clock ctrl register so we can restore it in case
+                 * of an abort.
                  */
-                clocksource_unregister(&ttccs->cs);
-                clocksource_register_hz(&ttccs->cs,
-                                ndata->new_rate / PRESCALE);
-                /* fall through */
-        case PRE_RATE_CHANGE:
+                ttccs->scale_clk_ctrl_reg_old =
+                        __raw_readl(ttccs->ttc.base_addr +
+                                        TTC_CLK_CNTRL_OFFSET);
+
+                psv = (ttccs->scale_clk_ctrl_reg_old &
+                                TTC_CLK_CNTRL_PSV_MASK) >>
+                                TTC_CLK_CNTRL_PSV_SHIFT;
+                if (ndata->new_rate < ndata->old_rate)
+                        psv -= factor;
+                else
+                        psv += factor;
+
+                /* prescaler within legal range? */
+                if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
+                        return NOTIFY_BAD;
+
+                ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
+                        ~TTC_CLK_CNTRL_PSV_MASK;
+                ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
+
+
+                /* scale down: adjust divider in post-change notification */
+                if (ndata->new_rate < ndata->old_rate)
+                        return NOTIFY_DONE;
+
+                /* scale up: adjust divider now - before frequency change */
+                __raw_writel(ttccs->scale_clk_ctrl_reg_new,
+                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
+                break;
+        }
+        case POST_RATE_CHANGE:
+                /* scale up: pre-change notification did the adjustment */
+                if (ndata->new_rate > ndata->old_rate)
+                        return NOTIFY_OK;
+
+                /* scale down: adjust divider now - after frequency change */
+                __raw_writel(ttccs->scale_clk_ctrl_reg_new,
+                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
+                break;
+
         case ABORT_RATE_CHANGE:
+                /* we have to undo the adjustment in case we scale up */
+                if (ndata->new_rate < ndata->old_rate)
+                        return NOTIFY_OK;
+
+                /* restore original register value */
+                __raw_writel(ttccs->scale_clk_ctrl_reg_old,
+                                ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
+                /* fall through */
         default:
                 return NOTIFY_DONE;
         }
+
+        return NOTIFY_DONE;
 }
 
 static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
@@ -321,25 +385,12 @@ static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
 
         switch (event) {
         case POST_RATE_CHANGE:
-        {
-                unsigned long flags;
-
-                /*
-                 * clockevents_update_freq should be called with IRQ disabled on
-                 * the CPU the timer provides events for. The timer we use is
-                 * common to both CPUs, not sure if we need to run on both
-                 * cores.
-                 */
-                local_irq_save(flags);
-                clockevents_update_freq(&ttcce->ce,
-                                ndata->new_rate / PRESCALE);
-                local_irq_restore(flags);
-
                 /* update cached frequency */
                 ttc->freq = ndata->new_rate;
 
+                clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
+
                 /* fall through */
-        }
         case PRE_RATE_CHANGE:
         case ABORT_RATE_CHANGE:
         default:
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 48f76bc05da0..c2e390efbdca 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -410,7 +410,7 @@ static int exynos4_local_timer_setup(struct clock_event_device *evt)
         mevt = container_of(evt, struct mct_clock_event_device, evt);
 
         mevt->base = EXYNOS4_MCT_L_BASE(cpu);
-        sprintf(mevt->name, "mct_tick%d", cpu);
+        snprintf(mevt->name, sizeof(mevt->name), "mct_tick%d", cpu);
 
         evt->name = mevt->name;
         evt->cpumask = cpumask_of(cpu);
diff --git a/drivers/clocksource/sun4i_timer.c b/drivers/clocksource/sun4i_timer.c
index bf497afba9ad..efb17c3ee120 100644
--- a/drivers/clocksource/sun4i_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -196,5 +196,5 @@ static void __init sun4i_timer_init(struct device_node *node)
         clockevents_config_and_register(&sun4i_clockevent, rate,
                                         TIMER_SYNC_TICKS, 0xffffffff);
 }
-CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
+CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-a10-timer",
                        sun4i_timer_init);
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c
index ee8691b89944..0451e62fac7a 100644
--- a/drivers/clocksource/time-armada-370-xp.c
+++ b/drivers/clocksource/time-armada-370-xp.c
@@ -85,12 +85,6 @@ static u32 ticks_per_jiffy;
 
 static struct clock_event_device __percpu *armada_370_xp_evt;
 
-static void timer_ctrl_clrset(u32 clr, u32 set)
-{
-        writel((readl(timer_base + TIMER_CTRL_OFF) & ~clr) | set,
-                timer_base + TIMER_CTRL_OFF);
-}
-
 static void local_timer_ctrl_clrset(u32 clr, u32 set)
 {
         writel((readl(local_base + TIMER_CTRL_OFF) & ~clr) | set,
@@ -245,7 +239,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
                 clr = TIMER0_25MHZ;
                 enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT);
         }
-        timer_ctrl_clrset(clr, set);
+        atomic_io_modify(timer_base + TIMER_CTRL_OFF, clr | set, set);
         local_timer_ctrl_clrset(clr, set);
 
         /*
@@ -263,7 +257,9 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np)
         writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
         writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
 
-        timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask);
+        atomic_io_modify(timer_base + TIMER_CTRL_OFF,
+                TIMER0_RELOAD_EN | enable_mask,
+                TIMER0_RELOAD_EN | enable_mask);
 
         /*
          * Set scale and timer for sched_clock.
diff --git a/drivers/clocksource/time-orion.c b/drivers/clocksource/time-orion.c
index 20066222f3f2..0b3ce0399c51 100644
--- a/drivers/clocksource/time-orion.c
+++ b/drivers/clocksource/time-orion.c
@@ -35,20 +35,6 @@
 #define ORION_ONESHOT_MAX       0xfffffffe
 
 static void __iomem *timer_base;
-static DEFINE_SPINLOCK(timer_ctrl_lock);
-
-/*
- * Thread-safe access to TIMER_CTRL register
- * (shared with watchdog timer)
- */
-void orion_timer_ctrl_clrset(u32 clr, u32 set)
-{
-        spin_lock(&timer_ctrl_lock);
-        writel((readl(timer_base + TIMER_CTRL) & ~clr) | set,
-                timer_base + TIMER_CTRL);
-        spin_unlock(&timer_ctrl_lock);
-}
-EXPORT_SYMBOL(orion_timer_ctrl_clrset);
 
 /*
  * Free-running clocksource handling.
@@ -68,7 +54,8 @@ static int orion_clkevt_next_event(unsigned long delta,
 {
         /* setup and enable one-shot timer */
         writel(delta, timer_base + TIMER1_VAL);
-        orion_timer_ctrl_clrset(TIMER1_RELOAD_EN, TIMER1_EN);
+        atomic_io_modify(timer_base + TIMER_CTRL,
+                TIMER1_RELOAD_EN | TIMER1_EN, TIMER1_EN);
 
         return 0;
 }
@@ -80,10 +67,13 @@ static void orion_clkevt_mode(enum clock_event_mode mode,
                 /* setup and enable periodic timer at 1/HZ intervals */
                 writel(ticks_per_jiffy - 1, timer_base + TIMER1_RELOAD);
                 writel(ticks_per_jiffy - 1, timer_base + TIMER1_VAL);
-                orion_timer_ctrl_clrset(0, TIMER1_RELOAD_EN | TIMER1_EN);
+                atomic_io_modify(timer_base + TIMER_CTRL,
+                        TIMER1_RELOAD_EN | TIMER1_EN,
+                        TIMER1_RELOAD_EN | TIMER1_EN);
         } else {
                 /* disable timer */
-                orion_timer_ctrl_clrset(TIMER1_RELOAD_EN | TIMER1_EN, 0);
+                atomic_io_modify(timer_base + TIMER_CTRL,
+                        TIMER1_RELOAD_EN | TIMER1_EN, 0);
         }
 }
 
@@ -131,7 +121,9 @@ static void __init orion_timer_init(struct device_node *np)
         /* setup timer0 as free-running clocksource */
         writel(~0, timer_base + TIMER0_VAL);
         writel(~0, timer_base + TIMER0_RELOAD);
-        orion_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | TIMER0_EN);
+        atomic_io_modify(timer_base + TIMER_CTRL,
+                TIMER0_RELOAD_EN | TIMER0_EN,
+                TIMER0_RELOAD_EN | TIMER0_EN);
         clocksource_mmio_init(timer_base + TIMER0_VAL, "orion_clocksource",
                               clk_get_rate(clk), 300, 32,
                               clocksource_mmio_readl_down);
diff --git a/drivers/clocksource/timer-keystone.c b/drivers/clocksource/timer-keystone.c
new file mode 100644
index 000000000000..0250354f7e55
--- /dev/null
+++ b/drivers/clocksource/timer-keystone.c
@@ -0,0 +1,241 @@
+/*
+ * Keystone broadcast clock-event
+ *
+ * Copyright 2013 Texas Instruments, Inc.
+ *
+ * Author: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/interrupt.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#define TIMER_NAME                      "timer-keystone"
+
+/* Timer register offsets */
+#define TIM12                           0x10
+#define TIM34                           0x14
+#define PRD12                           0x18
+#define PRD34                           0x1c
+#define TCR                             0x20
+#define TGCR                            0x24
+#define INTCTLSTAT                      0x44
+
+/* Timer register bitfields */
+#define TCR_ENAMODE_MASK                0xC0
+#define TCR_ENAMODE_ONESHOT_MASK        0x40
+#define TCR_ENAMODE_PERIODIC_MASK       0x80
+
+#define TGCR_TIM_UNRESET_MASK           0x03
+#define INTCTLSTAT_ENINT_MASK           0x01
+
+/**
+ * struct keystone_timer: holds timer's data
+ * @base: timer memory base address
+ * @hz_period: cycles per HZ period
+ * @event_dev: event device based on timer
+ */
+static struct keystone_timer {
+        void __iomem *base;
+        unsigned long hz_period;
+        struct clock_event_device event_dev;
+} timer;
+
+static inline u32 keystone_timer_readl(unsigned long rg)
+{
+        return readl_relaxed(timer.base + rg);
+}
+
+static inline void keystone_timer_writel(u32 val, unsigned long rg)
+{
+        writel_relaxed(val, timer.base + rg);
+}
+
+/**
+ * keystone_timer_barrier: write memory barrier
+ * use explicit barrier to avoid using readl/writel non relaxed function
+ * variants, because in our case non relaxed variants hide the true places
+ * where barrier is needed.
+ */
+static inline void keystone_timer_barrier(void)
+{
+        __iowmb();
+}
+
+/**
+ * keystone_timer_config: configures timer to work in oneshot/periodic modes.
+ * @ mode: mode to configure
+ * @ period: cycles number to configure for
+ */
+static int keystone_timer_config(u64 period, enum clock_event_mode mode)
+{
+        u32 tcr;
+        u32 off;
+
+        tcr = keystone_timer_readl(TCR);
+        off = tcr & ~(TCR_ENAMODE_MASK);
+
+        /* set enable mode */
+        switch (mode) {
+        case CLOCK_EVT_MODE_ONESHOT:
+                tcr |= TCR_ENAMODE_ONESHOT_MASK;
+                break;
+        case CLOCK_EVT_MODE_PERIODIC:
+                tcr |= TCR_ENAMODE_PERIODIC_MASK;
+                break;
+        default:
+                return -1;
+        }
+
+        /* disable timer */
+        keystone_timer_writel(off, TCR);
+        /* here we have to be sure the timer has been disabled */
+        keystone_timer_barrier();
+
+        /* reset counter to zero, set new period */
+        keystone_timer_writel(0, TIM12);
+        keystone_timer_writel(0, TIM34);
+        keystone_timer_writel(period & 0xffffffff, PRD12);
+        keystone_timer_writel(period >> 32, PRD34);
+
+        /*
+         * enable timer
+         * here we have to be sure that CNTLO, CNTHI, PRDLO, PRDHI registers
+         * have been written.
+         */
+        keystone_timer_barrier();
+        keystone_timer_writel(tcr, TCR);
+        return 0;
+}
+
+static void keystone_timer_disable(void)
+{
+        u32 tcr;
+
+        tcr = keystone_timer_readl(TCR);
+
+        /* disable timer */
+        tcr &= ~(TCR_ENAMODE_MASK);
+        keystone_timer_writel(tcr, TCR);
+}
+
+static irqreturn_t keystone_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = dev_id;
+
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+
+static int keystone_set_next_event(unsigned long cycles,
+                                  struct clock_event_device *evt)
+{
+        return keystone_timer_config(cycles, evt->mode);
+}
+
+static void keystone_set_mode(enum clock_event_mode mode,
+                             struct clock_event_device *evt)
+{
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                keystone_timer_config(timer.hz_period, CLOCK_EVT_MODE_PERIODIC);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+        case CLOCK_EVT_MODE_ONESHOT:
+                keystone_timer_disable();
+                break;
+        default:
+                break;
+        }
+}
+
+static void __init keystone_timer_init(struct device_node *np)
+{
+        struct clock_event_device *event_dev = &timer.event_dev;
+        unsigned long rate;
+        struct clk *clk;
+        int irq, error;
+
+        irq  = irq_of_parse_and_map(np, 0);
+        if (irq == NO_IRQ) {
+                pr_err("%s: failed to map interrupts\n", __func__);
+                return;
+        }
+
+        timer.base = of_iomap(np, 0);
+        if (!timer.base) {
+                pr_err("%s: failed to map registers\n", __func__);
+                return;
+        }
+
+        clk = of_clk_get(np, 0);
+        if (IS_ERR(clk)) {
+                pr_err("%s: failed to get clock\n", __func__);
+                iounmap(timer.base);
+                return;
+        }
+
+        error = clk_prepare_enable(clk);
+        if (error) {
+                pr_err("%s: failed to enable clock\n", __func__);
+                goto err;
+        }
+
+        rate = clk_get_rate(clk);
+
+        /* disable, use internal clock source */
+        keystone_timer_writel(0, TCR);
+        /* here we have to be sure the timer has been disabled */
+        keystone_timer_barrier();
+
+        /* reset timer as 64-bit, no pre-scaler, plus features are disabled */
+        keystone_timer_writel(0, TGCR);
+
+        /* unreset timer */
+        keystone_timer_writel(TGCR_TIM_UNRESET_MASK, TGCR);
+
+        /* init counter to zero */
+        keystone_timer_writel(0, TIM12);
+        keystone_timer_writel(0, TIM34);
+
+        timer.hz_period = DIV_ROUND_UP(rate, HZ);
+
+        /* enable timer interrupts */
+        keystone_timer_writel(INTCTLSTAT_ENINT_MASK, INTCTLSTAT);
+
+        error = request_irq(irq, keystone_timer_interrupt, IRQF_TIMER,
+                            TIMER_NAME, event_dev);
+        if (error) {
+                pr_err("%s: failed to setup irq\n", __func__);
+                goto err;
+        }
+
+        /* setup clockevent */
+        event_dev->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
+        event_dev->set_next_event = keystone_set_next_event;
+        event_dev->set_mode = keystone_set_mode;
+        event_dev->cpumask = cpu_all_mask;
+        event_dev->owner = THIS_MODULE;
+        event_dev->name = TIMER_NAME;
+        event_dev->irq = irq;
+
+        clockevents_config_and_register(event_dev, rate, 1, ULONG_MAX);
+
+        pr_info("keystone timer clock @%lu Hz\n", rate);
+        return;
+err:
+        clk_put(clk);
+        iounmap(timer.base);
+}
+
+CLOCKSOURCE_OF_DECLARE(keystone_timer, "ti,keystone-timer",
+                                        keystone_timer_init);
diff --git a/drivers/clocksource/timer-u300.c b/drivers/clocksource/timer-u300.c
new file mode 100644
index 000000000000..e63d469661fd
--- /dev/null
+++ b/drivers/clocksource/timer-u300.c
@@ -0,0 +1,447 @@
+/*
+ * Copyright (C) 2007-2009 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Timer COH 901 328, runs the OS timer interrupt.
+ * Author: Linus Walleij <linus.walleij@stericsson.com>
+ */
+#include <linux/interrupt.h>
+#include <linux/time.h>
+#include <linux/timex.h>
+#include <linux/clockchips.h>
+#include <linux/clocksource.h>
+#include <linux/types.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/irq.h>
+#include <linux/delay.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/sched_clock.h>
+
+/* Generic stuff */
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+/*
+ * APP side special timer registers
+ * This timer contains four timers which can fire an interrupt each.
+ * OS (operating system) timer @ 32768 Hz
+ * DD (device driver) timer @ 1 kHz
+ * GP1 (general purpose 1) timer @ 1MHz
+ * GP2 (general purpose 2) timer @ 1MHz
+ */
+
+/* Reset OS Timer 32bit (-/W) */
+#define U300_TIMER_APP_ROST                                     (0x0000)
+#define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
+/* Enable OS Timer 32bit (-/W) */
+#define U300_TIMER_APP_EOST                                     (0x0004)
+#define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
+/* Disable OS Timer 32bit (-/W) */
+#define U300_TIMER_APP_DOST                                     (0x0008)
+#define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
+/* OS Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SOSTM                                    (0x000c)
+#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
+/* OS Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_OSTS                                     (0x0010)
+#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
+#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
+#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
+#define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
+#define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
+#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
+#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
+#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
+#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
+/* OS Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_OSTCC                                    (0x0014)
+/* OS Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_OSTTC                                    (0x0018)
+/* OS Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_OSTIE                                    (0x001c)
+#define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
+#define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
+/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_OSTIA                                    (0x0020)
+#define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
+
+/* Reset DD Timer 32bit (-/W) */
+#define U300_TIMER_APP_RDDT                                     (0x0040)
+#define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
+/* Enable DD Timer 32bit (-/W) */
+#define U300_TIMER_APP_EDDT                                     (0x0044)
+#define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
+/* Disable DD Timer 32bit (-/W) */
+#define U300_TIMER_APP_DDDT                                     (0x0048)
+#define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
+/* DD Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SDDTM                                    (0x004c)
+#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
+/* DD Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_DDTS                                     (0x0050)
+#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
+#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
+#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
+#define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
+#define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
+#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
+#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
+#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
+#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
+/* DD Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_DDTCC                                    (0x0054)
+/* DD Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_DDTTC                                    (0x0058)
+/* DD Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_DDTIE                                    (0x005c)
+#define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
+#define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
+/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_DDTIA                                    (0x0060)
+#define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
+
+/* Reset GP1 Timer 32bit (-/W) */
+#define U300_TIMER_APP_RGPT1                                    (0x0080)
+#define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
+/* Enable GP1 Timer 32bit (-/W) */
+#define U300_TIMER_APP_EGPT1                                    (0x0084)
+#define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
+/* Disable GP1 Timer 32bit (-/W) */
+#define U300_TIMER_APP_DGPT1                                    (0x0088)
+#define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
+/* GP1 Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SGPT1M                                   (0x008c)
+#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
+#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
+/* GP1 Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT1S                                    (0x0090)
+#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
+#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
+#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
+#define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
+#define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
+#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
+#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
+#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
+/* GP1 Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT1CC                                   (0x0094)
+/* GP1 Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_GPT1TC                                   (0x0098)
+/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT1IE                                   (0x009c)
+#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
+#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
+/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT1IA                                   (0x00a0)
+#define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
+
+/* Reset GP2 Timer 32bit (-/W) */
+#define U300_TIMER_APP_RGPT2                                    (0x00c0)
+#define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
+/* Enable GP2 Timer 32bit (-/W) */
+#define U300_TIMER_APP_EGPT2                                    (0x00c4)
+#define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
+/* Disable GP2 Timer 32bit (-/W) */
+#define U300_TIMER_APP_DGPT2                                    (0x00c8)
+#define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
+/* GP2 Timer Mode Register 32bit (-/W) */
+#define U300_TIMER_APP_SGPT2M                                   (0x00cc)
+#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
+#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
+/* GP2 Timer Status Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT2S                                    (0x00d0)
+#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
+#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
+#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
+#define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
+#define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
+#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
+#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
+#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
+#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
+/* GP2 Timer Current Count Register 32bit (R/-) */
+#define U300_TIMER_APP_GPT2CC                                   (0x00d4)
+/* GP2 Timer Terminal Count Register 32bit (R/W) */
+#define U300_TIMER_APP_GPT2TC                                   (0x00d8)
+/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT2IE                                   (0x00dc)
+#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
+#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
+/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
+#define U300_TIMER_APP_GPT2IA                                   (0x00e0)
+#define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
+
+/* Clock request control register - all four timers */
+#define U300_TIMER_APP_CRC                                      (0x100)
+#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
+
+static void __iomem *u300_timer_base;
+
+struct u300_clockevent_data {
+        struct clock_event_device cevd;
+        unsigned ticks_per_jiffy;
+};
+
+/*
+ * The u300_set_mode() function is always called first, if we
+ * have oneshot timer active, the oneshot scheduling function
+ * u300_set_next_event() is called immediately after.
+ */
+static void u300_set_mode(enum clock_event_mode mode,
+                          struct clock_event_device *evt)
+{
+        struct u300_clockevent_data *cevdata =
+                container_of(evt, struct u300_clockevent_data, cevd);
+
+        switch (mode) {
+        case CLOCK_EVT_MODE_PERIODIC:
+                /* Disable interrupts on GPT1 */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
+                /* Disable GP1 while we're reprogramming it. */
+                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
+                /*
+                 * Set the periodic mode to a certain number of ticks per
+                 * jiffy.
+                 */
+                writel(cevdata->ticks_per_jiffy,
+                       u300_timer_base + U300_TIMER_APP_GPT1TC);
+                /*
+                 * Set continuous mode, so the timer keeps triggering
+                 * interrupts.
+                 */
+                writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
+                /* Enable timer interrupts */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
+                /* Then enable the OS timer again */
+                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
+                break;
+        case CLOCK_EVT_MODE_ONESHOT:
+                /* Just break; here? */
+                /*
+                 * The actual event will be programmed by the next event hook,
+                 * so we just set a dummy value somewhere at the end of the
+                 * universe here.
+                 */
+                /* Disable interrupts on GPT1 */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
+                /* Disable GP1 while we're reprogramming it. */
+                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
+                /*
+                 * Expire far in the future, u300_set_next_event() will be
+                 * called soon...
+                 */
+                writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
+                /* We run one shot per tick here! */
+                writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
+                       u300_timer_base + U300_TIMER_APP_SGPT1M);
+                /* Enable interrupts for this timer */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
+                /* Enable timer */
+                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
+                       u300_timer_base + U300_TIMER_APP_EGPT1);
+                break;
+        case CLOCK_EVT_MODE_UNUSED:
+        case CLOCK_EVT_MODE_SHUTDOWN:
+                /* Disable interrupts on GP1 */
+                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+                       u300_timer_base + U300_TIMER_APP_GPT1IE);
+                /* Disable GP1 */
+                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+                       u300_timer_base + U300_TIMER_APP_DGPT1);
+                break;
+        case CLOCK_EVT_MODE_RESUME:
+                /* Ignore this call */
+                break;
+        }
+}
+
+/*
+ * The app timer in one shot mode obviously has to be reprogrammed
+ * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
+ * the interrupt disable + timer disable commands with a reset command,
+ * it will fail miserably. Apparently (and I found this the hard way)
+ * the timer is very sensitive to the instruction order, though you don't
+ * get that impression from the data sheet.
+ */
+static int u300_set_next_event(unsigned long cycles,
+                               struct clock_event_device *evt)
+
+{
+        /* Disable interrupts on GPT1 */
+        writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
+        /* Disable GP1 while we're reprogramming it. */
+        writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
+               u300_timer_base + U300_TIMER_APP_DGPT1);
+        /* Reset the General Purpose timer 1. */
+        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
+               u300_timer_base + U300_TIMER_APP_RGPT1);
+        /* IRQ in n * cycles */
+        writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
+        /*
+         * We run one shot per tick here! (This is necessary to reconfigure,
+         * the timer will tilt if you don't!)
+         */
+        writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
+               u300_timer_base + U300_TIMER_APP_SGPT1M);
+        /* Enable timer interrupts */
+        writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
+               u300_timer_base + U300_TIMER_APP_GPT1IE);
+        /* Then enable the OS timer again */
+        writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
+               u300_timer_base + U300_TIMER_APP_EGPT1);
+        return 0;
+}
+
+static struct u300_clockevent_data u300_clockevent_data = {
+        /* Use general purpose timer 1 as clock event */
+        .cevd = {
+                .name           = "GPT1",
+                /* Reasonably fast and accurate clock event */
+                .rating         = 300,
+                .features       = CLOCK_EVT_FEAT_PERIODIC |
+                        CLOCK_EVT_FEAT_ONESHOT,
+                .set_next_event = u300_set_next_event,
+                .set_mode       = u300_set_mode,
+        },
+};
+
+/* Clock event timer interrupt handler */
+static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
+{
+        struct clock_event_device *evt = &u300_clockevent_data.cevd;
+        /* ACK/Clear timer IRQ for the APP GPT1 Timer */
+
+        writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
+                u300_timer_base + U300_TIMER_APP_GPT1IA);
+        evt->event_handler(evt);
+        return IRQ_HANDLED;
+}
+
+static struct irqaction u300_timer_irq = {
+        .name           = "U300 Timer Tick",
+        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
+        .handler        = u300_timer_interrupt,
+};
+
+/*
+ * Override the global weak sched_clock symbol with this
+ * local implementation which uses the clocksource to get some
+ * better resolution when scheduling the kernel. We accept that
+ * this wraps around for now, since it is just a relative time
+ * stamp. (Inspired by OMAP implementation.)
+ */
+
+static u64 notrace u300_read_sched_clock(void)
+{
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
+}
+
+static unsigned long u300_read_current_timer(void)
+{
+        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
+}
+
+static struct delay_timer u300_delay_timer;
+
+/*
+ * This sets up the system timers, clock source and clock event.
+ */
+static void __init u300_timer_init_of(struct device_node *np)
+{
+        unsigned int irq;
+        struct clk *clk;
+        unsigned long rate;
+
+        u300_timer_base = of_iomap(np, 0);
+        if (!u300_timer_base)
+                panic("could not ioremap system timer\n");
+
+        /* Get the IRQ for the GP1 timer */
+        irq = irq_of_parse_and_map(np, 2);
+        if (!irq)
+                panic("no IRQ for system timer\n");
+
+        pr_info("U300 GP1 timer @ base: %p, IRQ: %u\n", u300_timer_base, irq);
+
+        /* Clock the interrupt controller */
+        clk = of_clk_get(np, 0);
+        BUG_ON(IS_ERR(clk));
+        clk_prepare_enable(clk);
+        rate = clk_get_rate(clk);
+
+        u300_clockevent_data.ticks_per_jiffy = DIV_ROUND_CLOSEST(rate, HZ);
+
+        sched_clock_register(u300_read_sched_clock, 32, rate);
+
+        u300_delay_timer.read_current_timer = &u300_read_current_timer;
+        u300_delay_timer.freq = rate;
+        register_current_timer_delay(&u300_delay_timer);
+
+        /*
+         * Disable the "OS" and "DD" timers - these are designed for Symbian!
+         * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
+         */
+        writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
+                u300_timer_base + U300_TIMER_APP_CRC);
+        writel(U300_TIMER_APP_ROST_TIMER_RESET,
+                u300_timer_base + U300_TIMER_APP_ROST);
+        writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
+                u300_timer_base + U300_TIMER_APP_DOST);
+        writel(U300_TIMER_APP_RDDT_TIMER_RESET,
+                u300_timer_base + U300_TIMER_APP_RDDT);
+        writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
+                u300_timer_base + U300_TIMER_APP_DDDT);
+
+        /* Reset the General Purpose timer 1. */
+        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
+                u300_timer_base + U300_TIMER_APP_RGPT1);
+
+        /* Set up the IRQ handler */
+        setup_irq(irq, &u300_timer_irq);
+
+        /* Reset the General Purpose timer 2 */
+        writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
+                u300_timer_base + U300_TIMER_APP_RGPT2);
+        /* Set this timer to run around forever */
+        writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
+        /* Set continuous mode so it wraps around */
+        writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
+               u300_timer_base + U300_TIMER_APP_SGPT2M);
+        /* Disable timer interrupts */
+        writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
+                u300_timer_base + U300_TIMER_APP_GPT2IE);
+        /* Then enable the GP2 timer to use as a free running us counter */
+        writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
+                u300_timer_base + U300_TIMER_APP_EGPT2);
+
+        /* Use general purpose timer 2 as clock source */
+        if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
+                        "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
+                pr_err("timer: failed to initialize U300 clock source\n");
+
+        /* Configure and register the clockevent */
+        clockevents_config_and_register(&u300_clockevent_data.cevd, rate,
+                                        1, 0xffffffff);
+
+        /*
+         * TODO: init and register the rest of the timers too, they can be
+         * used by hrtimers!
+         */
+}
+
+CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
+                       u300_timer_init_of);