diff options
Diffstat (limited to 'drivers/clocksource/time-armada-370-xp.c')
-rw-r--r-- | drivers/clocksource/time-armada-370-xp.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/clocksource/time-armada-370-xp.c b/drivers/clocksource/time-armada-370-xp.c index 4e7f6802e840..ee8691b89944 100644 --- a/drivers/clocksource/time-armada-370-xp.c +++ b/drivers/clocksource/time-armada-370-xp.c | |||
@@ -76,6 +76,7 @@ | |||
76 | static void __iomem *timer_base, *local_base; | 76 | static void __iomem *timer_base, *local_base; |
77 | static unsigned int timer_clk; | 77 | static unsigned int timer_clk; |
78 | static bool timer25Mhz = true; | 78 | static bool timer25Mhz = true; |
79 | static u32 enable_mask; | ||
79 | 80 | ||
80 | /* | 81 | /* |
81 | * Number of timer ticks per jiffy. | 82 | * Number of timer ticks per jiffy. |
@@ -121,8 +122,7 @@ armada_370_xp_clkevt_next_event(unsigned long delta, | |||
121 | /* | 122 | /* |
122 | * Enable the timer. | 123 | * Enable the timer. |
123 | */ | 124 | */ |
124 | local_timer_ctrl_clrset(TIMER0_RELOAD_EN, | 125 | local_timer_ctrl_clrset(TIMER0_RELOAD_EN, enable_mask); |
125 | TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT)); | ||
126 | return 0; | 126 | return 0; |
127 | } | 127 | } |
128 | 128 | ||
@@ -141,9 +141,7 @@ armada_370_xp_clkevt_mode(enum clock_event_mode mode, | |||
141 | /* | 141 | /* |
142 | * Enable timer. | 142 | * Enable timer. |
143 | */ | 143 | */ |
144 | local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | | 144 | local_timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask); |
145 | TIMER0_EN | | ||
146 | TIMER0_DIV(TIMER_DIVIDER_SHIFT)); | ||
147 | } else { | 145 | } else { |
148 | /* | 146 | /* |
149 | * Disable timer. | 147 | * Disable timer. |
@@ -240,10 +238,13 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np) | |||
240 | WARN_ON(!timer_base); | 238 | WARN_ON(!timer_base); |
241 | local_base = of_iomap(np, 1); | 239 | local_base = of_iomap(np, 1); |
242 | 240 | ||
243 | if (timer25Mhz) | 241 | if (timer25Mhz) { |
244 | set = TIMER0_25MHZ; | 242 | set = TIMER0_25MHZ; |
245 | else | 243 | enable_mask = TIMER0_EN; |
244 | } else { | ||
246 | clr = TIMER0_25MHZ; | 245 | clr = TIMER0_25MHZ; |
246 | enable_mask = TIMER0_EN | TIMER0_DIV(TIMER_DIVIDER_SHIFT); | ||
247 | } | ||
247 | timer_ctrl_clrset(clr, set); | 248 | timer_ctrl_clrset(clr, set); |
248 | local_timer_ctrl_clrset(clr, set); | 249 | local_timer_ctrl_clrset(clr, set); |
249 | 250 | ||
@@ -262,8 +263,7 @@ static void __init armada_370_xp_timer_common_init(struct device_node *np) | |||
262 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); | 263 | writel(0xffffffff, timer_base + TIMER0_VAL_OFF); |
263 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); | 264 | writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF); |
264 | 265 | ||
265 | timer_ctrl_clrset(0, TIMER0_EN | TIMER0_RELOAD_EN | | 266 | timer_ctrl_clrset(0, TIMER0_RELOAD_EN | enable_mask); |
266 | TIMER0_DIV(TIMER_DIVIDER_SHIFT)); | ||
267 | 267 | ||
268 | /* | 268 | /* |
269 | * Set scale and timer for sched_clock. | 269 | * Set scale and timer for sched_clock. |