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path: root/drivers/clk/samsung/clk-exynos5420.c
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Diffstat (limited to 'drivers/clk/samsung/clk-exynos5420.c')
-rw-r--r--drivers/clk/samsung/clk-exynos5420.c10
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index bea4a173eef5..a1d731ca8f48 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -504,7 +504,7 @@ static struct samsung_fixed_factor_clock
504 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), 504 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
505}; 505};
506 506
507struct samsung_mux_clock exynos5800_mux_clks[] __initdata = { 507static struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
508 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3), 508 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
509 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3), 509 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
510 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3), 510 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
@@ -553,7 +553,7 @@ struct samsung_mux_clock exynos5800_mux_clks[] __initdata = {
553 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3), 553 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
554}; 554};
555 555
556struct samsung_div_clock exynos5800_div_clks[] __initdata = { 556static struct samsung_div_clock exynos5800_div_clks[] __initdata = {
557 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3), 557 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore", DIV_TOP0, 16, 3),
558 558
559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam", 559 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
@@ -569,14 +569,14 @@ struct samsung_div_clock exynos5800_div_clks[] __initdata = {
569 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6), 569 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
570}; 570};
571 571
572struct samsung_gate_clock exynos5800_gate_clks[] __initdata = { 572static struct samsung_gate_clock exynos5800_gate_clks[] __initdata = {
573 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam", 573 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
574 GATE_BUS_TOP, 24, 0, 0), 574 GATE_BUS_TOP, 24, 0, 0),
575 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler", 575 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
576 GATE_BUS_TOP, 27, 0, 0), 576 GATE_BUS_TOP, 27, 0, 0),
577}; 577};
578 578
579struct samsung_mux_clock exynos5420_mux_clks[] __initdata = { 579static struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
580 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1), 580 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
581 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p, 581 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
582 TOP_SPARE2, 4, 1), 582 TOP_SPARE2, 4, 1),
@@ -606,7 +606,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
606 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1), 606 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
607}; 607};
608 608
609struct samsung_div_clock exynos5420_div_clks[] __initdata = { 609static struct samsung_div_clock exynos5420_div_clks[] __initdata = {
610 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll", 610 DIV(0, "dout_aclk400_wcore", "mout_aclk400_wcore_bpll",
611 DIV_TOP0, 16, 3), 611 DIV_TOP0, 16, 3),
612}; 612};