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path: root/drivers/clk/qcom/gcc-msm8998.c
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Diffstat (limited to 'drivers/clk/qcom/gcc-msm8998.c')
-rw-r--r--drivers/clk/qcom/gcc-msm8998.c61
1 files changed, 56 insertions, 5 deletions
diff --git a/drivers/clk/qcom/gcc-msm8998.c b/drivers/clk/qcom/gcc-msm8998.c
index 1b779396e04f..c240fba794c7 100644
--- a/drivers/clk/qcom/gcc-msm8998.c
+++ b/drivers/clk/qcom/gcc-msm8998.c
@@ -1112,6 +1112,7 @@ static struct clk_rcg2 ufs_axi_clk_src = {
1112 1112
1113static const struct freq_tbl ftbl_usb30_master_clk_src[] = { 1113static const struct freq_tbl ftbl_usb30_master_clk_src[] = {
1114 F(19200000, P_XO, 1, 0, 0), 1114 F(19200000, P_XO, 1, 0, 0),
1115 F(60000000, P_GPLL0_OUT_MAIN, 10, 0, 0),
1115 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0), 1116 F(120000000, P_GPLL0_OUT_MAIN, 5, 0, 0),
1116 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0), 1117 F(150000000, P_GPLL0_OUT_MAIN, 4, 0, 0),
1117 { } 1118 { }
@@ -1189,6 +1190,7 @@ static struct clk_branch gcc_aggre1_ufs_axi_clk = {
1189 "ufs_axi_clk_src", 1190 "ufs_axi_clk_src",
1190 }, 1191 },
1191 .num_parents = 1, 1192 .num_parents = 1,
1193 .flags = CLK_SET_RATE_PARENT,
1192 .ops = &clk_branch2_ops, 1194 .ops = &clk_branch2_ops,
1193 }, 1195 },
1194 }, 1196 },
@@ -1206,6 +1208,7 @@ static struct clk_branch gcc_aggre1_usb3_axi_clk = {
1206 "usb30_master_clk_src", 1208 "usb30_master_clk_src",
1207 }, 1209 },
1208 .num_parents = 1, 1210 .num_parents = 1,
1211 .flags = CLK_SET_RATE_PARENT,
1209 .ops = &clk_branch2_ops, 1212 .ops = &clk_branch2_ops,
1210 }, 1213 },
1211 }, 1214 },
@@ -1288,6 +1291,7 @@ static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {
1288 "blsp1_qup1_i2c_apps_clk_src", 1291 "blsp1_qup1_i2c_apps_clk_src",
1289 }, 1292 },
1290 .num_parents = 1, 1293 .num_parents = 1,
1294 .flags = CLK_SET_RATE_PARENT,
1291 .ops = &clk_branch2_ops, 1295 .ops = &clk_branch2_ops,
1292 }, 1296 },
1293 }, 1297 },
@@ -1305,6 +1309,7 @@ static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {
1305 "blsp1_qup1_spi_apps_clk_src", 1309 "blsp1_qup1_spi_apps_clk_src",
1306 }, 1310 },
1307 .num_parents = 1, 1311 .num_parents = 1,
1312 .flags = CLK_SET_RATE_PARENT,
1308 .ops = &clk_branch2_ops, 1313 .ops = &clk_branch2_ops,
1309 }, 1314 },
1310 }, 1315 },
@@ -1322,6 +1327,7 @@ static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {
1322 "blsp1_qup2_i2c_apps_clk_src", 1327 "blsp1_qup2_i2c_apps_clk_src",
1323 }, 1328 },
1324 .num_parents = 1, 1329 .num_parents = 1,
1330 .flags = CLK_SET_RATE_PARENT,
1325 .ops = &clk_branch2_ops, 1331 .ops = &clk_branch2_ops,
1326 }, 1332 },
1327 }, 1333 },
@@ -1339,6 +1345,7 @@ static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {
1339 "blsp1_qup2_spi_apps_clk_src", 1345 "blsp1_qup2_spi_apps_clk_src",
1340 }, 1346 },
1341 .num_parents = 1, 1347 .num_parents = 1,
1348 .flags = CLK_SET_RATE_PARENT,
1342 .ops = &clk_branch2_ops, 1349 .ops = &clk_branch2_ops,
1343 }, 1350 },
1344 }, 1351 },
@@ -1356,6 +1363,7 @@ static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {
1356 "blsp1_qup3_i2c_apps_clk_src", 1363 "blsp1_qup3_i2c_apps_clk_src",
1357 }, 1364 },
1358 .num_parents = 1, 1365 .num_parents = 1,
1366 .flags = CLK_SET_RATE_PARENT,
1359 .ops = &clk_branch2_ops, 1367 .ops = &clk_branch2_ops,
1360 }, 1368 },
1361 }, 1369 },
@@ -1373,6 +1381,7 @@ static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {
1373 "blsp1_qup3_spi_apps_clk_src", 1381 "blsp1_qup3_spi_apps_clk_src",
1374 }, 1382 },
1375 .num_parents = 1, 1383 .num_parents = 1,
1384 .flags = CLK_SET_RATE_PARENT,
1376 .ops = &clk_branch2_ops, 1385 .ops = &clk_branch2_ops,
1377 }, 1386 },
1378 }, 1387 },
@@ -1390,6 +1399,7 @@ static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {
1390 "blsp1_qup4_i2c_apps_clk_src", 1399 "blsp1_qup4_i2c_apps_clk_src",
1391 }, 1400 },
1392 .num_parents = 1, 1401 .num_parents = 1,
1402 .flags = CLK_SET_RATE_PARENT,
1393 .ops = &clk_branch2_ops, 1403 .ops = &clk_branch2_ops,
1394 }, 1404 },
1395 }, 1405 },
@@ -1407,6 +1417,7 @@ static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {
1407 "blsp1_qup4_spi_apps_clk_src", 1417 "blsp1_qup4_spi_apps_clk_src",
1408 }, 1418 },
1409 .num_parents = 1, 1419 .num_parents = 1,
1420 .flags = CLK_SET_RATE_PARENT,
1410 .ops = &clk_branch2_ops, 1421 .ops = &clk_branch2_ops,
1411 }, 1422 },
1412 }, 1423 },
@@ -1424,6 +1435,7 @@ static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {
1424 "blsp1_qup5_i2c_apps_clk_src", 1435 "blsp1_qup5_i2c_apps_clk_src",
1425 }, 1436 },
1426 .num_parents = 1, 1437 .num_parents = 1,
1438 .flags = CLK_SET_RATE_PARENT,
1427 .ops = &clk_branch2_ops, 1439 .ops = &clk_branch2_ops,
1428 }, 1440 },
1429 }, 1441 },
@@ -1441,6 +1453,7 @@ static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {
1441 "blsp1_qup5_spi_apps_clk_src", 1453 "blsp1_qup5_spi_apps_clk_src",
1442 }, 1454 },
1443 .num_parents = 1, 1455 .num_parents = 1,
1456 .flags = CLK_SET_RATE_PARENT,
1444 .ops = &clk_branch2_ops, 1457 .ops = &clk_branch2_ops,
1445 }, 1458 },
1446 }, 1459 },
@@ -1458,6 +1471,7 @@ static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {
1458 "blsp1_qup6_i2c_apps_clk_src", 1471 "blsp1_qup6_i2c_apps_clk_src",
1459 }, 1472 },
1460 .num_parents = 1, 1473 .num_parents = 1,
1474 .flags = CLK_SET_RATE_PARENT,
1461 .ops = &clk_branch2_ops, 1475 .ops = &clk_branch2_ops,
1462 }, 1476 },
1463 }, 1477 },
@@ -1475,6 +1489,7 @@ static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {
1475 "blsp1_qup6_spi_apps_clk_src", 1489 "blsp1_qup6_spi_apps_clk_src",
1476 }, 1490 },
1477 .num_parents = 1, 1491 .num_parents = 1,
1492 .flags = CLK_SET_RATE_PARENT,
1478 .ops = &clk_branch2_ops, 1493 .ops = &clk_branch2_ops,
1479 }, 1494 },
1480 }, 1495 },
@@ -1505,6 +1520,7 @@ static struct clk_branch gcc_blsp1_uart1_apps_clk = {
1505 "blsp1_uart1_apps_clk_src", 1520 "blsp1_uart1_apps_clk_src",
1506 }, 1521 },
1507 .num_parents = 1, 1522 .num_parents = 1,
1523 .flags = CLK_SET_RATE_PARENT,
1508 .ops = &clk_branch2_ops, 1524 .ops = &clk_branch2_ops,
1509 }, 1525 },
1510 }, 1526 },
@@ -1522,6 +1538,7 @@ static struct clk_branch gcc_blsp1_uart2_apps_clk = {
1522 "blsp1_uart2_apps_clk_src", 1538 "blsp1_uart2_apps_clk_src",
1523 }, 1539 },
1524 .num_parents = 1, 1540 .num_parents = 1,
1541 .flags = CLK_SET_RATE_PARENT,
1525 .ops = &clk_branch2_ops, 1542 .ops = &clk_branch2_ops,
1526 }, 1543 },
1527 }, 1544 },
@@ -1539,6 +1556,7 @@ static struct clk_branch gcc_blsp1_uart3_apps_clk = {
1539 "blsp1_uart3_apps_clk_src", 1556 "blsp1_uart3_apps_clk_src",
1540 }, 1557 },
1541 .num_parents = 1, 1558 .num_parents = 1,
1559 .flags = CLK_SET_RATE_PARENT,
1542 .ops = &clk_branch2_ops, 1560 .ops = &clk_branch2_ops,
1543 }, 1561 },
1544 }, 1562 },
@@ -1569,6 +1587,7 @@ static struct clk_branch gcc_blsp2_qup1_i2c_apps_clk = {
1569 "blsp2_qup1_i2c_apps_clk_src", 1587 "blsp2_qup1_i2c_apps_clk_src",
1570 }, 1588 },
1571 .num_parents = 1, 1589 .num_parents = 1,
1590 .flags = CLK_SET_RATE_PARENT,
1572 .ops = &clk_branch2_ops, 1591 .ops = &clk_branch2_ops,
1573 }, 1592 },
1574 }, 1593 },
@@ -1586,6 +1605,7 @@ static struct clk_branch gcc_blsp2_qup1_spi_apps_clk = {
1586 "blsp2_qup1_spi_apps_clk_src", 1605 "blsp2_qup1_spi_apps_clk_src",
1587 }, 1606 },
1588 .num_parents = 1, 1607 .num_parents = 1,
1608 .flags = CLK_SET_RATE_PARENT,
1589 .ops = &clk_branch2_ops, 1609 .ops = &clk_branch2_ops,
1590 }, 1610 },
1591 }, 1611 },
@@ -1603,6 +1623,7 @@ static struct clk_branch gcc_blsp2_qup2_i2c_apps_clk = {
1603 "blsp2_qup2_i2c_apps_clk_src", 1623 "blsp2_qup2_i2c_apps_clk_src",
1604 }, 1624 },
1605 .num_parents = 1, 1625 .num_parents = 1,
1626 .flags = CLK_SET_RATE_PARENT,
1606 .ops = &clk_branch2_ops, 1627 .ops = &clk_branch2_ops,
1607 }, 1628 },
1608 }, 1629 },
@@ -1620,6 +1641,7 @@ static struct clk_branch gcc_blsp2_qup2_spi_apps_clk = {
1620 "blsp2_qup2_spi_apps_clk_src", 1641 "blsp2_qup2_spi_apps_clk_src",
1621 }, 1642 },
1622 .num_parents = 1, 1643 .num_parents = 1,
1644 .flags = CLK_SET_RATE_PARENT,
1623 .ops = &clk_branch2_ops, 1645 .ops = &clk_branch2_ops,
1624 }, 1646 },
1625 }, 1647 },
@@ -1637,6 +1659,7 @@ static struct clk_branch gcc_blsp2_qup3_i2c_apps_clk = {
1637 "blsp2_qup3_i2c_apps_clk_src", 1659 "blsp2_qup3_i2c_apps_clk_src",
1638 }, 1660 },
1639 .num_parents = 1, 1661 .num_parents = 1,
1662 .flags = CLK_SET_RATE_PARENT,
1640 .ops = &clk_branch2_ops, 1663 .ops = &clk_branch2_ops,
1641 }, 1664 },
1642 }, 1665 },
@@ -1654,6 +1677,7 @@ static struct clk_branch gcc_blsp2_qup3_spi_apps_clk = {
1654 "blsp2_qup3_spi_apps_clk_src", 1677 "blsp2_qup3_spi_apps_clk_src",
1655 }, 1678 },
1656 .num_parents = 1, 1679 .num_parents = 1,
1680 .flags = CLK_SET_RATE_PARENT,
1657 .ops = &clk_branch2_ops, 1681 .ops = &clk_branch2_ops,
1658 }, 1682 },
1659 }, 1683 },
@@ -1671,6 +1695,7 @@ static struct clk_branch gcc_blsp2_qup4_i2c_apps_clk = {
1671 "blsp2_qup4_i2c_apps_clk_src", 1695 "blsp2_qup4_i2c_apps_clk_src",
1672 }, 1696 },
1673 .num_parents = 1, 1697 .num_parents = 1,
1698 .flags = CLK_SET_RATE_PARENT,
1674 .ops = &clk_branch2_ops, 1699 .ops = &clk_branch2_ops,
1675 }, 1700 },
1676 }, 1701 },
@@ -1688,6 +1713,7 @@ static struct clk_branch gcc_blsp2_qup4_spi_apps_clk = {
1688 "blsp2_qup4_spi_apps_clk_src", 1713 "blsp2_qup4_spi_apps_clk_src",
1689 }, 1714 },
1690 .num_parents = 1, 1715 .num_parents = 1,
1716 .flags = CLK_SET_RATE_PARENT,
1691 .ops = &clk_branch2_ops, 1717 .ops = &clk_branch2_ops,
1692 }, 1718 },
1693 }, 1719 },
@@ -1705,6 +1731,7 @@ static struct clk_branch gcc_blsp2_qup5_i2c_apps_clk = {
1705 "blsp2_qup5_i2c_apps_clk_src", 1731 "blsp2_qup5_i2c_apps_clk_src",
1706 }, 1732 },
1707 .num_parents = 1, 1733 .num_parents = 1,
1734 .flags = CLK_SET_RATE_PARENT,
1708 .ops = &clk_branch2_ops, 1735 .ops = &clk_branch2_ops,
1709 }, 1736 },
1710 }, 1737 },
@@ -1722,6 +1749,7 @@ static struct clk_branch gcc_blsp2_qup5_spi_apps_clk = {
1722 "blsp2_qup5_spi_apps_clk_src", 1749 "blsp2_qup5_spi_apps_clk_src",
1723 }, 1750 },
1724 .num_parents = 1, 1751 .num_parents = 1,
1752 .flags = CLK_SET_RATE_PARENT,
1725 .ops = &clk_branch2_ops, 1753 .ops = &clk_branch2_ops,
1726 }, 1754 },
1727 }, 1755 },
@@ -1739,6 +1767,7 @@ static struct clk_branch gcc_blsp2_qup6_i2c_apps_clk = {
1739 "blsp2_qup6_i2c_apps_clk_src", 1767 "blsp2_qup6_i2c_apps_clk_src",
1740 }, 1768 },
1741 .num_parents = 1, 1769 .num_parents = 1,
1770 .flags = CLK_SET_RATE_PARENT,
1742 .ops = &clk_branch2_ops, 1771 .ops = &clk_branch2_ops,
1743 }, 1772 },
1744 }, 1773 },
@@ -1756,6 +1785,7 @@ static struct clk_branch gcc_blsp2_qup6_spi_apps_clk = {
1756 "blsp2_qup6_spi_apps_clk_src", 1785 "blsp2_qup6_spi_apps_clk_src",
1757 }, 1786 },
1758 .num_parents = 1, 1787 .num_parents = 1,
1788 .flags = CLK_SET_RATE_PARENT,
1759 .ops = &clk_branch2_ops, 1789 .ops = &clk_branch2_ops,
1760 }, 1790 },
1761 }, 1791 },
@@ -1786,6 +1816,7 @@ static struct clk_branch gcc_blsp2_uart1_apps_clk = {
1786 "blsp2_uart1_apps_clk_src", 1816 "blsp2_uart1_apps_clk_src",
1787 }, 1817 },
1788 .num_parents = 1, 1818 .num_parents = 1,
1819 .flags = CLK_SET_RATE_PARENT,
1789 .ops = &clk_branch2_ops, 1820 .ops = &clk_branch2_ops,
1790 }, 1821 },
1791 }, 1822 },
@@ -1803,6 +1834,7 @@ static struct clk_branch gcc_blsp2_uart2_apps_clk = {
1803 "blsp2_uart2_apps_clk_src", 1834 "blsp2_uart2_apps_clk_src",
1804 }, 1835 },
1805 .num_parents = 1, 1836 .num_parents = 1,
1837 .flags = CLK_SET_RATE_PARENT,
1806 .ops = &clk_branch2_ops, 1838 .ops = &clk_branch2_ops,
1807 }, 1839 },
1808 }, 1840 },
@@ -1820,6 +1852,7 @@ static struct clk_branch gcc_blsp2_uart3_apps_clk = {
1820 "blsp2_uart3_apps_clk_src", 1852 "blsp2_uart3_apps_clk_src",
1821 }, 1853 },
1822 .num_parents = 1, 1854 .num_parents = 1,
1855 .flags = CLK_SET_RATE_PARENT,
1823 .ops = &clk_branch2_ops, 1856 .ops = &clk_branch2_ops,
1824 }, 1857 },
1825 }, 1858 },
@@ -1837,6 +1870,7 @@ static struct clk_branch gcc_cfg_noc_usb3_axi_clk = {
1837 "usb30_master_clk_src", 1870 "usb30_master_clk_src",
1838 }, 1871 },
1839 .num_parents = 1, 1872 .num_parents = 1,
1873 .flags = CLK_SET_RATE_PARENT,
1840 .ops = &clk_branch2_ops, 1874 .ops = &clk_branch2_ops,
1841 }, 1875 },
1842 }, 1876 },
@@ -1854,6 +1888,7 @@ static struct clk_branch gcc_gp1_clk = {
1854 "gp1_clk_src", 1888 "gp1_clk_src",
1855 }, 1889 },
1856 .num_parents = 1, 1890 .num_parents = 1,
1891 .flags = CLK_SET_RATE_PARENT,
1857 .ops = &clk_branch2_ops, 1892 .ops = &clk_branch2_ops,
1858 }, 1893 },
1859 }, 1894 },
@@ -1871,6 +1906,7 @@ static struct clk_branch gcc_gp2_clk = {
1871 "gp2_clk_src", 1906 "gp2_clk_src",
1872 }, 1907 },
1873 .num_parents = 1, 1908 .num_parents = 1,
1909 .flags = CLK_SET_RATE_PARENT,
1874 .ops = &clk_branch2_ops, 1910 .ops = &clk_branch2_ops,
1875 }, 1911 },
1876 }, 1912 },
@@ -1888,6 +1924,7 @@ static struct clk_branch gcc_gp3_clk = {
1888 "gp3_clk_src", 1924 "gp3_clk_src",
1889 }, 1925 },
1890 .num_parents = 1, 1926 .num_parents = 1,
1927 .flags = CLK_SET_RATE_PARENT,
1891 .ops = &clk_branch2_ops, 1928 .ops = &clk_branch2_ops,
1892 }, 1929 },
1893 }, 1930 },
@@ -1957,6 +1994,7 @@ static struct clk_branch gcc_hmss_ahb_clk = {
1957 "hmss_ahb_clk_src", 1994 "hmss_ahb_clk_src",
1958 }, 1995 },
1959 .num_parents = 1, 1996 .num_parents = 1,
1997 .flags = CLK_SET_RATE_PARENT,
1960 .ops = &clk_branch2_ops, 1998 .ops = &clk_branch2_ops,
1961 }, 1999 },
1962 }, 2000 },
@@ -1987,6 +2025,7 @@ static struct clk_branch gcc_hmss_rbcpr_clk = {
1987 "hmss_rbcpr_clk_src", 2025 "hmss_rbcpr_clk_src",
1988 }, 2026 },
1989 .num_parents = 1, 2027 .num_parents = 1,
2028 .flags = CLK_SET_RATE_PARENT,
1990 .ops = &clk_branch2_ops, 2029 .ops = &clk_branch2_ops,
1991 }, 2030 },
1992 }, 2031 },
@@ -2088,6 +2127,7 @@ static struct clk_branch gcc_pcie_0_aux_clk = {
2088 "pcie_aux_clk_src", 2127 "pcie_aux_clk_src",
2089 }, 2128 },
2090 .num_parents = 1, 2129 .num_parents = 1,
2130 .flags = CLK_SET_RATE_PARENT,
2091 .ops = &clk_branch2_ops, 2131 .ops = &clk_branch2_ops,
2092 }, 2132 },
2093 }, 2133 },
@@ -2157,6 +2197,7 @@ static struct clk_branch gcc_pcie_phy_aux_clk = {
2157 "pcie_aux_clk_src", 2197 "pcie_aux_clk_src",
2158 }, 2198 },
2159 .num_parents = 1, 2199 .num_parents = 1,
2200 .flags = CLK_SET_RATE_PARENT,
2160 .ops = &clk_branch2_ops, 2201 .ops = &clk_branch2_ops,
2161 }, 2202 },
2162 }, 2203 },
@@ -2174,6 +2215,7 @@ static struct clk_branch gcc_pdm2_clk = {
2174 "pdm2_clk_src", 2215 "pdm2_clk_src",
2175 }, 2216 },
2176 .num_parents = 1, 2217 .num_parents = 1,
2218 .flags = CLK_SET_RATE_PARENT,
2177 .ops = &clk_branch2_ops, 2219 .ops = &clk_branch2_ops,
2178 }, 2220 },
2179 }, 2221 },
@@ -2243,6 +2285,7 @@ static struct clk_branch gcc_sdcc2_apps_clk = {
2243 "sdcc2_apps_clk_src", 2285 "sdcc2_apps_clk_src",
2244 }, 2286 },
2245 .num_parents = 1, 2287 .num_parents = 1,
2288 .flags = CLK_SET_RATE_PARENT,
2246 .ops = &clk_branch2_ops, 2289 .ops = &clk_branch2_ops,
2247 }, 2290 },
2248 }, 2291 },
@@ -2273,6 +2316,7 @@ static struct clk_branch gcc_sdcc4_apps_clk = {
2273 "sdcc4_apps_clk_src", 2316 "sdcc4_apps_clk_src",
2274 }, 2317 },
2275 .num_parents = 1, 2318 .num_parents = 1,
2319 .flags = CLK_SET_RATE_PARENT,
2276 .ops = &clk_branch2_ops, 2320 .ops = &clk_branch2_ops,
2277 }, 2321 },
2278 }, 2322 },
@@ -2316,6 +2360,7 @@ static struct clk_branch gcc_tsif_ref_clk = {
2316 "tsif_ref_clk_src", 2360 "tsif_ref_clk_src",
2317 }, 2361 },
2318 .num_parents = 1, 2362 .num_parents = 1,
2363 .flags = CLK_SET_RATE_PARENT,
2319 .ops = &clk_branch2_ops, 2364 .ops = &clk_branch2_ops,
2320 }, 2365 },
2321 }, 2366 },
@@ -2346,6 +2391,7 @@ static struct clk_branch gcc_ufs_axi_clk = {
2346 "ufs_axi_clk_src", 2391 "ufs_axi_clk_src",
2347 }, 2392 },
2348 .num_parents = 1, 2393 .num_parents = 1,
2394 .flags = CLK_SET_RATE_PARENT,
2349 .ops = &clk_branch2_ops, 2395 .ops = &clk_branch2_ops,
2350 }, 2396 },
2351 }, 2397 },
@@ -2441,6 +2487,7 @@ static struct clk_branch gcc_usb30_master_clk = {
2441 "usb30_master_clk_src", 2487 "usb30_master_clk_src",
2442 }, 2488 },
2443 .num_parents = 1, 2489 .num_parents = 1,
2490 .flags = CLK_SET_RATE_PARENT,
2444 .ops = &clk_branch2_ops, 2491 .ops = &clk_branch2_ops,
2445 }, 2492 },
2446 }, 2493 },
@@ -2458,6 +2505,7 @@ static struct clk_branch gcc_usb30_mock_utmi_clk = {
2458 "usb30_mock_utmi_clk_src", 2505 "usb30_mock_utmi_clk_src",
2459 }, 2506 },
2460 .num_parents = 1, 2507 .num_parents = 1,
2508 .flags = CLK_SET_RATE_PARENT,
2461 .ops = &clk_branch2_ops, 2509 .ops = &clk_branch2_ops,
2462 }, 2510 },
2463 }, 2511 },
@@ -2488,6 +2536,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
2488 "usb3_phy_aux_clk_src", 2536 "usb3_phy_aux_clk_src",
2489 }, 2537 },
2490 .num_parents = 1, 2538 .num_parents = 1,
2539 .flags = CLK_SET_RATE_PARENT,
2491 .ops = &clk_branch2_ops, 2540 .ops = &clk_branch2_ops,
2492 }, 2541 },
2493 }, 2542 },
@@ -2495,7 +2544,7 @@ static struct clk_branch gcc_usb3_phy_aux_clk = {
2495 2544
2496static struct clk_branch gcc_usb3_phy_pipe_clk = { 2545static struct clk_branch gcc_usb3_phy_pipe_clk = {
2497 .halt_reg = 0x50004, 2546 .halt_reg = 0x50004,
2498 .halt_check = BRANCH_HALT, 2547 .halt_check = BRANCH_HALT_SKIP,
2499 .clkr = { 2548 .clkr = {
2500 .enable_reg = 0x50004, 2549 .enable_reg = 0x50004,
2501 .enable_mask = BIT(0), 2550 .enable_mask = BIT(0),
@@ -2910,6 +2959,10 @@ static const struct regmap_config gcc_msm8998_regmap_config = {
2910 .fast_io = true, 2959 .fast_io = true,
2911}; 2960};
2912 2961
2962static struct clk_hw *gcc_msm8998_hws[] = {
2963 &xo.hw,
2964};
2965
2913static const struct qcom_cc_desc gcc_msm8998_desc = { 2966static const struct qcom_cc_desc gcc_msm8998_desc = {
2914 .config = &gcc_msm8998_regmap_config, 2967 .config = &gcc_msm8998_regmap_config,
2915 .clks = gcc_msm8998_clocks, 2968 .clks = gcc_msm8998_clocks,
@@ -2918,6 +2971,8 @@ static const struct qcom_cc_desc gcc_msm8998_desc = {
2918 .num_resets = ARRAY_SIZE(gcc_msm8998_resets), 2971 .num_resets = ARRAY_SIZE(gcc_msm8998_resets),
2919 .gdscs = gcc_msm8998_gdscs, 2972 .gdscs = gcc_msm8998_gdscs,
2920 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs), 2973 .num_gdscs = ARRAY_SIZE(gcc_msm8998_gdscs),
2974 .clk_hws = gcc_msm8998_hws,
2975 .num_clk_hws = ARRAY_SIZE(gcc_msm8998_hws),
2921}; 2976};
2922 2977
2923static int gcc_msm8998_probe(struct platform_device *pdev) 2978static int gcc_msm8998_probe(struct platform_device *pdev)
@@ -2937,10 +2992,6 @@ static int gcc_msm8998_probe(struct platform_device *pdev)
2937 if (ret) 2992 if (ret)
2938 return ret; 2993 return ret;
2939 2994
2940 ret = devm_clk_hw_register(&pdev->dev, &xo.hw);
2941 if (ret)
2942 return ret;
2943
2944 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap); 2995 return qcom_cc_really_probe(pdev, &gcc_msm8998_desc, regmap);
2945} 2996}
2946 2997
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-30 22:34:47 -0500