1 files changed, 27 insertions, 20 deletions

diff --git a/drivers/bcma/driver_chipcommon_pmu.c b/drivers/bcma/driver_chipcommon_pmu.c
index 201faf106b3f..c62c788b3289 100644
--- a/drivers/bcma/driver_chipcommon_pmu.c
+++ b/drivers/bcma/driver_chipcommon_pmu.c
@@ -13,12 +13,13 @@
 #include <linux/export.h>
 #include <linux/bcma/bcma.h>
 
-static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
+u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
 {
         bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
         bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
         return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
 }
+EXPORT_SYMBOL_GPL(bcma_chipco_pll_read);
 
 void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
 {
@@ -144,7 +145,7 @@ static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
         }
 }
 
-void bcma_pmu_init(struct bcma_drv_cc *cc)
+void bcma_pmu_early_init(struct bcma_drv_cc *cc)
 {
         u32 pmucap;
 
@@ -153,7 +154,10 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
 
         bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
                    cc->pmu.rev, pmucap);
+}
 
+void bcma_pmu_init(struct bcma_drv_cc *cc)
+{
         if (cc->pmu.rev == 1)
                 bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
                               ~BCMA_CC_PMU_CTL_NOILPONW);
@@ -165,7 +169,7 @@ void bcma_pmu_init(struct bcma_drv_cc *cc)
         bcma_pmu_workarounds(cc);
 }
 
-u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
+u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
 {
         struct bcma_bus *bus = cc->core->bus;
 
@@ -193,7 +197,7 @@ u32 bcma_pmu_alp_clock(struct bcma_drv_cc *cc)
 /* Find the output of the "m" pll divider given pll controls that start with
  * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
  */
-static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 {
         u32 tmp, div, ndiv, p1, p2, fc;
         struct bcma_bus *bus = cc->core->bus;
@@ -222,14 +226,14 @@ static u32 bcma_pmu_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
         ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
 
         /* Do calculation in Mhz */
-        fc = bcma_pmu_alp_clock(cc) / 1000000;
+        fc = bcma_pmu_get_alp_clock(cc) / 1000000;
         fc = (p1 * ndiv * fc) / p2;
 
         /* Return clock in Hertz */
         return (fc / div) * 1000000;
 }
 
-static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
+static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 {
         u32 tmp, ndiv, p1div, p2div;
         u32 clock;
@@ -260,7 +264,7 @@ static u32 bcma_pmu_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
 }
 
 /* query bus clock frequency for PMU-enabled chipcommon */
-static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
+static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
 {
         struct bcma_bus *bus = cc->core->bus;
 
@@ -268,40 +272,42 @@ static u32 bcma_pmu_get_clockcontrol(struct bcma_drv_cc *cc)
         case BCMA_CHIP_ID_BCM4716:
         case BCMA_CHIP_ID_BCM4748:
         case BCMA_CHIP_ID_BCM47162:
-                return bcma_pmu_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
-                                      BCMA_CC_PMU5_MAINPLL_SSB);
+                return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
+                                          BCMA_CC_PMU5_MAINPLL_SSB);
         case BCMA_CHIP_ID_BCM5356:
-                return bcma_pmu_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
-                                      BCMA_CC_PMU5_MAINPLL_SSB);
+                return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
+                                          BCMA_CC_PMU5_MAINPLL_SSB);
         case BCMA_CHIP_ID_BCM5357:
         case BCMA_CHIP_ID_BCM4749:
-                return bcma_pmu_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
-                                      BCMA_CC_PMU5_MAINPLL_SSB);
+                return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
+                                          BCMA_CC_PMU5_MAINPLL_SSB);
         case BCMA_CHIP_ID_BCM4706:
-                return bcma_pmu_clock_bcm4706(cc, BCMA_CC_PMU4706_MAINPLL_PLL0,
-                                              BCMA_CC_PMU5_MAINPLL_SSB);
+                return bcma_pmu_pll_clock_bcm4706(cc,
+                                                  BCMA_CC_PMU4706_MAINPLL_PLL0,
+                                                  BCMA_CC_PMU5_MAINPLL_SSB);
         case BCMA_CHIP_ID_BCM53572:
                 return 75000000;
         default:
-                bcma_warn(bus, "No backplane clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
+                bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
                           bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
         }
         return BCMA_CC_PMU_HT_CLOCK;
 }
 
 /* query cpu clock frequency for PMU-enabled chipcommon */
-u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
+u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
 {
         struct bcma_bus *bus = cc->core->bus;
 
         if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
                 return 300000000;
 
+        /* New PMUs can have different clock for bus and CPU */
         if (cc->pmu.rev >= 5) {
                 u32 pll;
                 switch (bus->chipinfo.id) {
                 case BCMA_CHIP_ID_BCM4706:
-                        return bcma_pmu_clock_bcm4706(cc,
+                        return bcma_pmu_pll_clock_bcm4706(cc,
                                                 BCMA_CC_PMU4706_MAINPLL_PLL0,
                                                 BCMA_CC_PMU5_MAINPLL_CPU);
                 case BCMA_CHIP_ID_BCM5356:
@@ -316,10 +322,11 @@ u32 bcma_pmu_get_clockcpu(struct bcma_drv_cc *cc)
                         break;
                 }
 
-                return bcma_pmu_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
+                return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
         }
 
-        return bcma_pmu_get_clockcontrol(cc);
+        /* On old PMUs CPU has the same clock as the bus */
+        return bcma_pmu_get_bus_clock(cc);
 }
 
 static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,