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path: root/drivers/acpi/pci_mcfg.c
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Diffstat (limited to 'drivers/acpi/pci_mcfg.c')
-rw-r--r--drivers/acpi/pci_mcfg.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/acpi/pci_mcfg.c b/drivers/acpi/pci_mcfg.c
index 2944353253ed..a4e8432fc2fb 100644
--- a/drivers/acpi/pci_mcfg.c
+++ b/drivers/acpi/pci_mcfg.c
@@ -54,6 +54,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
54 54
55#define QCOM_ECAM32(seg) \ 55#define QCOM_ECAM32(seg) \
56 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops } 56 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
57
57 QCOM_ECAM32(0), 58 QCOM_ECAM32(0),
58 QCOM_ECAM32(1), 59 QCOM_ECAM32(1),
59 QCOM_ECAM32(2), 60 QCOM_ECAM32(2),
@@ -68,6 +69,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
68 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \ 69 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
69 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \ 70 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
70 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops } 71 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
72
71 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops), 73 HISI_QUAD_DOM("HIP05 ", 0, &hisi_pcie_ops),
72 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops), 74 HISI_QUAD_DOM("HIP06 ", 0, &hisi_pcie_ops),
73 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops), 75 HISI_QUAD_DOM("HIP07 ", 0, &hisi_pcie_ops),
@@ -77,6 +79,7 @@ static struct mcfg_fixup mcfg_quirks[] = {
77 79
78#define THUNDER_PEM_RES(addr, node) \ 80#define THUNDER_PEM_RES(addr, node) \
79 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M) 81 DEFINE_RES_MEM((addr) + ((u64) (node) << 44), 0x39 * SZ_16M)
82
80#define THUNDER_PEM_QUIRK(rev, node) \ 83#define THUNDER_PEM_QUIRK(rev, node) \
81 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \ 84 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
82 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \ 85 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x88001f000000UL, node) }, \
@@ -90,13 +93,16 @@ static struct mcfg_fixup mcfg_quirks[] = {
90 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \ 93 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x894057000000UL, node) }, \
91 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \ 94 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
92 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) } 95 &thunder_pem_ecam_ops, THUNDER_PEM_RES(0x89808f000000UL, node) }
93 /* SoC pass2.x */
94 THUNDER_PEM_QUIRK(1, 0),
95 THUNDER_PEM_QUIRK(1, 1),
96 96
97#define THUNDER_ECAM_QUIRK(rev, seg) \ 97#define THUNDER_ECAM_QUIRK(rev, seg) \
98 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \ 98 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
99 &pci_thunder_ecam_ops } 99 &pci_thunder_ecam_ops }
100
101 /* SoC pass2.x */
102 THUNDER_PEM_QUIRK(1, 0),
103 THUNDER_PEM_QUIRK(1, 1),
104 THUNDER_ECAM_QUIRK(1, 10),
105
100 /* SoC pass1.x */ 106 /* SoC pass1.x */
101 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */ 107 THUNDER_PEM_QUIRK(2, 0), /* off-chip devices */
102 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */ 108 THUNDER_PEM_QUIRK(2, 1), /* off-chip devices */
@@ -112,9 +118,11 @@ static struct mcfg_fixup mcfg_quirks[] = {
112#define XGENE_V1_ECAM_MCFG(rev, seg) \ 118#define XGENE_V1_ECAM_MCFG(rev, seg) \
113 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ 119 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
114 &xgene_v1_pcie_ecam_ops } 120 &xgene_v1_pcie_ecam_ops }
121
115#define XGENE_V2_ECAM_MCFG(rev, seg) \ 122#define XGENE_V2_ECAM_MCFG(rev, seg) \
116 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \ 123 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
117 &xgene_v2_pcie_ecam_ops } 124 &xgene_v2_pcie_ecam_ops }
125
118 /* X-Gene SoC with v1 PCIe controller */ 126 /* X-Gene SoC with v1 PCIe controller */
119 XGENE_V1_ECAM_MCFG(1, 0), 127 XGENE_V1_ECAM_MCFG(1, 0),
120 XGENE_V1_ECAM_MCFG(1, 1), 128 XGENE_V1_ECAM_MCFG(1, 1),