2 files changed, 18 insertions, 0 deletions

diff --git a/arch/x86/events/amd/uncore.c b/arch/x86/events/amd/uncore.c
index 981ba5e8241b..8671de126eac 100644
--- a/arch/x86/events/amd/uncore.c
+++ b/arch/x86/events/amd/uncore.c
@@ -36,6 +36,7 @@
 
 static int num_counters_llc;
 static int num_counters_nb;
+static bool l3_mask;
 
 static HLIST_HEAD(uncore_unused_list);
 
@@ -209,6 +210,13 @@ static int amd_uncore_event_init(struct perf_event *event)
         hwc->config = event->attr.config & AMD64_RAW_EVENT_MASK_NB;
         hwc->idx = -1;
 
+        /*
+         * SliceMask and ThreadMask need to be set for certain L3 events in
+         * Family 17h. For other events, the two fields do not affect the count.
+         */
+        if (l3_mask)
+                hwc->config |= (AMD64_L3_SLICE_MASK | AMD64_L3_THREAD_MASK);
+
         if (event->cpu < 0)
                 return -EINVAL;
 
@@ -525,6 +533,7 @@ static int __init amd_uncore_init(void)
                 amd_llc_pmu.name          = "amd_l3";
                 format_attr_event_df.show = &event_show_df;
                 format_attr_event_l3.show = &event_show_l3;
+                l3_mask                   = true;
         } else {
                 num_counters_nb           = NUM_COUNTERS_NB;
                 num_counters_llc          = NUM_COUNTERS_L2;
@@ -532,6 +541,7 @@ static int __init amd_uncore_init(void)
                 amd_llc_pmu.name          = "amd_l2";
                 format_attr_event_df      = format_attr_event;
                 format_attr_event_l3      = format_attr_event;
+                l3_mask                   = false;
         }
 
         amd_nb_pmu.attr_groups  = amd_uncore_attr_groups_df;
diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index 12f54082f4c8..78241b736f2a 100644
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -46,6 +46,14 @@
 #define INTEL_ARCH_EVENT_MASK   \
         (ARCH_PERFMON_EVENTSEL_UMASK | ARCH_PERFMON_EVENTSEL_EVENT)
 
+#define AMD64_L3_SLICE_SHIFT                            48
+#define AMD64_L3_SLICE_MASK                             \
+        ((0xFULL) << AMD64_L3_SLICE_SHIFT)
+
+#define AMD64_L3_THREAD_SHIFT                           56
+#define AMD64_L3_THREAD_MASK                            \
+        ((0xFFULL) << AMD64_L3_THREAD_SHIFT)
+
 #define X86_RAW_EVENT_MASK              \
         (ARCH_PERFMON_EVENTSEL_EVENT |  \
          ARCH_PERFMON_EVENTSEL_UMASK |  \