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-rw-r--r--arch/x86/include/asm/bios_ebda.h21
-rw-r--r--arch/x86/include/asm/uv/bios.h59
-rw-r--r--arch/x86/include/asm/uv/uv_bau.h2
-rw-r--r--arch/x86/include/asm/uv/uv_hub.h409
-rw-r--r--arch/x86/include/asm/uv/uv_mmrs.h2207
-rw-r--r--arch/x86/kernel/apic/x2apic_uv_x.c850
-rw-r--r--arch/x86/platform/uv/bios_uv.c48
-rw-r--r--arch/x86/platform/uv/tlb_uv.c38
-rw-r--r--arch/x86/platform/uv/uv_sysfs.c2
-rw-r--r--arch/x86/platform/uv/uv_time.c6
10 files changed, 2865 insertions, 777 deletions
diff --git a/arch/x86/include/asm/bios_ebda.h b/arch/x86/include/asm/bios_ebda.h
index aa6a3170ab5a..2b00c776f223 100644
--- a/arch/x86/include/asm/bios_ebda.h
+++ b/arch/x86/include/asm/bios_ebda.h
@@ -17,27 +17,6 @@ static inline unsigned int get_bios_ebda(void)
17 return address; /* 0 means none */ 17 return address; /* 0 means none */
18} 18}
19 19
20/*
21 * Return the sanitized length of the EBDA in bytes, if it exists.
22 */
23static inline unsigned int get_bios_ebda_length(void)
24{
25 unsigned int address;
26 unsigned int length;
27
28 address = get_bios_ebda();
29 if (!address)
30 return 0;
31
32 /* EBDA length is byte 0 of the EBDA (stored in KiB) */
33 length = *(unsigned char *)phys_to_virt(address);
34 length <<= 10;
35
36 /* Trim the length if it extends beyond 640KiB */
37 length = min_t(unsigned int, (640 * 1024) - address, length);
38 return length;
39}
40
41void reserve_ebda_region(void); 20void reserve_ebda_region(void);
42 21
43#ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION 22#ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION
diff --git a/arch/x86/include/asm/uv/bios.h b/arch/x86/include/asm/uv/bios.h
index 71605c7d5c5c..c852590254d5 100644
--- a/arch/x86/include/asm/uv/bios.h
+++ b/arch/x86/include/asm/uv/bios.h
@@ -51,15 +51,66 @@ enum {
51 BIOS_STATUS_UNAVAIL = -EBUSY 51 BIOS_STATUS_UNAVAIL = -EBUSY
52}; 52};
53 53
54/* Address map parameters */
55struct uv_gam_parameters {
56 u64 mmr_base;
57 u64 gru_base;
58 u8 mmr_shift; /* Convert PNode to MMR space offset */
59 u8 gru_shift; /* Convert PNode to GRU space offset */
60 u8 gpa_shift; /* Size of offset field in GRU phys addr */
61 u8 unused1;
62};
63
64/* UV_TABLE_GAM_RANGE_ENTRY values */
65#define UV_GAM_RANGE_TYPE_UNUSED 0 /* End of table */
66#define UV_GAM_RANGE_TYPE_RAM 1 /* Normal RAM */
67#define UV_GAM_RANGE_TYPE_NVRAM 2 /* Non-volatile memory */
68#define UV_GAM_RANGE_TYPE_NV_WINDOW 3 /* NVMDIMM block window */
69#define UV_GAM_RANGE_TYPE_NV_MAILBOX 4 /* NVMDIMM mailbox */
70#define UV_GAM_RANGE_TYPE_HOLE 5 /* Unused address range */
71#define UV_GAM_RANGE_TYPE_MAX 6
72
73/* The structure stores PA bits 56:26, for 64MB granularity */
74#define UV_GAM_RANGE_SHFT 26 /* 64MB */
75
76struct uv_gam_range_entry {
77 char type; /* Entry type: GAM_RANGE_TYPE_UNUSED, etc. */
78 char unused1;
79 u16 nasid; /* HNasid */
80 u16 sockid; /* Socket ID, high bits of APIC ID */
81 u16 pnode; /* Index to MMR and GRU spaces */
82 u32 pxm; /* ACPI proximity domain number */
83 u32 limit; /* PA bits 56:26 (UV_GAM_RANGE_SHFT) */
84};
85
86#define UV_SYSTAB_SIG "UVST"
87#define UV_SYSTAB_VERSION_1 1 /* UV1/2/3 BIOS version */
88#define UV_SYSTAB_VERSION_UV4 0x400 /* UV4 BIOS base version */
89#define UV_SYSTAB_VERSION_UV4_1 0x401 /* + gpa_shift */
90#define UV_SYSTAB_VERSION_UV4_2 0x402 /* + TYPE_NVRAM/WINDOW/MBOX */
91#define UV_SYSTAB_VERSION_UV4_LATEST UV_SYSTAB_VERSION_UV4_2
92
93#define UV_SYSTAB_TYPE_UNUSED 0 /* End of table (offset == 0) */
94#define UV_SYSTAB_TYPE_GAM_PARAMS 1 /* GAM PARAM conversions */
95#define UV_SYSTAB_TYPE_GAM_RNG_TBL 2 /* GAM entry table */
96#define UV_SYSTAB_TYPE_MAX 3
97
54/* 98/*
55 * The UV system table describes specific firmware 99 * The UV system table describes specific firmware
56 * capabilities available to the Linux kernel at runtime. 100 * capabilities available to the Linux kernel at runtime.
57 */ 101 */
58struct uv_systab { 102struct uv_systab {
59 char signature[4]; /* must be "UVST" */ 103 char signature[4]; /* must be UV_SYSTAB_SIG */
60 u32 revision; /* distinguish different firmware revs */ 104 u32 revision; /* distinguish different firmware revs */
61 u64 function; /* BIOS runtime callback function ptr */ 105 u64 function; /* BIOS runtime callback function ptr */
106 u32 size; /* systab size (starting with _VERSION_UV4) */
107 struct {
108 u32 type:8; /* type of entry */
109 u32 offset:24; /* byte offset from struct start to entry */
110 } entry[1]; /* additional entries follow */
62}; 111};
112extern struct uv_systab *uv_systab;
113/* (... end of definitions from UV BIOS ...) */
63 114
64enum { 115enum {
65 BIOS_FREQ_BASE_PLATFORM = 0, 116 BIOS_FREQ_BASE_PLATFORM = 0,
@@ -99,7 +150,11 @@ extern s64 uv_bios_change_memprotect(u64, u64, enum uv_memprotect);
99extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *); 150extern s64 uv_bios_reserved_page_pa(u64, u64 *, u64 *, u64 *);
100extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus); 151extern int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus);
101 152
153#ifdef CONFIG_EFI
102extern void uv_bios_init(void); 154extern void uv_bios_init(void);
155#else
156void uv_bios_init(void) { }
157#endif
103 158
104extern unsigned long sn_rtc_cycles_per_second; 159extern unsigned long sn_rtc_cycles_per_second;
105extern int uv_type; 160extern int uv_type;
@@ -107,7 +162,7 @@ extern long sn_partition_id;
107extern long sn_coherency_id; 162extern long sn_coherency_id;
108extern long sn_region_size; 163extern long sn_region_size;
109extern long system_serial_number; 164extern long system_serial_number;
110#define partition_coherence_id() (sn_coherency_id) 165#define uv_partition_coherence_id() (sn_coherency_id)
111 166
112extern struct kobject *sgi_uv_kobj; /* /sys/firmware/sgi_uv */ 167extern struct kobject *sgi_uv_kobj; /* /sys/firmware/sgi_uv */
113 168
diff --git a/arch/x86/include/asm/uv/uv_bau.h b/arch/x86/include/asm/uv/uv_bau.h
index fc808b83fccb..cc44d926c17e 100644
--- a/arch/x86/include/asm/uv/uv_bau.h
+++ b/arch/x86/include/asm/uv/uv_bau.h
@@ -598,7 +598,7 @@ struct bau_control {
598 int timeout_tries; 598 int timeout_tries;
599 int ipi_attempts; 599 int ipi_attempts;
600 int conseccompletes; 600 int conseccompletes;
601 short nobau; 601 bool nobau;
602 short baudisabled; 602 short baudisabled;
603 short cpu; 603 short cpu;
604 short osnode; 604 short osnode;
diff --git a/arch/x86/include/asm/uv/uv_hub.h b/arch/x86/include/asm/uv/uv_hub.h
index ea7074784cc4..097b80c989c4 100644
--- a/arch/x86/include/asm/uv/uv_hub.h
+++ b/arch/x86/include/asm/uv/uv_hub.h
@@ -16,9 +16,11 @@
16#include <linux/percpu.h> 16#include <linux/percpu.h>
17#include <linux/timer.h> 17#include <linux/timer.h>
18#include <linux/io.h> 18#include <linux/io.h>
19#include <linux/topology.h>
19#include <asm/types.h> 20#include <asm/types.h>
20#include <asm/percpu.h> 21#include <asm/percpu.h>
21#include <asm/uv/uv_mmrs.h> 22#include <asm/uv/uv_mmrs.h>
23#include <asm/uv/bios.h>
22#include <asm/irq_vectors.h> 24#include <asm/irq_vectors.h>
23#include <asm/io_apic.h> 25#include <asm/io_apic.h>
24 26
@@ -103,7 +105,6 @@
103 * processor APICID register. 105 * processor APICID register.
104 */ 106 */
105 107
106
107/* 108/*
108 * Maximum number of bricks in all partitions and in all coherency domains. 109 * Maximum number of bricks in all partitions and in all coherency domains.
109 * This is the total number of bricks accessible in the numalink fabric. It 110 * This is the total number of bricks accessible in the numalink fabric. It
@@ -127,6 +128,7 @@
127 */ 128 */
128#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2) 129#define UV_MAX_NASID_VALUE (UV_MAX_NUMALINK_BLADES * 2)
129 130
131/* System Controller Interface Reg info */
130struct uv_scir_s { 132struct uv_scir_s {
131 struct timer_list timer; 133 struct timer_list timer;
132 unsigned long offset; 134 unsigned long offset;
@@ -137,71 +139,173 @@ struct uv_scir_s {
137 unsigned char enabled; 139 unsigned char enabled;
138}; 140};
139 141
142/* GAM (globally addressed memory) range table */
143struct uv_gam_range_s {
144 u32 limit; /* PA bits 56:26 (GAM_RANGE_SHFT) */
145 u16 nasid; /* node's global physical address */
146 s8 base; /* entry index of node's base addr */
147 u8 reserved;
148};
149
140/* 150/*
141 * The following defines attributes of the HUB chip. These attributes are 151 * The following defines attributes of the HUB chip. These attributes are
142 * frequently referenced and are kept in the per-cpu data areas of each cpu. 152 * frequently referenced and are kept in a common per hub struct.
143 * They are kept together in a struct to minimize cache misses. 153 * After setup, the struct is read only, so it should be readily
154 * available in the L3 cache on the cpu socket for the node.
144 */ 155 */
145struct uv_hub_info_s { 156struct uv_hub_info_s {
146 unsigned long global_mmr_base; 157 unsigned long global_mmr_base;
158 unsigned long global_mmr_shift;
147 unsigned long gpa_mask; 159 unsigned long gpa_mask;
148 unsigned int gnode_extra; 160 unsigned short *socket_to_node;
161 unsigned short *socket_to_pnode;
162 unsigned short *pnode_to_socket;
163 struct uv_gam_range_s *gr_table;
164 unsigned short min_socket;
165 unsigned short min_pnode;
166 unsigned char m_val;
167 unsigned char n_val;
168 unsigned char gr_table_len;
149 unsigned char hub_revision; 169 unsigned char hub_revision;
150 unsigned char apic_pnode_shift; 170 unsigned char apic_pnode_shift;
171 unsigned char gpa_shift;
151 unsigned char m_shift; 172 unsigned char m_shift;
152 unsigned char n_lshift; 173 unsigned char n_lshift;
174 unsigned int gnode_extra;
153 unsigned long gnode_upper; 175 unsigned long gnode_upper;
154 unsigned long lowmem_remap_top; 176 unsigned long lowmem_remap_top;
155 unsigned long lowmem_remap_base; 177 unsigned long lowmem_remap_base;
178 unsigned long global_gru_base;
179 unsigned long global_gru_shift;
156 unsigned short pnode; 180 unsigned short pnode;
157 unsigned short pnode_mask; 181 unsigned short pnode_mask;
158 unsigned short coherency_domain_number; 182 unsigned short coherency_domain_number;
159 unsigned short numa_blade_id; 183 unsigned short numa_blade_id;
160 unsigned char blade_processor_id; 184 unsigned short nr_possible_cpus;
161 unsigned char m_val; 185 unsigned short nr_online_cpus;
162 unsigned char n_val; 186 short memory_nid;
187};
188
189/* CPU specific info with a pointer to the hub common info struct */
190struct uv_cpu_info_s {
191 void *p_uv_hub_info;
192 unsigned char blade_cpu_id;
163 struct uv_scir_s scir; 193 struct uv_scir_s scir;
164}; 194};
195DECLARE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
196
197#define uv_cpu_info this_cpu_ptr(&__uv_cpu_info)
198#define uv_cpu_info_per(cpu) (&per_cpu(__uv_cpu_info, cpu))
199
200#define uv_scir_info (&uv_cpu_info->scir)
201#define uv_cpu_scir_info(cpu) (&uv_cpu_info_per(cpu)->scir)
202
203/* Node specific hub common info struct */
204extern void **__uv_hub_info_list;
205static inline struct uv_hub_info_s *uv_hub_info_list(int node)
206{
207 return (struct uv_hub_info_s *)__uv_hub_info_list[node];
208}
209
210static inline struct uv_hub_info_s *_uv_hub_info(void)
211{
212 return (struct uv_hub_info_s *)uv_cpu_info->p_uv_hub_info;
213}
214#define uv_hub_info _uv_hub_info()
165 215
166DECLARE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 216static inline struct uv_hub_info_s *uv_cpu_hub_info(int cpu)
167#define uv_hub_info this_cpu_ptr(&__uv_hub_info) 217{
168#define uv_cpu_hub_info(cpu) (&per_cpu(__uv_hub_info, cpu)) 218 return (struct uv_hub_info_s *)uv_cpu_info_per(cpu)->p_uv_hub_info;
219}
220
221#define UV_HUB_INFO_VERSION 0x7150
222extern int uv_hub_info_version(void);
223static inline int uv_hub_info_check(int version)
224{
225 if (uv_hub_info_version() == version)
226 return 0;
227
228 pr_crit("UV: uv_hub_info version(%x) mismatch, expecting(%x)\n",
229 uv_hub_info_version(), version);
230
231 BUG(); /* Catastrophic - cannot continue on unknown UV system */
232}
233#define _uv_hub_info_check() uv_hub_info_check(UV_HUB_INFO_VERSION)
169 234
170/* 235/*
171 * Hub revisions less than UV2_HUB_REVISION_BASE are UV1 hubs. All UV2 236 * HUB revision ranges for each UV HUB architecture.
172 * hubs have revision numbers greater than or equal to UV2_HUB_REVISION_BASE.
173 * This is a software convention - NOT the hardware revision numbers in 237 * This is a software convention - NOT the hardware revision numbers in
174 * the hub chip. 238 * the hub chip.
175 */ 239 */
176#define UV1_HUB_REVISION_BASE 1 240#define UV1_HUB_REVISION_BASE 1
177#define UV2_HUB_REVISION_BASE 3 241#define UV2_HUB_REVISION_BASE 3
178#define UV3_HUB_REVISION_BASE 5 242#define UV3_HUB_REVISION_BASE 5
243#define UV4_HUB_REVISION_BASE 7
179 244
245#ifdef UV1_HUB_IS_SUPPORTED
180static inline int is_uv1_hub(void) 246static inline int is_uv1_hub(void)
181{ 247{
182 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE; 248 return uv_hub_info->hub_revision < UV2_HUB_REVISION_BASE;
183} 249}
250#else
251static inline int is_uv1_hub(void)
252{
253 return 0;
254}
255#endif
184 256
257#ifdef UV2_HUB_IS_SUPPORTED
185static inline int is_uv2_hub(void) 258static inline int is_uv2_hub(void)
186{ 259{
187 return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) && 260 return ((uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE) &&
188 (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE)); 261 (uv_hub_info->hub_revision < UV3_HUB_REVISION_BASE));
189} 262}
263#else
264static inline int is_uv2_hub(void)
265{
266 return 0;
267}
268#endif
190 269
270#ifdef UV3_HUB_IS_SUPPORTED
271static inline int is_uv3_hub(void)
272{
273 return ((uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE) &&
274 (uv_hub_info->hub_revision < UV4_HUB_REVISION_BASE));
275}
276#else
191static inline int is_uv3_hub(void) 277static inline int is_uv3_hub(void)
192{ 278{
193 return uv_hub_info->hub_revision >= UV3_HUB_REVISION_BASE; 279 return 0;
194} 280}
281#endif
195 282
196static inline int is_uv_hub(void) 283#ifdef UV4_HUB_IS_SUPPORTED
284static inline int is_uv4_hub(void)
197{ 285{
198 return uv_hub_info->hub_revision; 286 return uv_hub_info->hub_revision >= UV4_HUB_REVISION_BASE;
199} 287}
288#else
289static inline int is_uv4_hub(void)
290{
291 return 0;
292}
293#endif
200 294
201/* code common to uv2 and uv3 only */
202static inline int is_uvx_hub(void) 295static inline int is_uvx_hub(void)
203{ 296{
204 return uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE; 297 if (uv_hub_info->hub_revision >= UV2_HUB_REVISION_BASE)
298 return uv_hub_info->hub_revision;
299
300 return 0;
301}
302
303static inline int is_uv_hub(void)
304{
305#ifdef UV1_HUB_IS_SUPPORTED
306 return uv_hub_info->hub_revision;
307#endif
308 return is_uvx_hub();
205} 309}
206 310
207union uvh_apicid { 311union uvh_apicid {
@@ -243,24 +347,42 @@ union uvh_apicid {
243#define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024) 347#define UV3_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
244#define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024) 348#define UV3_GLOBAL_MMR32_SIZE (32UL * 1024 * 1024)
245 349
246#define UV_LOCAL_MMR_BASE (is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \ 350#define UV4_LOCAL_MMR_BASE 0xfa000000UL
247 (is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \ 351#define UV4_GLOBAL_MMR32_BASE 0xfc000000UL
248 UV3_LOCAL_MMR_BASE)) 352#define UV4_LOCAL_MMR_SIZE (32UL * 1024 * 1024)
249#define UV_GLOBAL_MMR32_BASE (is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE :\ 353#define UV4_GLOBAL_MMR32_SIZE (16UL * 1024 * 1024)
250 (is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE :\ 354
251 UV3_GLOBAL_MMR32_BASE)) 355#define UV_LOCAL_MMR_BASE ( \
252#define UV_LOCAL_MMR_SIZE (is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \ 356 is_uv1_hub() ? UV1_LOCAL_MMR_BASE : \
253 (is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \ 357 is_uv2_hub() ? UV2_LOCAL_MMR_BASE : \
254 UV3_LOCAL_MMR_SIZE)) 358 is_uv3_hub() ? UV3_LOCAL_MMR_BASE : \
255#define UV_GLOBAL_MMR32_SIZE (is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE :\ 359 /*is_uv4_hub*/ UV4_LOCAL_MMR_BASE)
256 (is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE :\ 360
257 UV3_GLOBAL_MMR32_SIZE)) 361#define UV_GLOBAL_MMR32_BASE ( \
362 is_uv1_hub() ? UV1_GLOBAL_MMR32_BASE : \
363 is_uv2_hub() ? UV2_GLOBAL_MMR32_BASE : \
364 is_uv3_hub() ? UV3_GLOBAL_MMR32_BASE : \
365 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_BASE)
366
367#define UV_LOCAL_MMR_SIZE ( \
368 is_uv1_hub() ? UV1_LOCAL_MMR_SIZE : \
369 is_uv2_hub() ? UV2_LOCAL_MMR_SIZE : \
370 is_uv3_hub() ? UV3_LOCAL_MMR_SIZE : \
371 /*is_uv4_hub*/ UV4_LOCAL_MMR_SIZE)
372
373#define UV_GLOBAL_MMR32_SIZE ( \
374 is_uv1_hub() ? UV1_GLOBAL_MMR32_SIZE : \
375 is_uv2_hub() ? UV2_GLOBAL_MMR32_SIZE : \
376 is_uv3_hub() ? UV3_GLOBAL_MMR32_SIZE : \
377 /*is_uv4_hub*/ UV4_GLOBAL_MMR32_SIZE)
378
258#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base) 379#define UV_GLOBAL_MMR64_BASE (uv_hub_info->global_mmr_base)
259 380
260#define UV_GLOBAL_GRU_MMR_BASE 0x4000000 381#define UV_GLOBAL_GRU_MMR_BASE 0x4000000
261 382
262#define UV_GLOBAL_MMR32_PNODE_SHIFT 15 383#define UV_GLOBAL_MMR32_PNODE_SHIFT 15
263#define UV_GLOBAL_MMR64_PNODE_SHIFT 26 384#define _UV_GLOBAL_MMR64_PNODE_SHIFT 26
385#define UV_GLOBAL_MMR64_PNODE_SHIFT (uv_hub_info->global_mmr_shift)
264 386
265#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT)) 387#define UV_GLOBAL_MMR32_PNODE_BITS(p) ((p) << (UV_GLOBAL_MMR32_PNODE_SHIFT))
266 388
@@ -307,18 +429,74 @@ union uvh_apicid {
307 * between socket virtual and socket physical addresses. 429 * between socket virtual and socket physical addresses.
308 */ 430 */
309 431
432/* global bits offset - number of local address bits in gpa for this UV arch */
433static inline unsigned int uv_gpa_shift(void)
434{
435 return uv_hub_info->gpa_shift;
436}
437#define _uv_gpa_shift
438
439/* Find node that has the address range that contains global address */
440static inline struct uv_gam_range_s *uv_gam_range(unsigned long pa)
441{
442 struct uv_gam_range_s *gr = uv_hub_info->gr_table;
443 unsigned long pal = (pa & uv_hub_info->gpa_mask) >> UV_GAM_RANGE_SHFT;
444 int i, num = uv_hub_info->gr_table_len;
445
446 if (gr) {
447 for (i = 0; i < num; i++, gr++) {
448 if (pal < gr->limit)
449 return gr;
450 }
451 }
452 pr_crit("UV: GAM Range for 0x%lx not found at %p!\n", pa, gr);
453 BUG();
454}
455
456/* Return base address of node that contains global address */
457static inline unsigned long uv_gam_range_base(unsigned long pa)
458{
459 struct uv_gam_range_s *gr = uv_gam_range(pa);
460 int base = gr->base;
461
462 if (base < 0)
463 return 0UL;
464
465 return uv_hub_info->gr_table[base].limit;
466}
467
468/* socket phys RAM --> UV global NASID (UV4+) */
469static inline unsigned long uv_soc_phys_ram_to_nasid(unsigned long paddr)
470{
471 return uv_gam_range(paddr)->nasid;
472}
473#define _uv_soc_phys_ram_to_nasid
474
475/* socket virtual --> UV global NASID (UV4+) */
476static inline unsigned long uv_gpa_nasid(void *v)
477{
478 return uv_soc_phys_ram_to_nasid(__pa(v));
479}
480
310/* socket phys RAM --> UV global physical address */ 481/* socket phys RAM --> UV global physical address */
311static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr) 482static inline unsigned long uv_soc_phys_ram_to_gpa(unsigned long paddr)
312{ 483{
484 unsigned int m_val = uv_hub_info->m_val;
485
313 if (paddr < uv_hub_info->lowmem_remap_top) 486 if (paddr < uv_hub_info->lowmem_remap_top)
314 paddr |= uv_hub_info->lowmem_remap_base; 487 paddr |= uv_hub_info->lowmem_remap_base;
315 paddr |= uv_hub_info->gnode_upper; 488 paddr |= uv_hub_info->gnode_upper;
316 paddr = ((paddr << uv_hub_info->m_shift) >> uv_hub_info->m_shift) | 489 if (m_val)
317 ((paddr >> uv_hub_info->m_val) << uv_hub_info->n_lshift); 490 paddr = ((paddr << uv_hub_info->m_shift)
491 >> uv_hub_info->m_shift) |
492 ((paddr >> uv_hub_info->m_val)
493 << uv_hub_info->n_lshift);
494 else
495 paddr |= uv_soc_phys_ram_to_nasid(paddr)
496 << uv_hub_info->gpa_shift;
318 return paddr; 497 return paddr;
319} 498}
320 499
321
322/* socket virtual --> UV global physical address */ 500/* socket virtual --> UV global physical address */
323static inline unsigned long uv_gpa(void *v) 501static inline unsigned long uv_gpa(void *v)
324{ 502{
@@ -338,54 +516,89 @@ static inline unsigned long uv_gpa_to_soc_phys_ram(unsigned long gpa)
338 unsigned long paddr; 516 unsigned long paddr;
339 unsigned long remap_base = uv_hub_info->lowmem_remap_base; 517 unsigned long remap_base = uv_hub_info->lowmem_remap_base;
340 unsigned long remap_top = uv_hub_info->lowmem_remap_top; 518 unsigned long remap_top = uv_hub_info->lowmem_remap_top;
519 unsigned int m_val = uv_hub_info->m_val;
520
521 if (m_val)
522 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
523 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
341 524
342 gpa = ((gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift) |
343 ((gpa >> uv_hub_info->n_lshift) << uv_hub_info->m_val);
344 paddr = gpa & uv_hub_info->gpa_mask; 525 paddr = gpa & uv_hub_info->gpa_mask;
345 if (paddr >= remap_base && paddr < remap_base + remap_top) 526 if (paddr >= remap_base && paddr < remap_base + remap_top)
346 paddr -= remap_base; 527 paddr -= remap_base;
347 return paddr; 528 return paddr;
348} 529}
349 530
350 531/* gpa -> gnode */
351/* gpa -> pnode */
352static inline unsigned long uv_gpa_to_gnode(unsigned long gpa) 532static inline unsigned long uv_gpa_to_gnode(unsigned long gpa)
353{ 533{
354 return gpa >> uv_hub_info->n_lshift; 534 unsigned int n_lshift = uv_hub_info->n_lshift;
535
536 if (n_lshift)
537 return gpa >> n_lshift;
538
539 return uv_gam_range(gpa)->nasid >> 1;
355} 540}
356 541
357/* gpa -> pnode */ 542/* gpa -> pnode */
358static inline int uv_gpa_to_pnode(unsigned long gpa) 543static inline int uv_gpa_to_pnode(unsigned long gpa)
359{ 544{
360 unsigned long n_mask = (1UL << uv_hub_info->n_val) - 1; 545 return uv_gpa_to_gnode(gpa) & uv_hub_info->pnode_mask;
361
362 return uv_gpa_to_gnode(gpa) & n_mask;
363} 546}
364 547
365/* gpa -> node offset*/ 548/* gpa -> node offset */
366static inline unsigned long uv_gpa_to_offset(unsigned long gpa) 549static inline unsigned long uv_gpa_to_offset(unsigned long gpa)
367{ 550{
368 return (gpa << uv_hub_info->m_shift) >> uv_hub_info->m_shift; 551 unsigned int m_shift = uv_hub_info->m_shift;
552
553 if (m_shift)
554 return (gpa << m_shift) >> m_shift;
555
556 return (gpa & uv_hub_info->gpa_mask) - uv_gam_range_base(gpa);
557}
558
559/* Convert socket to node */
560static inline int _uv_socket_to_node(int socket, unsigned short *s2nid)
561{
562 return s2nid ? s2nid[socket - uv_hub_info->min_socket] : socket;
563}
564
565static inline int uv_socket_to_node(int socket)
566{
567 return _uv_socket_to_node(socket, uv_hub_info->socket_to_node);
369} 568}
370 569
371/* pnode, offset --> socket virtual */ 570/* pnode, offset --> socket virtual */
372static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset) 571static inline void *uv_pnode_offset_to_vaddr(int pnode, unsigned long offset)
373{ 572{
374 return __va(((unsigned long)pnode << uv_hub_info->m_val) | offset); 573 unsigned int m_val = uv_hub_info->m_val;
375} 574 unsigned long base;
575 unsigned short sockid, node, *p2s;
376 576
577 if (m_val)
578 return __va(((unsigned long)pnode << m_val) | offset);
377 579
378/* 580 p2s = uv_hub_info->pnode_to_socket;
379 * Extract a PNODE from an APICID (full apicid, not processor subset) 581 sockid = p2s ? p2s[pnode - uv_hub_info->min_pnode] : pnode;
380 */ 582 node = uv_socket_to_node(sockid);
583
584 /* limit address of previous socket is our base, except node 0 is 0 */
585 if (!node)
586 return __va((unsigned long)offset);
587
588 base = (unsigned long)(uv_hub_info->gr_table[node - 1].limit);
589 return __va(base << UV_GAM_RANGE_SHFT | offset);
590}
591
592/* Extract/Convert a PNODE from an APICID (full apicid, not processor subset) */
381static inline int uv_apicid_to_pnode(int apicid) 593static inline int uv_apicid_to_pnode(int apicid)
382{ 594{
383 return (apicid >> uv_hub_info->apic_pnode_shift); 595 int pnode = apicid >> uv_hub_info->apic_pnode_shift;
596 unsigned short *s2pn = uv_hub_info->socket_to_pnode;
597
598 return s2pn ? s2pn[pnode - uv_hub_info->min_socket] : pnode;
384} 599}
385 600
386/* 601/* Convert an apicid to the socket number on the blade */
387 * Convert an apicid to the socket number on the blade
388 */
389static inline int uv_apicid_to_socket(int apicid) 602static inline int uv_apicid_to_socket(int apicid)
390{ 603{
391 if (is_uv1_hub()) 604 if (is_uv1_hub())
@@ -434,16 +647,6 @@ static inline unsigned long uv_read_global_mmr64(int pnode, unsigned long offset
434 return readq(uv_global_mmr64_address(pnode, offset)); 647 return readq(uv_global_mmr64_address(pnode, offset));
435} 648}
436 649
437/*
438 * Global MMR space addresses when referenced by the GRU. (GRU does
439 * NOT use socket addressing).
440 */
441static inline unsigned long uv_global_gru_mmr_address(int pnode, unsigned long offset)
442{
443 return UV_GLOBAL_GRU_MMR_BASE | offset |
444 ((unsigned long)pnode << uv_hub_info->m_val);
445}
446
447static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val) 650static inline void uv_write_global_mmr8(int pnode, unsigned long offset, unsigned char val)
448{ 651{
449 writeb(val, uv_global_mmr64_address(pnode, offset)); 652 writeb(val, uv_global_mmr64_address(pnode, offset));
@@ -483,27 +686,23 @@ static inline void uv_write_local_mmr8(unsigned long offset, unsigned char val)
483 writeb(val, uv_local_mmr_address(offset)); 686 writeb(val, uv_local_mmr_address(offset));
484} 687}
485 688
486/*
487 * Structures and definitions for converting between cpu, node, pnode, and blade
488 * numbers.
489 */
490struct uv_blade_info {
491 unsigned short nr_possible_cpus;
492 unsigned short nr_online_cpus;
493 unsigned short pnode;
494 short memory_nid;
495 spinlock_t nmi_lock; /* obsolete, see uv_hub_nmi */
496 unsigned long nmi_count; /* obsolete, see uv_hub_nmi */
497};
498extern struct uv_blade_info *uv_blade_info;
499extern short *uv_node_to_blade;
500extern short *uv_cpu_to_blade;
501extern short uv_possible_blades;
502
503/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */ 689/* Blade-local cpu number of current cpu. Numbered 0 .. <# cpus on the blade> */
504static inline int uv_blade_processor_id(void) 690static inline int uv_blade_processor_id(void)
505{ 691{
506 return uv_hub_info->blade_processor_id; 692 return uv_cpu_info->blade_cpu_id;
693}
694
695/* Blade-local cpu number of cpu N. Numbered 0 .. <# cpus on the blade> */
696static inline int uv_cpu_blade_processor_id(int cpu)
697{
698 return uv_cpu_info_per(cpu)->blade_cpu_id;
699}
700#define _uv_cpu_blade_processor_id 1 /* indicate function available */
701
702/* Blade number to Node number (UV1..UV4 is 1:1) */
703static inline int uv_blade_to_node(int blade)
704{
705 return blade;
507} 706}
508 707
509/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */ 708/* Blade number of current cpu. Numnbered 0 .. <#blades -1> */
@@ -512,55 +711,60 @@ static inline int uv_numa_blade_id(void)
512 return uv_hub_info->numa_blade_id; 711 return uv_hub_info->numa_blade_id;
513} 712}
514 713
515/* Convert a cpu number to the the UV blade number */ 714/*
516static inline int uv_cpu_to_blade_id(int cpu) 715 * Convert linux node number to the UV blade number.
716 * .. Currently for UV1 thru UV4 the node and the blade are identical.
717 * .. If this changes then you MUST check references to this function!
718 */
719static inline int uv_node_to_blade_id(int nid)
517{ 720{
518 return uv_cpu_to_blade[cpu]; 721 return nid;
519} 722}
520 723
521/* Convert linux node number to the UV blade number */ 724/* Convert a cpu number to the the UV blade number */
522static inline int uv_node_to_blade_id(int nid) 725static inline int uv_cpu_to_blade_id(int cpu)
523{ 726{
524 return uv_node_to_blade[nid]; 727 return uv_node_to_blade_id(cpu_to_node(cpu));
525} 728}
526 729
527/* Convert a blade id to the PNODE of the blade */ 730/* Convert a blade id to the PNODE of the blade */
528static inline int uv_blade_to_pnode(int bid) 731static inline int uv_blade_to_pnode(int bid)
529{ 732{
530 return uv_blade_info[bid].pnode; 733 return uv_hub_info_list(uv_blade_to_node(bid))->pnode;
531} 734}
532 735
533/* Nid of memory node on blade. -1 if no blade-local memory */ 736/* Nid of memory node on blade. -1 if no blade-local memory */
534static inline int uv_blade_to_memory_nid(int bid) 737static inline int uv_blade_to_memory_nid(int bid)
535{ 738{
536 return uv_blade_info[bid].memory_nid; 739 return uv_hub_info_list(uv_blade_to_node(bid))->memory_nid;
537} 740}
538 741
539/* Determine the number of possible cpus on a blade */ 742/* Determine the number of possible cpus on a blade */
540static inline int uv_blade_nr_possible_cpus(int bid) 743static inline int uv_blade_nr_possible_cpus(int bid)
541{ 744{
542 return uv_blade_info[bid].nr_possible_cpus; 745 return uv_hub_info_list(uv_blade_to_node(bid))->nr_possible_cpus;
543} 746}
544 747
545/* Determine the number of online cpus on a blade */ 748/* Determine the number of online cpus on a blade */
546static inline int uv_blade_nr_online_cpus(int bid) 749static inline int uv_blade_nr_online_cpus(int bid)
547{ 750{
548 return uv_blade_info[bid].nr_online_cpus; 751 return uv_hub_info_list(uv_blade_to_node(bid))->nr_online_cpus;
549} 752}
550 753
551/* Convert a cpu id to the PNODE of the blade containing the cpu */ 754/* Convert a cpu id to the PNODE of the blade containing the cpu */
552static inline int uv_cpu_to_pnode(int cpu) 755static inline int uv_cpu_to_pnode(int cpu)
553{ 756{
554 return uv_blade_info[uv_cpu_to_blade_id(cpu)].pnode; 757 return uv_cpu_hub_info(cpu)->pnode;
555} 758}
556 759
557/* Convert a linux node number to the PNODE of the blade */ 760/* Convert a linux node number to the PNODE of the blade */
558static inline int uv_node_to_pnode(int nid) 761static inline int uv_node_to_pnode(int nid)
559{ 762{
560 return uv_blade_info[uv_node_to_blade_id(nid)].pnode; 763 return uv_hub_info_list(nid)->pnode;
561} 764}
562 765
563/* Maximum possible number of blades */ 766/* Maximum possible number of blades */
767extern short uv_possible_blades;
564static inline int uv_num_possible_blades(void) 768static inline int uv_num_possible_blades(void)
565{ 769{
566 return uv_possible_blades; 770 return uv_possible_blades;
@@ -578,9 +782,7 @@ extern void uv_nmi_setup(void);
578/* Newer SMM NMI handler, not present in all systems */ 782/* Newer SMM NMI handler, not present in all systems */
579#define UVH_NMI_MMRX UVH_EVENT_OCCURRED0 783#define UVH_NMI_MMRX UVH_EVENT_OCCURRED0
580#define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS 784#define UVH_NMI_MMRX_CLEAR UVH_EVENT_OCCURRED0_ALIAS
581#define UVH_NMI_MMRX_SHIFT (is_uv1_hub() ? \ 785#define UVH_NMI_MMRX_SHIFT UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT
582 UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT :\
583 UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
584#define UVH_NMI_MMRX_TYPE "EXTIO_INT0" 786#define UVH_NMI_MMRX_TYPE "EXTIO_INT0"
585 787
586/* Non-zero indicates newer SMM NMI handler present */ 788/* Non-zero indicates newer SMM NMI handler present */
@@ -622,9 +824,9 @@ DECLARE_PER_CPU(struct uv_cpu_nmi_s, uv_cpu_nmi);
622/* Update SCIR state */ 824/* Update SCIR state */
623static inline void uv_set_scir_bits(unsigned char value) 825static inline void uv_set_scir_bits(unsigned char value)
624{ 826{
625 if (uv_hub_info->scir.state != value) { 827 if (uv_scir_info->state != value) {
626 uv_hub_info->scir.state = value; 828 uv_scir_info->state = value;
627 uv_write_local_mmr8(uv_hub_info->scir.offset, value); 829 uv_write_local_mmr8(uv_scir_info->offset, value);
628 } 830 }
629} 831}
630 832
@@ -635,10 +837,10 @@ static inline unsigned long uv_scir_offset(int apicid)
635 837
636static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value) 838static inline void uv_set_cpu_scir_bits(int cpu, unsigned char value)
637{ 839{
638 if (uv_cpu_hub_info(cpu)->scir.state != value) { 840 if (uv_cpu_scir_info(cpu)->state != value) {
639 uv_write_global_mmr8(uv_cpu_to_pnode(cpu), 841 uv_write_global_mmr8(uv_cpu_to_pnode(cpu),
640 uv_cpu_hub_info(cpu)->scir.offset, value); 842 uv_cpu_scir_info(cpu)->offset, value);
641 uv_cpu_hub_info(cpu)->scir.state = value; 843 uv_cpu_scir_info(cpu)->state = value;
642 } 844 }
643} 845}
644 846
@@ -666,10 +868,7 @@ static inline void uv_hub_send_ipi(int pnode, int apicid, int vector)
666 868
667/* 869/*
668 * Get the minimum revision number of the hub chips within the partition. 870 * Get the minimum revision number of the hub chips within the partition.
669 * 1 - UV1 rev 1.0 initial silicon 871 * (See UVx_HUB_REVISION_BASE above for specific values.)
670 * 2 - UV1 rev 2.0 production silicon
671 * 3 - UV2 rev 1.0 initial silicon
672 * 5 - UV3 rev 1.0 initial silicon
673 */ 872 */
674static inline int uv_get_min_hub_revision_id(void) 873static inline int uv_get_min_hub_revision_id(void)
675{ 874{
diff --git a/arch/x86/include/asm/uv/uv_mmrs.h b/arch/x86/include/asm/uv/uv_mmrs.h
index ddd8db6b6e70..548d684a7960 100644
--- a/arch/x86/include/asm/uv/uv_mmrs.h
+++ b/arch/x86/include/asm/uv/uv_mmrs.h
@@ -5,7 +5,7 @@
5 * 5 *
6 * SGI UV MMR definitions 6 * SGI UV MMR definitions
7 * 7 *
8 * Copyright (C) 2007-2014 Silicon Graphics, Inc. All rights reserved. 8 * Copyright (C) 2007-2016 Silicon Graphics, Inc. All rights reserved.
9 */ 9 */
10 10
11#ifndef _ASM_X86_UV_UV_MMRS_H 11#ifndef _ASM_X86_UV_UV_MMRS_H
@@ -18,10 +18,11 @@
18 * grouped by architecture types. 18 * grouped by architecture types.
19 * 19 *
20 * UVH - definitions common to all UV hub types. 20 * UVH - definitions common to all UV hub types.
21 * UVXH - definitions common to all UV eXtended hub types (currently 2 & 3). 21 * UVXH - definitions common to all UV eXtended hub types (currently 2, 3, 4).
22 * UV1H - definitions specific to UV type 1 hub. 22 * UV1H - definitions specific to UV type 1 hub.
23 * UV2H - definitions specific to UV type 2 hub. 23 * UV2H - definitions specific to UV type 2 hub.
24 * UV3H - definitions specific to UV type 3 hub. 24 * UV3H - definitions specific to UV type 3 hub.
25 * UV4H - definitions specific to UV type 4 hub.
25 * 26 *
26 * So in general, MMR addresses and structures are identical on all hubs types. 27 * So in general, MMR addresses and structures are identical on all hubs types.
27 * These MMRs are identified as: 28 * These MMRs are identified as:
@@ -32,19 +33,25 @@
32 * } s; 33 * } s;
33 * }; 34 * };
34 * 35 *
35 * If the MMR exists on all hub types but have different addresses: 36 * If the MMR exists on all hub types but have different addresses,
37 * use a conditional operator to define the value at runtime.
36 * #define UV1Hxxx a 38 * #define UV1Hxxx a
37 * #define UV2Hxxx b 39 * #define UV2Hxxx b
38 * #define UV3Hxxx c 40 * #define UV3Hxxx c
41 * #define UV4Hxxx d
39 * #define UVHxxx (is_uv1_hub() ? UV1Hxxx : 42 * #define UVHxxx (is_uv1_hub() ? UV1Hxxx :
40 * (is_uv2_hub() ? UV2Hxxx : 43 * (is_uv2_hub() ? UV2Hxxx :
41 * UV3Hxxx)) 44 * (is_uv3_hub() ? UV3Hxxx :
45 * UV4Hxxx))
42 * 46 *
43 * If the MMR exists on all hub types > 1 but have different addresses: 47 * If the MMR exists on all hub types > 1 but have different addresses, the
48 * variation using "UVX" as the prefix exists.
44 * #define UV2Hxxx b 49 * #define UV2Hxxx b
45 * #define UV3Hxxx c 50 * #define UV3Hxxx c
46 * #define UVXHxxx (is_uv2_hub() ? UV2Hxxx : 51 * #define UV4Hxxx d
47 * UV3Hxxx)) 52 * #define UVHxxx (is_uv2_hub() ? UV2Hxxx :
53 * (is_uv3_hub() ? UV3Hxxx :
54 * UV4Hxxx))
48 * 55 *
49 * union uvh_xxx { 56 * union uvh_xxx {
50 * unsigned long v; 57 * unsigned long v;
@@ -56,6 +63,8 @@
56 * } s2; 63 * } s2;
57 * struct uv3h_xxx_s { # Full UV3 definition (*) 64 * struct uv3h_xxx_s { # Full UV3 definition (*)
58 * } s3; 65 * } s3;
66 * struct uv4h_xxx_s { # Full UV4 definition (*)
67 * } s4;
59 * }; 68 * };
60 * (* - if present and different than the common struct) 69 * (* - if present and different than the common struct)
61 * 70 *
@@ -73,7 +82,7 @@
73 * } sn; 82 * } sn;
74 * }; 83 * };
75 * 84 *
76 * (GEN Flags: mflags_opt= undefs=0 UV23=UVXH) 85 * (GEN Flags: mflags_opt= undefs=function UV234=UVXH)
77 */ 86 */
78 87
79#define UV_MMR_ENABLE (1UL << 63) 88#define UV_MMR_ENABLE (1UL << 63)
@@ -83,20 +92,36 @@
83#define UV2_HUB_PART_NUMBER_X 0x1111 92#define UV2_HUB_PART_NUMBER_X 0x1111
84#define UV3_HUB_PART_NUMBER 0x9578 93#define UV3_HUB_PART_NUMBER 0x9578
85#define UV3_HUB_PART_NUMBER_X 0x4321 94#define UV3_HUB_PART_NUMBER_X 0x4321
95#define UV4_HUB_PART_NUMBER 0x99a1
86 96
87/* Compat: Indicate which UV Hubs are supported. */ 97/* Compat: Indicate which UV Hubs are supported. */
98#define UV1_HUB_IS_SUPPORTED 1
88#define UV2_HUB_IS_SUPPORTED 1 99#define UV2_HUB_IS_SUPPORTED 1
89#define UV3_HUB_IS_SUPPORTED 1 100#define UV3_HUB_IS_SUPPORTED 1
101#define UV4_HUB_IS_SUPPORTED 1
102
103/* Error function to catch undefined references */
104extern unsigned long uv_undefined(char *str);
90 105
91/* ========================================================================= */ 106/* ========================================================================= */
92/* UVH_BAU_DATA_BROADCAST */ 107/* UVH_BAU_DATA_BROADCAST */
93/* ========================================================================= */ 108/* ========================================================================= */
94#define UVH_BAU_DATA_BROADCAST 0x61688UL 109#define UVH_BAU_DATA_BROADCAST 0x61688UL
95#define UVH_BAU_DATA_BROADCAST_32 0x440 110
111#define UV1H_BAU_DATA_BROADCAST_32 0x440
112#define UV2H_BAU_DATA_BROADCAST_32 0x440
113#define UV3H_BAU_DATA_BROADCAST_32 0x440
114#define UV4H_BAU_DATA_BROADCAST_32 0x360
115#define UVH_BAU_DATA_BROADCAST_32 ( \
116 is_uv1_hub() ? UV1H_BAU_DATA_BROADCAST_32 : \
117 is_uv2_hub() ? UV2H_BAU_DATA_BROADCAST_32 : \
118 is_uv3_hub() ? UV3H_BAU_DATA_BROADCAST_32 : \
119 /*is_uv4_hub*/ UV4H_BAU_DATA_BROADCAST_32)
96 120
97#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0 121#define UVH_BAU_DATA_BROADCAST_ENABLE_SHFT 0
98#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL 122#define UVH_BAU_DATA_BROADCAST_ENABLE_MASK 0x0000000000000001UL
99 123
124
100union uvh_bau_data_broadcast_u { 125union uvh_bau_data_broadcast_u {
101 unsigned long v; 126 unsigned long v;
102 struct uvh_bau_data_broadcast_s { 127 struct uvh_bau_data_broadcast_s {
@@ -109,7 +134,16 @@ union uvh_bau_data_broadcast_u {
109/* UVH_BAU_DATA_CONFIG */ 134/* UVH_BAU_DATA_CONFIG */
110/* ========================================================================= */ 135/* ========================================================================= */
111#define UVH_BAU_DATA_CONFIG 0x61680UL 136#define UVH_BAU_DATA_CONFIG 0x61680UL
112#define UVH_BAU_DATA_CONFIG_32 0x438 137
138#define UV1H_BAU_DATA_CONFIG_32 0x438
139#define UV2H_BAU_DATA_CONFIG_32 0x438
140#define UV3H_BAU_DATA_CONFIG_32 0x438
141#define UV4H_BAU_DATA_CONFIG_32 0x358
142#define UVH_BAU_DATA_CONFIG_32 ( \
143 is_uv1_hub() ? UV1H_BAU_DATA_CONFIG_32 : \
144 is_uv2_hub() ? UV2H_BAU_DATA_CONFIG_32 : \
145 is_uv3_hub() ? UV3H_BAU_DATA_CONFIG_32 : \
146 /*is_uv4_hub*/ UV4H_BAU_DATA_CONFIG_32)
113 147
114#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0 148#define UVH_BAU_DATA_CONFIG_VECTOR_SHFT 0
115#define UVH_BAU_DATA_CONFIG_DM_SHFT 8 149#define UVH_BAU_DATA_CONFIG_DM_SHFT 8
@@ -128,6 +162,7 @@ union uvh_bau_data_broadcast_u {
128#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL 162#define UVH_BAU_DATA_CONFIG_M_MASK 0x0000000000010000UL
129#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 163#define UVH_BAU_DATA_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
130 164
165
131union uvh_bau_data_config_u { 166union uvh_bau_data_config_u {
132 unsigned long v; 167 unsigned long v;
133 struct uvh_bau_data_config_s { 168 struct uvh_bau_data_config_s {
@@ -266,7 +301,6 @@ union uvh_bau_data_config_u {
266#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL 301#define UV1H_EVENT_OCCURRED0_BAU_DATA_MASK 0x0080000000000000UL
267#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL 302#define UV1H_EVENT_OCCURRED0_POWER_MANAGEMENT_REQ_MASK 0x0100000000000000UL
268 303
269#define UVXH_EVENT_OCCURRED0_QP_HCERR_SHFT 1
270#define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2 304#define UVXH_EVENT_OCCURRED0_RH_HCERR_SHFT 2
271#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3 305#define UVXH_EVENT_OCCURRED0_LH0_HCERR_SHFT 3
272#define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4 306#define UVXH_EVENT_OCCURRED0_LH1_HCERR_SHFT 4
@@ -275,55 +309,11 @@ union uvh_bau_data_config_u {
275#define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7 309#define UVXH_EVENT_OCCURRED0_NI0_HCERR_SHFT 7
276#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8 310#define UVXH_EVENT_OCCURRED0_NI1_HCERR_SHFT 8
277#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9 311#define UVXH_EVENT_OCCURRED0_LB_AOERR0_SHFT 9
278#define UVXH_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
279#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12 312#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_SHFT 12
280#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13 313#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_SHFT 13
281#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14 314#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_SHFT 14
282#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15 315#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_SHFT 15
283#define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16 316#define UVXH_EVENT_OCCURRED0_XB_AOERR0_SHFT 16
284#define UVXH_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
285#define UVXH_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
286#define UVXH_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
287#define UVXH_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
288#define UVXH_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
289#define UVXH_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
290#define UVXH_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
291#define UVXH_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
292#define UVXH_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
293#define UVXH_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
294#define UVXH_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
295#define UVXH_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
296#define UVXH_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
297#define UVXH_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
298#define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
299#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
300#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
301#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
302#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
303#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
304#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
305#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
306#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
307#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
308#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
309#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
310#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
311#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
312#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
313#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
314#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
315#define UVXH_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
316#define UVXH_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
317#define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
318#define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
319#define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
320#define UVXH_EVENT_OCCURRED0_IPI_INT_SHFT 53
321#define UVXH_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
322#define UVXH_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
323#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
324#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
325#define UVXH_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
326#define UVXH_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
327#define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL 317#define UVXH_EVENT_OCCURRED0_RH_HCERR_MASK 0x0000000000000004UL
328#define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL 318#define UVXH_EVENT_OCCURRED0_LH0_HCERR_MASK 0x0000000000000008UL
329#define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL 319#define UVXH_EVENT_OCCURRED0_LH1_HCERR_MASK 0x0000000000000010UL
@@ -332,54 +322,294 @@ union uvh_bau_data_config_u {
332#define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL 322#define UVXH_EVENT_OCCURRED0_NI0_HCERR_MASK 0x0000000000000080UL
333#define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL 323#define UVXH_EVENT_OCCURRED0_NI1_HCERR_MASK 0x0000000000000100UL
334#define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL 324#define UVXH_EVENT_OCCURRED0_LB_AOERR0_MASK 0x0000000000000200UL
335#define UVXH_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
336#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL 325#define UVXH_EVENT_OCCURRED0_LH0_AOERR0_MASK 0x0000000000001000UL
337#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL 326#define UVXH_EVENT_OCCURRED0_LH1_AOERR0_MASK 0x0000000000002000UL
338#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL 327#define UVXH_EVENT_OCCURRED0_GR0_AOERR0_MASK 0x0000000000004000UL
339#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL 328#define UVXH_EVENT_OCCURRED0_GR1_AOERR0_MASK 0x0000000000008000UL
340#define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL 329#define UVXH_EVENT_OCCURRED0_XB_AOERR0_MASK 0x0000000000010000UL
341#define UVXH_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL 330
342#define UVXH_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL 331#define UV2H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
343#define UVXH_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL 332#define UV2H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
344#define UVXH_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL 333#define UV2H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
345#define UVXH_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL 334#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
346#define UVXH_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL 335#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
347#define UVXH_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL 336#define UV2H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
348#define UVXH_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL 337#define UV2H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
349#define UVXH_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL 338#define UV2H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
350#define UVXH_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL 339#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
351#define UVXH_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL 340#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
352#define UVXH_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL 341#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
353#define UVXH_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL 342#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
354#define UVXH_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL 343#define UV2H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
355#define UVXH_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL 344#define UV2H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
356#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL 345#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
357#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL 346#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
358#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL 347#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
359#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL 348#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
360#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL 349#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
361#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL 350#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
362#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL 351#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
363#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL 352#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
364#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL 353#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
365#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL 354#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
366#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL 355#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
367#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL 356#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
368#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL 357#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
369#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL 358#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
370#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL 359#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
371#define UVXH_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL 360#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
372#define UVXH_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL 361#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
373#define UVXH_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL 362#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
374#define UVXH_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL 363#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
375#define UVXH_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL 364#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
376#define UVXH_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL 365#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
377#define UVXH_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL 366#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
378#define UVXH_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL 367#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
379#define UVXH_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL 368#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
380#define UVXH_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL 369#define UV2H_EVENT_OCCURRED0_IPI_INT_SHFT 53
381#define UVXH_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL 370#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
382#define UVXH_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL 371#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
372#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
373#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
374#define UV2H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
375#define UV2H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
376#define UV2H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
377#define UV2H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
378#define UV2H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
379#define UV2H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
380#define UV2H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
381#define UV2H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
382#define UV2H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
383#define UV2H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
384#define UV2H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
385#define UV2H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
386#define UV2H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
387#define UV2H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
388#define UV2H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
389#define UV2H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
390#define UV2H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
391#define UV2H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
392#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
393#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
394#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
395#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
396#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
397#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
398#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
399#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
400#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
401#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
402#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
403#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
404#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
405#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
406#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
407#define UV2H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
408#define UV2H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
409#define UV2H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
410#define UV2H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
411#define UV2H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
412#define UV2H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
413#define UV2H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
414#define UV2H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
415#define UV2H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
416#define UV2H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
417#define UV2H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
418#define UV2H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
419
420#define UV3H_EVENT_OCCURRED0_QP_HCERR_SHFT 1
421#define UV3H_EVENT_OCCURRED0_QP_AOERR0_SHFT 10
422#define UV3H_EVENT_OCCURRED0_RT_AOERR0_SHFT 17
423#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 18
424#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 19
425#define UV3H_EVENT_OCCURRED0_LB_AOERR1_SHFT 20
426#define UV3H_EVENT_OCCURRED0_QP_AOERR1_SHFT 21
427#define UV3H_EVENT_OCCURRED0_RH_AOERR1_SHFT 22
428#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 23
429#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 24
430#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 25
431#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 26
432#define UV3H_EVENT_OCCURRED0_XB_AOERR1_SHFT 27
433#define UV3H_EVENT_OCCURRED0_RT_AOERR1_SHFT 28
434#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 29
435#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 30
436#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 31
437#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 32
438#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 33
439#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 34
440#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 35
441#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 36
442#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 37
443#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 38
444#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 39
445#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 40
446#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 41
447#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 42
448#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 43
449#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 44
450#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 45
451#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 46
452#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 47
453#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 48
454#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 49
455#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 50
456#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 51
457#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 52
458#define UV3H_EVENT_OCCURRED0_IPI_INT_SHFT 53
459#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 54
460#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 55
461#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 56
462#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 57
463#define UV3H_EVENT_OCCURRED0_PROFILE_INT_SHFT 58
464#define UV3H_EVENT_OCCURRED0_QP_HCERR_MASK 0x0000000000000002UL
465#define UV3H_EVENT_OCCURRED0_QP_AOERR0_MASK 0x0000000000000400UL
466#define UV3H_EVENT_OCCURRED0_RT_AOERR0_MASK 0x0000000000020000UL
467#define UV3H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000040000UL
468#define UV3H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000080000UL
469#define UV3H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000100000UL
470#define UV3H_EVENT_OCCURRED0_QP_AOERR1_MASK 0x0000000000200000UL
471#define UV3H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000000400000UL
472#define UV3H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000000800000UL
473#define UV3H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000001000000UL
474#define UV3H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000002000000UL
475#define UV3H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000004000000UL
476#define UV3H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000008000000UL
477#define UV3H_EVENT_OCCURRED0_RT_AOERR1_MASK 0x0000000010000000UL
478#define UV3H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000020000000UL
479#define UV3H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000000040000000UL
480#define UV3H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000000080000000UL
481#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000000100000000UL
482#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000000200000000UL
483#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000000400000000UL
484#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000000800000000UL
485#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000001000000000UL
486#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000002000000000UL
487#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000004000000000UL
488#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000008000000000UL
489#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000010000000000UL
490#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000020000000000UL
491#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0000040000000000UL
492#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0000080000000000UL
493#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0000100000000000UL
494#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0000200000000000UL
495#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0000400000000000UL
496#define UV3H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0000800000000000UL
497#define UV3H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0001000000000000UL
498#define UV3H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0002000000000000UL
499#define UV3H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0004000000000000UL
500#define UV3H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0008000000000000UL
501#define UV3H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0010000000000000UL
502#define UV3H_EVENT_OCCURRED0_IPI_INT_MASK 0x0020000000000000UL
503#define UV3H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x0040000000000000UL
504#define UV3H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x0080000000000000UL
505#define UV3H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x0100000000000000UL
506#define UV3H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x0200000000000000UL
507#define UV3H_EVENT_OCCURRED0_PROFILE_INT_MASK 0x0400000000000000UL
508
509#define UV4H_EVENT_OCCURRED0_KT_HCERR_SHFT 1
510#define UV4H_EVENT_OCCURRED0_KT_AOERR0_SHFT 10
511#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_SHFT 17
512#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_SHFT 18
513#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_SHFT 19
514#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_SHFT 20
515#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_SHFT 21
516#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_SHFT 22
517#define UV4H_EVENT_OCCURRED0_LB_AOERR1_SHFT 23
518#define UV4H_EVENT_OCCURRED0_KT_AOERR1_SHFT 24
519#define UV4H_EVENT_OCCURRED0_RH_AOERR1_SHFT 25
520#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_SHFT 26
521#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_SHFT 27
522#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_SHFT 28
523#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_SHFT 29
524#define UV4H_EVENT_OCCURRED0_XB_AOERR1_SHFT 30
525#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_SHFT 31
526#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_SHFT 32
527#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_SHFT 33
528#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_SHFT 34
529#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_SHFT 35
530#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_SHFT 36
531#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_SHFT 37
532#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_SHFT 38
533#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_SHFT 39
534#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_SHFT 40
535#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_SHFT 41
536#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_SHFT 42
537#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_SHFT 43
538#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_SHFT 44
539#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_SHFT 45
540#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_SHFT 46
541#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_SHFT 47
542#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_SHFT 48
543#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_SHFT 49
544#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_SHFT 50
545#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_SHFT 51
546#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_SHFT 52
547#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_SHFT 53
548#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_SHFT 54
549#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_SHFT 55
550#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_SHFT 56
551#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_SHFT 57
552#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_SHFT 58
553#define UV4H_EVENT_OCCURRED0_IPI_INT_SHFT 59
554#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT 60
555#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_SHFT 61
556#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_SHFT 62
557#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_SHFT 63
558#define UV4H_EVENT_OCCURRED0_KT_HCERR_MASK 0x0000000000000002UL
559#define UV4H_EVENT_OCCURRED0_KT_AOERR0_MASK 0x0000000000000400UL
560#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR0_MASK 0x0000000000020000UL
561#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR0_MASK 0x0000000000040000UL
562#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR0_MASK 0x0000000000080000UL
563#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR0_MASK 0x0000000000100000UL
564#define UV4H_EVENT_OCCURRED0_NI0_AOERR0_MASK 0x0000000000200000UL
565#define UV4H_EVENT_OCCURRED0_NI1_AOERR0_MASK 0x0000000000400000UL
566#define UV4H_EVENT_OCCURRED0_LB_AOERR1_MASK 0x0000000000800000UL
567#define UV4H_EVENT_OCCURRED0_KT_AOERR1_MASK 0x0000000001000000UL
568#define UV4H_EVENT_OCCURRED0_RH_AOERR1_MASK 0x0000000002000000UL
569#define UV4H_EVENT_OCCURRED0_LH0_AOERR1_MASK 0x0000000004000000UL
570#define UV4H_EVENT_OCCURRED0_LH1_AOERR1_MASK 0x0000000008000000UL
571#define UV4H_EVENT_OCCURRED0_GR0_AOERR1_MASK 0x0000000010000000UL
572#define UV4H_EVENT_OCCURRED0_GR1_AOERR1_MASK 0x0000000020000000UL
573#define UV4H_EVENT_OCCURRED0_XB_AOERR1_MASK 0x0000000040000000UL
574#define UV4H_EVENT_OCCURRED0_RTQ0_AOERR1_MASK 0x0000000080000000UL
575#define UV4H_EVENT_OCCURRED0_RTQ1_AOERR1_MASK 0x0000000100000000UL
576#define UV4H_EVENT_OCCURRED0_RTQ2_AOERR1_MASK 0x0000000200000000UL
577#define UV4H_EVENT_OCCURRED0_RTQ3_AOERR1_MASK 0x0000000400000000UL
578#define UV4H_EVENT_OCCURRED0_NI0_AOERR1_MASK 0x0000000800000000UL
579#define UV4H_EVENT_OCCURRED0_NI1_AOERR1_MASK 0x0000001000000000UL
580#define UV4H_EVENT_OCCURRED0_SYSTEM_SHUTDOWN_INT_MASK 0x0000002000000000UL
581#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_0_MASK 0x0000004000000000UL
582#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_1_MASK 0x0000008000000000UL
583#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_2_MASK 0x0000010000000000UL
584#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_3_MASK 0x0000020000000000UL
585#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_4_MASK 0x0000040000000000UL
586#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_5_MASK 0x0000080000000000UL
587#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_6_MASK 0x0000100000000000UL
588#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_7_MASK 0x0000200000000000UL
589#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_8_MASK 0x0000400000000000UL
590#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_9_MASK 0x0000800000000000UL
591#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_10_MASK 0x0001000000000000UL
592#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_11_MASK 0x0002000000000000UL
593#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_12_MASK 0x0004000000000000UL
594#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_13_MASK 0x0008000000000000UL
595#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_14_MASK 0x0010000000000000UL
596#define UV4H_EVENT_OCCURRED0_LB_IRQ_INT_15_MASK 0x0020000000000000UL
597#define UV4H_EVENT_OCCURRED0_L1_NMI_INT_MASK 0x0040000000000000UL
598#define UV4H_EVENT_OCCURRED0_STOP_CLOCK_MASK 0x0080000000000000UL
599#define UV4H_EVENT_OCCURRED0_ASIC_TO_L1_MASK 0x0100000000000000UL
600#define UV4H_EVENT_OCCURRED0_L1_TO_ASIC_MASK 0x0200000000000000UL
601#define UV4H_EVENT_OCCURRED0_LA_SEQ_TRIGGER_MASK 0x0400000000000000UL
602#define UV4H_EVENT_OCCURRED0_IPI_INT_MASK 0x0800000000000000UL
603#define UV4H_EVENT_OCCURRED0_EXTIO_INT0_MASK 0x1000000000000000UL
604#define UV4H_EVENT_OCCURRED0_EXTIO_INT1_MASK 0x2000000000000000UL
605#define UV4H_EVENT_OCCURRED0_EXTIO_INT2_MASK 0x4000000000000000UL
606#define UV4H_EVENT_OCCURRED0_EXTIO_INT3_MASK 0x8000000000000000UL
607
608#define UVH_EVENT_OCCURRED0_EXTIO_INT0_SHFT ( \
609 is_uv1_hub() ? UV1H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \
610 is_uv2_hub() ? UV2H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \
611 is_uv3_hub() ? UV3H_EVENT_OCCURRED0_EXTIO_INT0_SHFT : \
612 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED0_EXTIO_INT0_SHFT)
383 613
384union uvh_event_occurred0_u { 614union uvh_event_occurred0_u {
385 unsigned long v; 615 unsigned long v;
@@ -391,7 +621,7 @@ union uvh_event_occurred0_u {
391 } s; 621 } s;
392 struct uvxh_event_occurred0_s { 622 struct uvxh_event_occurred0_s {
393 unsigned long lb_hcerr:1; /* RW */ 623 unsigned long lb_hcerr:1; /* RW */
394 unsigned long qp_hcerr:1; /* RW */ 624 unsigned long rsvd_1:1;
395 unsigned long rh_hcerr:1; /* RW */ 625 unsigned long rh_hcerr:1; /* RW */
396 unsigned long lh0_hcerr:1; /* RW */ 626 unsigned long lh0_hcerr:1; /* RW */
397 unsigned long lh1_hcerr:1; /* RW */ 627 unsigned long lh1_hcerr:1; /* RW */
@@ -400,25 +630,51 @@ union uvh_event_occurred0_u {
400 unsigned long ni0_hcerr:1; /* RW */ 630 unsigned long ni0_hcerr:1; /* RW */
401 unsigned long ni1_hcerr:1; /* RW */ 631 unsigned long ni1_hcerr:1; /* RW */
402 unsigned long lb_aoerr0:1; /* RW */ 632 unsigned long lb_aoerr0:1; /* RW */
403 unsigned long qp_aoerr0:1; /* RW */ 633 unsigned long rsvd_10:1;
404 unsigned long rh_aoerr0:1; /* RW */ 634 unsigned long rh_aoerr0:1; /* RW */
405 unsigned long lh0_aoerr0:1; /* RW */ 635 unsigned long lh0_aoerr0:1; /* RW */
406 unsigned long lh1_aoerr0:1; /* RW */ 636 unsigned long lh1_aoerr0:1; /* RW */
407 unsigned long gr0_aoerr0:1; /* RW */ 637 unsigned long gr0_aoerr0:1; /* RW */
408 unsigned long gr1_aoerr0:1; /* RW */ 638 unsigned long gr1_aoerr0:1; /* RW */
409 unsigned long xb_aoerr0:1; /* RW */ 639 unsigned long xb_aoerr0:1; /* RW */
410 unsigned long rt_aoerr0:1; /* RW */ 640 unsigned long rsvd_17_63:47;
641 } sx;
642 struct uv4h_event_occurred0_s {
643 unsigned long lb_hcerr:1; /* RW */
644 unsigned long kt_hcerr:1; /* RW */
645 unsigned long rh_hcerr:1; /* RW */
646 unsigned long lh0_hcerr:1; /* RW */
647 unsigned long lh1_hcerr:1; /* RW */
648 unsigned long gr0_hcerr:1; /* RW */
649 unsigned long gr1_hcerr:1; /* RW */
650 unsigned long ni0_hcerr:1; /* RW */
651 unsigned long ni1_hcerr:1; /* RW */
652 unsigned long lb_aoerr0:1; /* RW */
653 unsigned long kt_aoerr0:1; /* RW */
654 unsigned long rh_aoerr0:1; /* RW */
655 unsigned long lh0_aoerr0:1; /* RW */
656 unsigned long lh1_aoerr0:1; /* RW */
657 unsigned long gr0_aoerr0:1; /* RW */
658 unsigned long gr1_aoerr0:1; /* RW */
659 unsigned long xb_aoerr0:1; /* RW */
660 unsigned long rtq0_aoerr0:1; /* RW */
661 unsigned long rtq1_aoerr0:1; /* RW */
662 unsigned long rtq2_aoerr0:1; /* RW */
663 unsigned long rtq3_aoerr0:1; /* RW */
411 unsigned long ni0_aoerr0:1; /* RW */ 664 unsigned long ni0_aoerr0:1; /* RW */
412 unsigned long ni1_aoerr0:1; /* RW */ 665 unsigned long ni1_aoerr0:1; /* RW */
413 unsigned long lb_aoerr1:1; /* RW */ 666 unsigned long lb_aoerr1:1; /* RW */
414 unsigned long qp_aoerr1:1; /* RW */ 667 unsigned long kt_aoerr1:1; /* RW */
415 unsigned long rh_aoerr1:1; /* RW */ 668 unsigned long rh_aoerr1:1; /* RW */
416 unsigned long lh0_aoerr1:1; /* RW */ 669 unsigned long lh0_aoerr1:1; /* RW */
417 unsigned long lh1_aoerr1:1; /* RW */ 670 unsigned long lh1_aoerr1:1; /* RW */
418 unsigned long gr0_aoerr1:1; /* RW */ 671 unsigned long gr0_aoerr1:1; /* RW */
419 unsigned long gr1_aoerr1:1; /* RW */ 672 unsigned long gr1_aoerr1:1; /* RW */
420 unsigned long xb_aoerr1:1; /* RW */ 673 unsigned long xb_aoerr1:1; /* RW */
421 unsigned long rt_aoerr1:1; /* RW */ 674 unsigned long rtq0_aoerr1:1; /* RW */
675 unsigned long rtq1_aoerr1:1; /* RW */
676 unsigned long rtq2_aoerr1:1; /* RW */
677 unsigned long rtq3_aoerr1:1; /* RW */
422 unsigned long ni0_aoerr1:1; /* RW */ 678 unsigned long ni0_aoerr1:1; /* RW */
423 unsigned long ni1_aoerr1:1; /* RW */ 679 unsigned long ni1_aoerr1:1; /* RW */
424 unsigned long system_shutdown_int:1; /* RW */ 680 unsigned long system_shutdown_int:1; /* RW */
@@ -448,9 +704,7 @@ union uvh_event_occurred0_u {
448 unsigned long extio_int1:1; /* RW */ 704 unsigned long extio_int1:1; /* RW */
449 unsigned long extio_int2:1; /* RW */ 705 unsigned long extio_int2:1; /* RW */
450 unsigned long extio_int3:1; /* RW */ 706 unsigned long extio_int3:1; /* RW */
451 unsigned long profile_int:1; /* RW */ 707 } s4;
452 unsigned long rsvd_59_63:5;
453 } sx;
454}; 708};
455 709
456/* ========================================================================= */ 710/* ========================================================================= */
@@ -464,11 +718,21 @@ union uvh_event_occurred0_u {
464/* UVH_EXTIO_INT0_BROADCAST */ 718/* UVH_EXTIO_INT0_BROADCAST */
465/* ========================================================================= */ 719/* ========================================================================= */
466#define UVH_EXTIO_INT0_BROADCAST 0x61448UL 720#define UVH_EXTIO_INT0_BROADCAST 0x61448UL
467#define UVH_EXTIO_INT0_BROADCAST_32 0x3f0 721
722#define UV1H_EXTIO_INT0_BROADCAST_32 0x3f0
723#define UV2H_EXTIO_INT0_BROADCAST_32 0x3f0
724#define UV3H_EXTIO_INT0_BROADCAST_32 0x3f0
725#define UV4H_EXTIO_INT0_BROADCAST_32 0x310
726#define UVH_EXTIO_INT0_BROADCAST_32 ( \
727 is_uv1_hub() ? UV1H_EXTIO_INT0_BROADCAST_32 : \
728 is_uv2_hub() ? UV2H_EXTIO_INT0_BROADCAST_32 : \
729 is_uv3_hub() ? UV3H_EXTIO_INT0_BROADCAST_32 : \
730 /*is_uv4_hub*/ UV4H_EXTIO_INT0_BROADCAST_32)
468 731
469#define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0 732#define UVH_EXTIO_INT0_BROADCAST_ENABLE_SHFT 0
470#define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL 733#define UVH_EXTIO_INT0_BROADCAST_ENABLE_MASK 0x0000000000000001UL
471 734
735
472union uvh_extio_int0_broadcast_u { 736union uvh_extio_int0_broadcast_u {
473 unsigned long v; 737 unsigned long v;
474 struct uvh_extio_int0_broadcast_s { 738 struct uvh_extio_int0_broadcast_s {
@@ -499,6 +763,7 @@ union uvh_extio_int0_broadcast_u {
499#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 763#define UVH_GR0_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
500#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 764#define UVH_GR0_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
501 765
766
502union uvh_gr0_tlb_int0_config_u { 767union uvh_gr0_tlb_int0_config_u {
503 unsigned long v; 768 unsigned long v;
504 struct uvh_gr0_tlb_int0_config_s { 769 struct uvh_gr0_tlb_int0_config_s {
@@ -537,6 +802,7 @@ union uvh_gr0_tlb_int0_config_u {
537#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 802#define UVH_GR0_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
538#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 803#define UVH_GR0_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
539 804
805
540union uvh_gr0_tlb_int1_config_u { 806union uvh_gr0_tlb_int1_config_u {
541 unsigned long v; 807 unsigned long v;
542 struct uvh_gr0_tlb_int1_config_s { 808 struct uvh_gr0_tlb_int1_config_s {
@@ -559,19 +825,18 @@ union uvh_gr0_tlb_int1_config_u {
559#define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL 825#define UV1H_GR0_TLB_MMR_CONTROL 0x401080UL
560#define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL 826#define UV2H_GR0_TLB_MMR_CONTROL 0xc01080UL
561#define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL 827#define UV3H_GR0_TLB_MMR_CONTROL 0xc01080UL
562#define UVH_GR0_TLB_MMR_CONTROL \ 828#define UV4H_GR0_TLB_MMR_CONTROL 0x601080UL
563 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \ 829#define UVH_GR0_TLB_MMR_CONTROL ( \
564 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \ 830 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL : \
565 UV3H_GR0_TLB_MMR_CONTROL)) 831 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL : \
832 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL : \
833 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL)
566 834
567#define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 835#define UVH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
568#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
569#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 836#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
570#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 837#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
571#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 838#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
572#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 839#define UVH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
573#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
574#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
575#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 840#define UVH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
576#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 841#define UVH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
577#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 842#define UVH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
@@ -601,14 +866,11 @@ union uvh_gr0_tlb_int1_config_u {
601#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 866#define UV1H_GR0_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
602 867
603#define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0 868#define UVXH_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
604#define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
605#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 869#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
606#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 870#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
607#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 871#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
608#define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31 872#define UVXH_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
609#define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 873#define UVXH_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
610#define UVXH_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
611#define UVXH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
612#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 874#define UVXH_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
613#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 875#define UVXH_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
614#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 876#define UVXH_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
@@ -651,12 +913,45 @@ union uvh_gr0_tlb_int1_config_u {
651#define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 913#define UV3H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
652#define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 914#define UV3H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
653 915
916#define UV4H_GR0_TLB_MMR_CONTROL_INDEX_SHFT 0
917#define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT 13
918#define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
919#define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
920#define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_SHFT 21
921#define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
922#define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_SHFT 31
923#define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
924#define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59
925#define UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL
926#define UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL
927#define UV4H_GR0_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
928#define UV4H_GR0_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
929#define UV4H_GR0_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL
930#define UV4H_GR0_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
931#define UV4H_GR0_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
932#define UV4H_GR0_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
933#define UV4H_GR0_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL
934
935#define UVH_GR0_TLB_MMR_CONTROL_INDEX_MASK ( \
936 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \
937 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \
938 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_INDEX_MASK : \
939 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_INDEX_MASK)
940#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK ( \
941 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \
942 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \
943 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK : \
944 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_MASK)
945#define UVH_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT ( \
946 is_uv1_hub() ? UV1H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \
947 is_uv2_hub() ? UV2H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \
948 is_uv3_hub() ? UV3H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT : \
949 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_CONTROL_MEM_SEL_SHFT)
950
654union uvh_gr0_tlb_mmr_control_u { 951union uvh_gr0_tlb_mmr_control_u {
655 unsigned long v; 952 unsigned long v;
656 struct uvh_gr0_tlb_mmr_control_s { 953 struct uvh_gr0_tlb_mmr_control_s {
657 unsigned long index:12; /* RW */ 954 unsigned long rsvd_0_15:16;
658 unsigned long mem_sel:2; /* RW */
659 unsigned long rsvd_14_15:2;
660 unsigned long auto_valid_en:1; /* RW */ 955 unsigned long auto_valid_en:1; /* RW */
661 unsigned long rsvd_17_19:3; 956 unsigned long rsvd_17_19:3;
662 unsigned long mmr_hash_index_en:1; /* RW */ 957 unsigned long mmr_hash_index_en:1; /* RW */
@@ -690,9 +985,7 @@ union uvh_gr0_tlb_mmr_control_u {
690 unsigned long rsvd_61_63:3; 985 unsigned long rsvd_61_63:3;
691 } s1; 986 } s1;
692 struct uvxh_gr0_tlb_mmr_control_s { 987 struct uvxh_gr0_tlb_mmr_control_s {
693 unsigned long index:12; /* RW */ 988 unsigned long rsvd_0_15:16;
694 unsigned long mem_sel:2; /* RW */
695 unsigned long rsvd_14_15:2;
696 unsigned long auto_valid_en:1; /* RW */ 989 unsigned long auto_valid_en:1; /* RW */
697 unsigned long rsvd_17_19:3; 990 unsigned long rsvd_17_19:3;
698 unsigned long mmr_hash_index_en:1; /* RW */ 991 unsigned long mmr_hash_index_en:1; /* RW */
@@ -703,8 +996,7 @@ union uvh_gr0_tlb_mmr_control_u {
703 unsigned long rsvd_33_47:15; 996 unsigned long rsvd_33_47:15;
704 unsigned long rsvd_48:1; 997 unsigned long rsvd_48:1;
705 unsigned long rsvd_49_51:3; 998 unsigned long rsvd_49_51:3;
706 unsigned long rsvd_52:1; 999 unsigned long rsvd_52_63:12;
707 unsigned long rsvd_53_63:11;
708 } sx; 1000 } sx;
709 struct uv2h_gr0_tlb_mmr_control_s { 1001 struct uv2h_gr0_tlb_mmr_control_s {
710 unsigned long index:12; /* RW */ 1002 unsigned long index:12; /* RW */
@@ -741,6 +1033,24 @@ union uvh_gr0_tlb_mmr_control_u {
741 unsigned long undef_52:1; /* Undefined */ 1033 unsigned long undef_52:1; /* Undefined */
742 unsigned long rsvd_53_63:11; 1034 unsigned long rsvd_53_63:11;
743 } s3; 1035 } s3;
1036 struct uv4h_gr0_tlb_mmr_control_s {
1037 unsigned long index:13; /* RW */
1038 unsigned long mem_sel:2; /* RW */
1039 unsigned long rsvd_15:1;
1040 unsigned long auto_valid_en:1; /* RW */
1041 unsigned long rsvd_17_19:3;
1042 unsigned long mmr_hash_index_en:1; /* RW */
1043 unsigned long ecc_sel:1; /* RW */
1044 unsigned long rsvd_22_29:8;
1045 unsigned long mmr_write:1; /* WP */
1046 unsigned long mmr_read:1; /* WP */
1047 unsigned long mmr_op_done:1; /* RW */
1048 unsigned long rsvd_33_47:15;
1049 unsigned long undef_48:1; /* Undefined */
1050 unsigned long rsvd_49_51:3;
1051 unsigned long rsvd_52_58:7;
1052 unsigned long page_size:5; /* RW */
1053 } s4;
744}; 1054};
745 1055
746/* ========================================================================= */ 1056/* ========================================================================= */
@@ -749,19 +1059,14 @@ union uvh_gr0_tlb_mmr_control_u {
749#define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL 1059#define UV1H_GR0_TLB_MMR_READ_DATA_HI 0x4010a0UL
750#define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1060#define UV2H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
751#define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL 1061#define UV3H_GR0_TLB_MMR_READ_DATA_HI 0xc010a0UL
752#define UVH_GR0_TLB_MMR_READ_DATA_HI \ 1062#define UV4H_GR0_TLB_MMR_READ_DATA_HI 0x6010a0UL
753 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \ 1063#define UVH_GR0_TLB_MMR_READ_DATA_HI ( \
754 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \ 1064 is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_HI : \
755 UV3H_GR0_TLB_MMR_READ_DATA_HI)) 1065 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_HI : \
1066 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_HI : \
1067 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_HI)
756 1068
757#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1069#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
758#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
759#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
760#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
761#define UVH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
762#define UVH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
763#define UVH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
764#define UVH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
765 1070
766#define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1071#define UV1H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
767#define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1072#define UV1H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
@@ -773,13 +1078,6 @@ union uvh_gr0_tlb_mmr_control_u {
773#define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1078#define UV1H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
774 1079
775#define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1080#define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
776#define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
777#define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
778#define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
779#define UVXH_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
780#define UVXH_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
781#define UVXH_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
782#define UVXH_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
783 1081
784#define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1082#define UV2H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
785#define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1083#define UV2H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
@@ -803,15 +1101,24 @@ union uvh_gr0_tlb_mmr_control_u {
803#define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1101#define UV3H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL
804#define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1102#define UV3H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL
805 1103
1104#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
1105#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_SHFT 34
1106#define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_SHFT 49
1107#define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51
1108#define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52
1109#define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53
1110#define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55
1111#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL
1112#define UV4H_GR0_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL
1113#define UV4H_GR0_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL
1114#define UV4H_GR0_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL
1115#define UV4H_GR0_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL
1116#define UV4H_GR0_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL
1117#define UV4H_GR0_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL
1118
1119
806union uvh_gr0_tlb_mmr_read_data_hi_u { 1120union uvh_gr0_tlb_mmr_read_data_hi_u {
807 unsigned long v; 1121 unsigned long v;
808 struct uvh_gr0_tlb_mmr_read_data_hi_s {
809 unsigned long pfn:41; /* RO */
810 unsigned long gaa:2; /* RO */
811 unsigned long dirty:1; /* RO */
812 unsigned long larger:1; /* RO */
813 unsigned long rsvd_45_63:19;
814 } s;
815 struct uv1h_gr0_tlb_mmr_read_data_hi_s { 1122 struct uv1h_gr0_tlb_mmr_read_data_hi_s {
816 unsigned long pfn:41; /* RO */ 1123 unsigned long pfn:41; /* RO */
817 unsigned long gaa:2; /* RO */ 1124 unsigned long gaa:2; /* RO */
@@ -819,13 +1126,6 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
819 unsigned long larger:1; /* RO */ 1126 unsigned long larger:1; /* RO */
820 unsigned long rsvd_45_63:19; 1127 unsigned long rsvd_45_63:19;
821 } s1; 1128 } s1;
822 struct uvxh_gr0_tlb_mmr_read_data_hi_s {
823 unsigned long pfn:41; /* RO */
824 unsigned long gaa:2; /* RO */
825 unsigned long dirty:1; /* RO */
826 unsigned long larger:1; /* RO */
827 unsigned long rsvd_45_63:19;
828 } sx;
829 struct uv2h_gr0_tlb_mmr_read_data_hi_s { 1129 struct uv2h_gr0_tlb_mmr_read_data_hi_s {
830 unsigned long pfn:41; /* RO */ 1130 unsigned long pfn:41; /* RO */
831 unsigned long gaa:2; /* RO */ 1131 unsigned long gaa:2; /* RO */
@@ -842,6 +1142,16 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
842 unsigned long undef_46_54:9; /* Undefined */ 1142 unsigned long undef_46_54:9; /* Undefined */
843 unsigned long way_ecc:9; /* RO */ 1143 unsigned long way_ecc:9; /* RO */
844 } s3; 1144 } s3;
1145 struct uv4h_gr0_tlb_mmr_read_data_hi_s {
1146 unsigned long pfn:34; /* RO */
1147 unsigned long pnid:15; /* RO */
1148 unsigned long gaa:2; /* RO */
1149 unsigned long dirty:1; /* RO */
1150 unsigned long larger:1; /* RO */
1151 unsigned long aa_ext:1; /* RO */
1152 unsigned long undef_54:1; /* Undefined */
1153 unsigned long way_ecc:9; /* RO */
1154 } s4;
845}; 1155};
846 1156
847/* ========================================================================= */ 1157/* ========================================================================= */
@@ -850,10 +1160,12 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
850#define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL 1160#define UV1H_GR0_TLB_MMR_READ_DATA_LO 0x4010a8UL
851#define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1161#define UV2H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
852#define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL 1162#define UV3H_GR0_TLB_MMR_READ_DATA_LO 0xc010a8UL
853#define UVH_GR0_TLB_MMR_READ_DATA_LO \ 1163#define UV4H_GR0_TLB_MMR_READ_DATA_LO 0x6010a8UL
854 (is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \ 1164#define UVH_GR0_TLB_MMR_READ_DATA_LO ( \
855 (is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \ 1165 is_uv1_hub() ? UV1H_GR0_TLB_MMR_READ_DATA_LO : \
856 UV3H_GR0_TLB_MMR_READ_DATA_LO)) 1166 is_uv2_hub() ? UV2H_GR0_TLB_MMR_READ_DATA_LO : \
1167 is_uv3_hub() ? UV3H_GR0_TLB_MMR_READ_DATA_LO : \
1168 /*is_uv4_hub*/ UV4H_GR0_TLB_MMR_READ_DATA_LO)
857 1169
858#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1170#define UVH_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
859#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1171#define UVH_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
@@ -890,6 +1202,14 @@ union uvh_gr0_tlb_mmr_read_data_hi_u {
890#define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1202#define UV3H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
891#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1203#define UV3H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
892 1204
1205#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
1206#define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
1207#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
1208#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
1209#define UV4H_GR0_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
1210#define UV4H_GR0_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
1211
1212
893union uvh_gr0_tlb_mmr_read_data_lo_u { 1213union uvh_gr0_tlb_mmr_read_data_lo_u {
894 unsigned long v; 1214 unsigned long v;
895 struct uvh_gr0_tlb_mmr_read_data_lo_s { 1215 struct uvh_gr0_tlb_mmr_read_data_lo_s {
@@ -917,12 +1237,25 @@ union uvh_gr0_tlb_mmr_read_data_lo_u {
917 unsigned long asid:24; /* RO */ 1237 unsigned long asid:24; /* RO */
918 unsigned long valid:1; /* RO */ 1238 unsigned long valid:1; /* RO */
919 } s3; 1239 } s3;
1240 struct uv4h_gr0_tlb_mmr_read_data_lo_s {
1241 unsigned long vpn:39; /* RO */
1242 unsigned long asid:24; /* RO */
1243 unsigned long valid:1; /* RO */
1244 } s4;
920}; 1245};
921 1246
922/* ========================================================================= */ 1247/* ========================================================================= */
923/* UVH_GR1_TLB_INT0_CONFIG */ 1248/* UVH_GR1_TLB_INT0_CONFIG */
924/* ========================================================================= */ 1249/* ========================================================================= */
925#define UVH_GR1_TLB_INT0_CONFIG 0x61f00UL 1250#define UV1H_GR1_TLB_INT0_CONFIG 0x61f00UL
1251#define UV2H_GR1_TLB_INT0_CONFIG 0x61f00UL
1252#define UV3H_GR1_TLB_INT0_CONFIG 0x61f00UL
1253#define UV4H_GR1_TLB_INT0_CONFIG 0x62100UL
1254#define UVH_GR1_TLB_INT0_CONFIG ( \
1255 is_uv1_hub() ? UV1H_GR1_TLB_INT0_CONFIG : \
1256 is_uv2_hub() ? UV2H_GR1_TLB_INT0_CONFIG : \
1257 is_uv3_hub() ? UV3H_GR1_TLB_INT0_CONFIG : \
1258 /*is_uv4_hub*/ UV4H_GR1_TLB_INT0_CONFIG)
926 1259
927#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0 1260#define UVH_GR1_TLB_INT0_CONFIG_VECTOR_SHFT 0
928#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8 1261#define UVH_GR1_TLB_INT0_CONFIG_DM_SHFT 8
@@ -941,6 +1274,7 @@ union uvh_gr0_tlb_mmr_read_data_lo_u {
941#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL 1274#define UVH_GR1_TLB_INT0_CONFIG_M_MASK 0x0000000000010000UL
942#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1275#define UVH_GR1_TLB_INT0_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
943 1276
1277
944union uvh_gr1_tlb_int0_config_u { 1278union uvh_gr1_tlb_int0_config_u {
945 unsigned long v; 1279 unsigned long v;
946 struct uvh_gr1_tlb_int0_config_s { 1280 struct uvh_gr1_tlb_int0_config_s {
@@ -960,7 +1294,15 @@ union uvh_gr1_tlb_int0_config_u {
960/* ========================================================================= */ 1294/* ========================================================================= */
961/* UVH_GR1_TLB_INT1_CONFIG */ 1295/* UVH_GR1_TLB_INT1_CONFIG */
962/* ========================================================================= */ 1296/* ========================================================================= */
963#define UVH_GR1_TLB_INT1_CONFIG 0x61f40UL 1297#define UV1H_GR1_TLB_INT1_CONFIG 0x61f40UL
1298#define UV2H_GR1_TLB_INT1_CONFIG 0x61f40UL
1299#define UV3H_GR1_TLB_INT1_CONFIG 0x61f40UL
1300#define UV4H_GR1_TLB_INT1_CONFIG 0x62140UL
1301#define UVH_GR1_TLB_INT1_CONFIG ( \
1302 is_uv1_hub() ? UV1H_GR1_TLB_INT1_CONFIG : \
1303 is_uv2_hub() ? UV2H_GR1_TLB_INT1_CONFIG : \
1304 is_uv3_hub() ? UV3H_GR1_TLB_INT1_CONFIG : \
1305 /*is_uv4_hub*/ UV4H_GR1_TLB_INT1_CONFIG)
964 1306
965#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0 1307#define UVH_GR1_TLB_INT1_CONFIG_VECTOR_SHFT 0
966#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8 1308#define UVH_GR1_TLB_INT1_CONFIG_DM_SHFT 8
@@ -979,6 +1321,7 @@ union uvh_gr1_tlb_int0_config_u {
979#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL 1321#define UVH_GR1_TLB_INT1_CONFIG_M_MASK 0x0000000000010000UL
980#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 1322#define UVH_GR1_TLB_INT1_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
981 1323
1324
982union uvh_gr1_tlb_int1_config_u { 1325union uvh_gr1_tlb_int1_config_u {
983 unsigned long v; 1326 unsigned long v;
984 struct uvh_gr1_tlb_int1_config_s { 1327 struct uvh_gr1_tlb_int1_config_s {
@@ -1001,19 +1344,18 @@ union uvh_gr1_tlb_int1_config_u {
1001#define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL 1344#define UV1H_GR1_TLB_MMR_CONTROL 0x801080UL
1002#define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL 1345#define UV2H_GR1_TLB_MMR_CONTROL 0x1001080UL
1003#define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL 1346#define UV3H_GR1_TLB_MMR_CONTROL 0x1001080UL
1004#define UVH_GR1_TLB_MMR_CONTROL \ 1347#define UV4H_GR1_TLB_MMR_CONTROL 0x701080UL
1005 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \ 1348#define UVH_GR1_TLB_MMR_CONTROL ( \
1006 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \ 1349 is_uv1_hub() ? UV1H_GR1_TLB_MMR_CONTROL : \
1007 UV3H_GR1_TLB_MMR_CONTROL)) 1350 is_uv2_hub() ? UV2H_GR1_TLB_MMR_CONTROL : \
1351 is_uv3_hub() ? UV3H_GR1_TLB_MMR_CONTROL : \
1352 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_CONTROL)
1008 1353
1009#define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1354#define UVH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
1010#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
1011#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1355#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
1012#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1356#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1013#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1357#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
1014#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1358#define UVH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
1015#define UVH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
1016#define UVH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
1017#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1359#define UVH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
1018#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1360#define UVH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1019#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1361#define UVH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
@@ -1043,14 +1385,11 @@ union uvh_gr1_tlb_int1_config_u {
1043#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL 1385#define UV1H_GR1_TLB_MMR_CONTROL_MMR_INJ_TLBLRUV_MASK 0x1000000000000000UL
1044 1386
1045#define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0 1387#define UVXH_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
1046#define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 12
1047#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16 1388#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
1048#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20 1389#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1049#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30 1390#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
1050#define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31 1391#define UVXH_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
1051#define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32 1392#define UVXH_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
1052#define UVXH_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000000fffUL
1053#define UVXH_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000003000UL
1054#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL 1393#define UVXH_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
1055#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL 1394#define UVXH_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1056#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL 1395#define UVXH_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
@@ -1093,12 +1432,30 @@ union uvh_gr1_tlb_int1_config_u {
1093#define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL 1432#define UV3H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
1094#define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL 1433#define UV3H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
1095 1434
1435#define UV4H_GR1_TLB_MMR_CONTROL_INDEX_SHFT 0
1436#define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_SHFT 13
1437#define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_SHFT 16
1438#define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_SHFT 20
1439#define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_SHFT 21
1440#define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_SHFT 30
1441#define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_SHFT 31
1442#define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_SHFT 32
1443#define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_SHFT 59
1444#define UV4H_GR1_TLB_MMR_CONTROL_INDEX_MASK 0x0000000000001fffUL
1445#define UV4H_GR1_TLB_MMR_CONTROL_MEM_SEL_MASK 0x0000000000006000UL
1446#define UV4H_GR1_TLB_MMR_CONTROL_AUTO_VALID_EN_MASK 0x0000000000010000UL
1447#define UV4H_GR1_TLB_MMR_CONTROL_MMR_HASH_INDEX_EN_MASK 0x0000000000100000UL
1448#define UV4H_GR1_TLB_MMR_CONTROL_ECC_SEL_MASK 0x0000000000200000UL
1449#define UV4H_GR1_TLB_MMR_CONTROL_MMR_WRITE_MASK 0x0000000040000000UL
1450#define UV4H_GR1_TLB_MMR_CONTROL_MMR_READ_MASK 0x0000000080000000UL
1451#define UV4H_GR1_TLB_MMR_CONTROL_MMR_OP_DONE_MASK 0x0000000100000000UL
1452#define UV4H_GR1_TLB_MMR_CONTROL_PAGE_SIZE_MASK 0xf800000000000000UL
1453
1454
1096union uvh_gr1_tlb_mmr_control_u { 1455union uvh_gr1_tlb_mmr_control_u {
1097 unsigned long v; 1456 unsigned long v;
1098 struct uvh_gr1_tlb_mmr_control_s { 1457 struct uvh_gr1_tlb_mmr_control_s {
1099 unsigned long index:12; /* RW */ 1458 unsigned long rsvd_0_15:16;
1100 unsigned long mem_sel:2; /* RW */
1101 unsigned long rsvd_14_15:2;
1102 unsigned long auto_valid_en:1; /* RW */ 1459 unsigned long auto_valid_en:1; /* RW */
1103 unsigned long rsvd_17_19:3; 1460 unsigned long rsvd_17_19:3;
1104 unsigned long mmr_hash_index_en:1; /* RW */ 1461 unsigned long mmr_hash_index_en:1; /* RW */
@@ -1132,9 +1489,7 @@ union uvh_gr1_tlb_mmr_control_u {
1132 unsigned long rsvd_61_63:3; 1489 unsigned long rsvd_61_63:3;
1133 } s1; 1490 } s1;
1134 struct uvxh_gr1_tlb_mmr_control_s { 1491 struct uvxh_gr1_tlb_mmr_control_s {
1135 unsigned long index:12; /* RW */ 1492 unsigned long rsvd_0_15:16;
1136 unsigned long mem_sel:2; /* RW */
1137 unsigned long rsvd_14_15:2;
1138 unsigned long auto_valid_en:1; /* RW */ 1493 unsigned long auto_valid_en:1; /* RW */
1139 unsigned long rsvd_17_19:3; 1494 unsigned long rsvd_17_19:3;
1140 unsigned long mmr_hash_index_en:1; /* RW */ 1495 unsigned long mmr_hash_index_en:1; /* RW */
@@ -1145,8 +1500,7 @@ union uvh_gr1_tlb_mmr_control_u {
1145 unsigned long rsvd_33_47:15; 1500 unsigned long rsvd_33_47:15;
1146 unsigned long rsvd_48:1; 1501 unsigned long rsvd_48:1;
1147 unsigned long rsvd_49_51:3; 1502 unsigned long rsvd_49_51:3;
1148 unsigned long rsvd_52:1; 1503 unsigned long rsvd_52_63:12;
1149 unsigned long rsvd_53_63:11;
1150 } sx; 1504 } sx;
1151 struct uv2h_gr1_tlb_mmr_control_s { 1505 struct uv2h_gr1_tlb_mmr_control_s {
1152 unsigned long index:12; /* RW */ 1506 unsigned long index:12; /* RW */
@@ -1183,6 +1537,24 @@ union uvh_gr1_tlb_mmr_control_u {
1183 unsigned long undef_52:1; /* Undefined */ 1537 unsigned long undef_52:1; /* Undefined */
1184 unsigned long rsvd_53_63:11; 1538 unsigned long rsvd_53_63:11;
1185 } s3; 1539 } s3;
1540 struct uv4h_gr1_tlb_mmr_control_s {
1541 unsigned long index:13; /* RW */
1542 unsigned long mem_sel:2; /* RW */
1543 unsigned long rsvd_15:1;
1544 unsigned long auto_valid_en:1; /* RW */
1545 unsigned long rsvd_17_19:3;
1546 unsigned long mmr_hash_index_en:1; /* RW */
1547 unsigned long ecc_sel:1; /* RW */
1548 unsigned long rsvd_22_29:8;
1549 unsigned long mmr_write:1; /* WP */
1550 unsigned long mmr_read:1; /* WP */
1551 unsigned long mmr_op_done:1; /* RW */
1552 unsigned long rsvd_33_47:15;
1553 unsigned long undef_48:1; /* Undefined */
1554 unsigned long rsvd_49_51:3;
1555 unsigned long rsvd_52_58:7;
1556 unsigned long page_size:5; /* RW */
1557 } s4;
1186}; 1558};
1187 1559
1188/* ========================================================================= */ 1560/* ========================================================================= */
@@ -1191,19 +1563,14 @@ union uvh_gr1_tlb_mmr_control_u {
1191#define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL 1563#define UV1H_GR1_TLB_MMR_READ_DATA_HI 0x8010a0UL
1192#define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1564#define UV2H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1193#define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL 1565#define UV3H_GR1_TLB_MMR_READ_DATA_HI 0x10010a0UL
1194#define UVH_GR1_TLB_MMR_READ_DATA_HI \ 1566#define UV4H_GR1_TLB_MMR_READ_DATA_HI 0x7010a0UL
1195 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \ 1567#define UVH_GR1_TLB_MMR_READ_DATA_HI ( \
1196 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \ 1568 is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_HI : \
1197 UV3H_GR1_TLB_MMR_READ_DATA_HI)) 1569 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_HI : \
1570 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_HI : \
1571 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_HI)
1198 1572
1199#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1573#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
1200#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
1201#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
1202#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
1203#define UVH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
1204#define UVH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
1205#define UVH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
1206#define UVH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
1207 1574
1208#define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1575#define UV1H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
1209#define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1576#define UV1H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
@@ -1215,13 +1582,6 @@ union uvh_gr1_tlb_mmr_control_u {
1215#define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL 1582#define UV1H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
1216 1583
1217#define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1584#define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
1218#define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
1219#define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 43
1220#define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 44
1221#define UVXH_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x000001ffffffffffUL
1222#define UVXH_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0000060000000000UL
1223#define UVXH_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0000080000000000UL
1224#define UVXH_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0000100000000000UL
1225 1585
1226#define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0 1586#define UV2H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
1227#define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41 1587#define UV2H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 41
@@ -1245,15 +1605,24 @@ union uvh_gr1_tlb_mmr_control_u {
1245#define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL 1605#define UV3H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0000200000000000UL
1246#define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL 1606#define UV3H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL
1247 1607
1608#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_SHFT 0
1609#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_SHFT 34
1610#define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_SHFT 49
1611#define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_SHFT 51
1612#define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_SHFT 52
1613#define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_SHFT 53
1614#define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_SHFT 55
1615#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PFN_MASK 0x00000003ffffffffUL
1616#define UV4H_GR1_TLB_MMR_READ_DATA_HI_PNID_MASK 0x0001fffc00000000UL
1617#define UV4H_GR1_TLB_MMR_READ_DATA_HI_GAA_MASK 0x0006000000000000UL
1618#define UV4H_GR1_TLB_MMR_READ_DATA_HI_DIRTY_MASK 0x0008000000000000UL
1619#define UV4H_GR1_TLB_MMR_READ_DATA_HI_LARGER_MASK 0x0010000000000000UL
1620#define UV4H_GR1_TLB_MMR_READ_DATA_HI_AA_EXT_MASK 0x0020000000000000UL
1621#define UV4H_GR1_TLB_MMR_READ_DATA_HI_WAY_ECC_MASK 0xff80000000000000UL
1622
1623
1248union uvh_gr1_tlb_mmr_read_data_hi_u { 1624union uvh_gr1_tlb_mmr_read_data_hi_u {
1249 unsigned long v; 1625 unsigned long v;
1250 struct uvh_gr1_tlb_mmr_read_data_hi_s {
1251 unsigned long pfn:41; /* RO */
1252 unsigned long gaa:2; /* RO */
1253 unsigned long dirty:1; /* RO */
1254 unsigned long larger:1; /* RO */
1255 unsigned long rsvd_45_63:19;
1256 } s;
1257 struct uv1h_gr1_tlb_mmr_read_data_hi_s { 1626 struct uv1h_gr1_tlb_mmr_read_data_hi_s {
1258 unsigned long pfn:41; /* RO */ 1627 unsigned long pfn:41; /* RO */
1259 unsigned long gaa:2; /* RO */ 1628 unsigned long gaa:2; /* RO */
@@ -1261,13 +1630,6 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
1261 unsigned long larger:1; /* RO */ 1630 unsigned long larger:1; /* RO */
1262 unsigned long rsvd_45_63:19; 1631 unsigned long rsvd_45_63:19;
1263 } s1; 1632 } s1;
1264 struct uvxh_gr1_tlb_mmr_read_data_hi_s {
1265 unsigned long pfn:41; /* RO */
1266 unsigned long gaa:2; /* RO */
1267 unsigned long dirty:1; /* RO */
1268 unsigned long larger:1; /* RO */
1269 unsigned long rsvd_45_63:19;
1270 } sx;
1271 struct uv2h_gr1_tlb_mmr_read_data_hi_s { 1633 struct uv2h_gr1_tlb_mmr_read_data_hi_s {
1272 unsigned long pfn:41; /* RO */ 1634 unsigned long pfn:41; /* RO */
1273 unsigned long gaa:2; /* RO */ 1635 unsigned long gaa:2; /* RO */
@@ -1284,6 +1646,16 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
1284 unsigned long undef_46_54:9; /* Undefined */ 1646 unsigned long undef_46_54:9; /* Undefined */
1285 unsigned long way_ecc:9; /* RO */ 1647 unsigned long way_ecc:9; /* RO */
1286 } s3; 1648 } s3;
1649 struct uv4h_gr1_tlb_mmr_read_data_hi_s {
1650 unsigned long pfn:34; /* RO */
1651 unsigned long pnid:15; /* RO */
1652 unsigned long gaa:2; /* RO */
1653 unsigned long dirty:1; /* RO */
1654 unsigned long larger:1; /* RO */
1655 unsigned long aa_ext:1; /* RO */
1656 unsigned long undef_54:1; /* Undefined */
1657 unsigned long way_ecc:9; /* RO */
1658 } s4;
1287}; 1659};
1288 1660
1289/* ========================================================================= */ 1661/* ========================================================================= */
@@ -1292,10 +1664,12 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
1292#define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL 1664#define UV1H_GR1_TLB_MMR_READ_DATA_LO 0x8010a8UL
1293#define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1665#define UV2H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1294#define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL 1666#define UV3H_GR1_TLB_MMR_READ_DATA_LO 0x10010a8UL
1295#define UVH_GR1_TLB_MMR_READ_DATA_LO \ 1667#define UV4H_GR1_TLB_MMR_READ_DATA_LO 0x7010a8UL
1296 (is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \ 1668#define UVH_GR1_TLB_MMR_READ_DATA_LO ( \
1297 (is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \ 1669 is_uv1_hub() ? UV1H_GR1_TLB_MMR_READ_DATA_LO : \
1298 UV3H_GR1_TLB_MMR_READ_DATA_LO)) 1670 is_uv2_hub() ? UV2H_GR1_TLB_MMR_READ_DATA_LO : \
1671 is_uv3_hub() ? UV3H_GR1_TLB_MMR_READ_DATA_LO : \
1672 /*is_uv4_hub*/ UV4H_GR1_TLB_MMR_READ_DATA_LO)
1299 1673
1300#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0 1674#define UVH_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
1301#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39 1675#define UVH_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
@@ -1332,6 +1706,14 @@ union uvh_gr1_tlb_mmr_read_data_hi_u {
1332#define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL 1706#define UV3H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
1333#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL 1707#define UV3H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
1334 1708
1709#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_SHFT 0
1710#define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_SHFT 39
1711#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_SHFT 63
1712#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VPN_MASK 0x0000007fffffffffUL
1713#define UV4H_GR1_TLB_MMR_READ_DATA_LO_ASID_MASK 0x7fffff8000000000UL
1714#define UV4H_GR1_TLB_MMR_READ_DATA_LO_VALID_MASK 0x8000000000000000UL
1715
1716
1335union uvh_gr1_tlb_mmr_read_data_lo_u { 1717union uvh_gr1_tlb_mmr_read_data_lo_u {
1336 unsigned long v; 1718 unsigned long v;
1337 struct uvh_gr1_tlb_mmr_read_data_lo_s { 1719 struct uvh_gr1_tlb_mmr_read_data_lo_s {
@@ -1359,6 +1741,11 @@ union uvh_gr1_tlb_mmr_read_data_lo_u {
1359 unsigned long asid:24; /* RO */ 1741 unsigned long asid:24; /* RO */
1360 unsigned long valid:1; /* RO */ 1742 unsigned long valid:1; /* RO */
1361 } s3; 1743 } s3;
1744 struct uv4h_gr1_tlb_mmr_read_data_lo_s {
1745 unsigned long vpn:39; /* RO */
1746 unsigned long asid:24; /* RO */
1747 unsigned long valid:1; /* RO */
1748 } s4;
1362}; 1749};
1363 1750
1364/* ========================================================================= */ 1751/* ========================================================================= */
@@ -1369,6 +1756,7 @@ union uvh_gr1_tlb_mmr_read_data_lo_u {
1369#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0 1756#define UVH_INT_CMPB_REAL_TIME_CMPB_SHFT 0
1370#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL 1757#define UVH_INT_CMPB_REAL_TIME_CMPB_MASK 0x00ffffffffffffffUL
1371 1758
1759
1372union uvh_int_cmpb_u { 1760union uvh_int_cmpb_u {
1373 unsigned long v; 1761 unsigned long v;
1374 struct uvh_int_cmpb_s { 1762 struct uvh_int_cmpb_s {
@@ -1382,12 +1770,14 @@ union uvh_int_cmpb_u {
1382/* ========================================================================= */ 1770/* ========================================================================= */
1383#define UVH_INT_CMPC 0x22100UL 1771#define UVH_INT_CMPC 0x22100UL
1384 1772
1773
1385#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0 1774#define UV1H_INT_CMPC_REAL_TIME_CMPC_SHFT 0
1386#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL 1775#define UV1H_INT_CMPC_REAL_TIME_CMPC_MASK 0x00ffffffffffffffUL
1387 1776
1388#define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0 1777#define UVXH_INT_CMPC_REAL_TIME_CMP_2_SHFT 0
1389#define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL 1778#define UVXH_INT_CMPC_REAL_TIME_CMP_2_MASK 0x00ffffffffffffffUL
1390 1779
1780
1391union uvh_int_cmpc_u { 1781union uvh_int_cmpc_u {
1392 unsigned long v; 1782 unsigned long v;
1393 struct uvh_int_cmpc_s { 1783 struct uvh_int_cmpc_s {
@@ -1401,12 +1791,14 @@ union uvh_int_cmpc_u {
1401/* ========================================================================= */ 1791/* ========================================================================= */
1402#define UVH_INT_CMPD 0x22180UL 1792#define UVH_INT_CMPD 0x22180UL
1403 1793
1794
1404#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0 1795#define UV1H_INT_CMPD_REAL_TIME_CMPD_SHFT 0
1405#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL 1796#define UV1H_INT_CMPD_REAL_TIME_CMPD_MASK 0x00ffffffffffffffUL
1406 1797
1407#define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0 1798#define UVXH_INT_CMPD_REAL_TIME_CMP_3_SHFT 0
1408#define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL 1799#define UVXH_INT_CMPD_REAL_TIME_CMP_3_MASK 0x00ffffffffffffffUL
1409 1800
1801
1410union uvh_int_cmpd_u { 1802union uvh_int_cmpd_u {
1411 unsigned long v; 1803 unsigned long v;
1412 struct uvh_int_cmpd_s { 1804 struct uvh_int_cmpd_s {
@@ -1419,7 +1811,16 @@ union uvh_int_cmpd_u {
1419/* UVH_IPI_INT */ 1811/* UVH_IPI_INT */
1420/* ========================================================================= */ 1812/* ========================================================================= */
1421#define UVH_IPI_INT 0x60500UL 1813#define UVH_IPI_INT 0x60500UL
1422#define UVH_IPI_INT_32 0x348 1814
1815#define UV1H_IPI_INT_32 0x348
1816#define UV2H_IPI_INT_32 0x348
1817#define UV3H_IPI_INT_32 0x348
1818#define UV4H_IPI_INT_32 0x268
1819#define UVH_IPI_INT_32 ( \
1820 is_uv1_hub() ? UV1H_IPI_INT_32 : \
1821 is_uv2_hub() ? UV2H_IPI_INT_32 : \
1822 is_uv3_hub() ? UV3H_IPI_INT_32 : \
1823 /*is_uv4_hub*/ UV4H_IPI_INT_32)
1423 1824
1424#define UVH_IPI_INT_VECTOR_SHFT 0 1825#define UVH_IPI_INT_VECTOR_SHFT 0
1425#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8 1826#define UVH_IPI_INT_DELIVERY_MODE_SHFT 8
@@ -1432,6 +1833,7 @@ union uvh_int_cmpd_u {
1432#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL 1833#define UVH_IPI_INT_APIC_ID_MASK 0x0000ffffffff0000UL
1433#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL 1834#define UVH_IPI_INT_SEND_MASK 0x8000000000000000UL
1434 1835
1836
1435union uvh_ipi_int_u { 1837union uvh_ipi_int_u {
1436 unsigned long v; 1838 unsigned long v;
1437 struct uvh_ipi_int_s { 1839 struct uvh_ipi_int_s {
@@ -1448,103 +1850,269 @@ union uvh_ipi_int_u {
1448/* ========================================================================= */ 1850/* ========================================================================= */
1449/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */ 1851/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST */
1450/* ========================================================================= */ 1852/* ========================================================================= */
1451#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL 1853#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1854#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1855#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST 0x320050UL
1856#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST")
1857#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST ( \
1858 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \
1859 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \
1860 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST : \
1861 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST)
1452#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0 1862#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_32 0x9c0
1453 1863
1454#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4 1864
1455#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49 1865#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1456#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL 1866#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1457#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL 1867#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1868#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1869
1870
1871#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1872#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1873#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1874#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1875
1876#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_SHFT 4
1877#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_SHFT 49
1878#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_ADDRESS_MASK 0x000007fffffffff0UL
1879#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_FIRST_NODE_ID_MASK 0x7ffe000000000000UL
1880
1458 1881
1459union uvh_lb_bau_intd_payload_queue_first_u { 1882union uvh_lb_bau_intd_payload_queue_first_u {
1460 unsigned long v; 1883 unsigned long v;
1461 struct uvh_lb_bau_intd_payload_queue_first_s { 1884 struct uv1h_lb_bau_intd_payload_queue_first_s {
1462 unsigned long rsvd_0_3:4; 1885 unsigned long rsvd_0_3:4;
1463 unsigned long address:39; /* RW */ 1886 unsigned long address:39; /* RW */
1464 unsigned long rsvd_43_48:6; 1887 unsigned long rsvd_43_48:6;
1465 unsigned long node_id:14; /* RW */ 1888 unsigned long node_id:14; /* RW */
1466 unsigned long rsvd_63:1; 1889 unsigned long rsvd_63:1;
1467 } s; 1890 } s1;
1891 struct uv2h_lb_bau_intd_payload_queue_first_s {
1892 unsigned long rsvd_0_3:4;
1893 unsigned long address:39; /* RW */
1894 unsigned long rsvd_43_48:6;
1895 unsigned long node_id:14; /* RW */
1896 unsigned long rsvd_63:1;
1897 } s2;
1898 struct uv3h_lb_bau_intd_payload_queue_first_s {
1899 unsigned long rsvd_0_3:4;
1900 unsigned long address:39; /* RW */
1901 unsigned long rsvd_43_48:6;
1902 unsigned long node_id:14; /* RW */
1903 unsigned long rsvd_63:1;
1904 } s3;
1468}; 1905};
1469 1906
1470/* ========================================================================= */ 1907/* ========================================================================= */
1471/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */ 1908/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST */
1472/* ========================================================================= */ 1909/* ========================================================================= */
1473#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL 1910#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1911#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1912#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST 0x320060UL
1913#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST")
1914#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST ( \
1915 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \
1916 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \
1917 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST : \
1918 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST)
1474#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8 1919#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_32 0x9c8
1475 1920
1476#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4 1921
1477#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL 1922#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1923#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1924
1925
1926#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1927#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1928
1929#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_SHFT 4
1930#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_LAST_ADDRESS_MASK 0x000007fffffffff0UL
1931
1478 1932
1479union uvh_lb_bau_intd_payload_queue_last_u { 1933union uvh_lb_bau_intd_payload_queue_last_u {
1480 unsigned long v; 1934 unsigned long v;
1481 struct uvh_lb_bau_intd_payload_queue_last_s { 1935 struct uv1h_lb_bau_intd_payload_queue_last_s {
1482 unsigned long rsvd_0_3:4; 1936 unsigned long rsvd_0_3:4;
1483 unsigned long address:39; /* RW */ 1937 unsigned long address:39; /* RW */
1484 unsigned long rsvd_43_63:21; 1938 unsigned long rsvd_43_63:21;
1485 } s; 1939 } s1;
1940 struct uv2h_lb_bau_intd_payload_queue_last_s {
1941 unsigned long rsvd_0_3:4;
1942 unsigned long address:39; /* RW */
1943 unsigned long rsvd_43_63:21;
1944 } s2;
1945 struct uv3h_lb_bau_intd_payload_queue_last_s {
1946 unsigned long rsvd_0_3:4;
1947 unsigned long address:39; /* RW */
1948 unsigned long rsvd_43_63:21;
1949 } s3;
1486}; 1950};
1487 1951
1488/* ========================================================================= */ 1952/* ========================================================================= */
1489/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */ 1953/* UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL */
1490/* ========================================================================= */ 1954/* ========================================================================= */
1491#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL 1955#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1956#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1957#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL 0x320070UL
1958#define UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL uv_undefined("UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL")
1959#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL ( \
1960 is_uv1_hub() ? UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \
1961 is_uv2_hub() ? UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \
1962 is_uv3_hub() ? UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL : \
1963 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL)
1492#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0 1964#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_32 0x9d0
1493 1965
1494#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4 1966
1495#define UVH_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL 1967#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1968#define UV1H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1969
1970
1971#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1972#define UV2H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1973
1974#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_SHFT 4
1975#define UV3H_LB_BAU_INTD_PAYLOAD_QUEUE_TAIL_ADDRESS_MASK 0x000007fffffffff0UL
1976
1496 1977
1497union uvh_lb_bau_intd_payload_queue_tail_u { 1978union uvh_lb_bau_intd_payload_queue_tail_u {
1498 unsigned long v; 1979 unsigned long v;
1499 struct uvh_lb_bau_intd_payload_queue_tail_s { 1980 struct uv1h_lb_bau_intd_payload_queue_tail_s {
1500 unsigned long rsvd_0_3:4; 1981 unsigned long rsvd_0_3:4;
1501 unsigned long address:39; /* RW */ 1982 unsigned long address:39; /* RW */
1502 unsigned long rsvd_43_63:21; 1983 unsigned long rsvd_43_63:21;
1503 } s; 1984 } s1;
1985 struct uv2h_lb_bau_intd_payload_queue_tail_s {
1986 unsigned long rsvd_0_3:4;
1987 unsigned long address:39; /* RW */
1988 unsigned long rsvd_43_63:21;
1989 } s2;
1990 struct uv3h_lb_bau_intd_payload_queue_tail_s {
1991 unsigned long rsvd_0_3:4;
1992 unsigned long address:39; /* RW */
1993 unsigned long rsvd_43_63:21;
1994 } s3;
1504}; 1995};
1505 1996
1506/* ========================================================================= */ 1997/* ========================================================================= */
1507/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */ 1998/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE */
1508/* ========================================================================= */ 1999/* ========================================================================= */
1509#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL 2000#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2001#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2002#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE 0x320080UL
2003#define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE")
2004#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE ( \
2005 is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \
2006 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \
2007 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE : \
2008 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE)
1510#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68 2009#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_32 0xa68
1511 2010
1512#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0 2011
1513#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1 2012#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
1514#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2 2013#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
1515#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3 2014#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
1516#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4 2015#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
1517#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5 2016#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
1518#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6 2017#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
1519#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7 2018#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
1520#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8 2019#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
1521#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9 2020#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
1522#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10 2021#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
1523#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11 2022#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
1524#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12 2023#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
1525#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13 2024#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
1526#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14 2025#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
1527#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15 2026#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
1528#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL 2027#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
1529#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL 2028#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
1530#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL 2029#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
1531#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL 2030#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
1532#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL 2031#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
1533#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL 2032#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
1534#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL 2033#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
1535#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL 2034#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
1536#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL 2035#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
1537#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL 2036#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
1538#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL 2037#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
1539#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL 2038#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
1540#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL 2039#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
1541#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL 2040#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
1542#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL 2041#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
1543#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL 2042#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2043#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2044
2045
2046#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2047#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2048#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2049#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2050#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2051#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2052#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2053#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2054#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2055#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2056#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2057#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2058#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2059#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2060#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2061#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2062#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2063#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2064#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2065#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2066#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2067#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2068#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2069#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2070#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2071#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2072#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2073#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2074#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2075#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2076#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2077#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2078
2079#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_SHFT 0
2080#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_SHFT 1
2081#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_SHFT 2
2082#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_SHFT 3
2083#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_SHFT 4
2084#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_SHFT 5
2085#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_SHFT 6
2086#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_SHFT 7
2087#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_SHFT 8
2088#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_SHFT 9
2089#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_SHFT 10
2090#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_SHFT 11
2091#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_SHFT 12
2092#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_SHFT 13
2093#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_SHFT 14
2094#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_SHFT 15
2095#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_0_MASK 0x0000000000000001UL
2096#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_1_MASK 0x0000000000000002UL
2097#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_2_MASK 0x0000000000000004UL
2098#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_3_MASK 0x0000000000000008UL
2099#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_4_MASK 0x0000000000000010UL
2100#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_5_MASK 0x0000000000000020UL
2101#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_6_MASK 0x0000000000000040UL
2102#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_PENDING_7_MASK 0x0000000000000080UL
2103#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_0_MASK 0x0000000000000100UL
2104#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_1_MASK 0x0000000000000200UL
2105#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_2_MASK 0x0000000000000400UL
2106#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_3_MASK 0x0000000000000800UL
2107#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_4_MASK 0x0000000000001000UL
2108#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_5_MASK 0x0000000000002000UL
2109#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_6_MASK 0x0000000000004000UL
2110#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_TIMEOUT_7_MASK 0x0000000000008000UL
2111
1544 2112
1545union uvh_lb_bau_intd_software_acknowledge_u { 2113union uvh_lb_bau_intd_software_acknowledge_u {
1546 unsigned long v; 2114 unsigned long v;
1547 struct uvh_lb_bau_intd_software_acknowledge_s { 2115 struct uv1h_lb_bau_intd_software_acknowledge_s {
1548 unsigned long pending_0:1; /* RW, W1C */ 2116 unsigned long pending_0:1; /* RW, W1C */
1549 unsigned long pending_1:1; /* RW, W1C */ 2117 unsigned long pending_1:1; /* RW, W1C */
1550 unsigned long pending_2:1; /* RW, W1C */ 2118 unsigned long pending_2:1; /* RW, W1C */
@@ -1562,27 +2130,84 @@ union uvh_lb_bau_intd_software_acknowledge_u {
1562 unsigned long timeout_6:1; /* RW, W1C */ 2130 unsigned long timeout_6:1; /* RW, W1C */
1563 unsigned long timeout_7:1; /* RW, W1C */ 2131 unsigned long timeout_7:1; /* RW, W1C */
1564 unsigned long rsvd_16_63:48; 2132 unsigned long rsvd_16_63:48;
1565 } s; 2133 } s1;
2134 struct uv2h_lb_bau_intd_software_acknowledge_s {
2135 unsigned long pending_0:1; /* RW */
2136 unsigned long pending_1:1; /* RW */
2137 unsigned long pending_2:1; /* RW */
2138 unsigned long pending_3:1; /* RW */
2139 unsigned long pending_4:1; /* RW */
2140 unsigned long pending_5:1; /* RW */
2141 unsigned long pending_6:1; /* RW */
2142 unsigned long pending_7:1; /* RW */
2143 unsigned long timeout_0:1; /* RW */
2144 unsigned long timeout_1:1; /* RW */
2145 unsigned long timeout_2:1; /* RW */
2146 unsigned long timeout_3:1; /* RW */
2147 unsigned long timeout_4:1; /* RW */
2148 unsigned long timeout_5:1; /* RW */
2149 unsigned long timeout_6:1; /* RW */
2150 unsigned long timeout_7:1; /* RW */
2151 unsigned long rsvd_16_63:48;
2152 } s2;
2153 struct uv3h_lb_bau_intd_software_acknowledge_s {
2154 unsigned long pending_0:1; /* RW */
2155 unsigned long pending_1:1; /* RW */
2156 unsigned long pending_2:1; /* RW */
2157 unsigned long pending_3:1; /* RW */
2158 unsigned long pending_4:1; /* RW */
2159 unsigned long pending_5:1; /* RW */
2160 unsigned long pending_6:1; /* RW */
2161 unsigned long pending_7:1; /* RW */
2162 unsigned long timeout_0:1; /* RW */
2163 unsigned long timeout_1:1; /* RW */
2164 unsigned long timeout_2:1; /* RW */
2165 unsigned long timeout_3:1; /* RW */
2166 unsigned long timeout_4:1; /* RW */
2167 unsigned long timeout_5:1; /* RW */
2168 unsigned long timeout_6:1; /* RW */
2169 unsigned long timeout_7:1; /* RW */
2170 unsigned long rsvd_16_63:48;
2171 } s3;
1566}; 2172};
1567 2173
1568/* ========================================================================= */ 2174/* ========================================================================= */
1569/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */ 2175/* UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS */
1570/* ========================================================================= */ 2176/* ========================================================================= */
1571#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL 2177#define UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2178#define UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2179#define UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS 0x320088UL
2180#define UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS uv_undefined("UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS")
2181#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS ( \
2182 is_uv1_hub() ? UV1H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \
2183 is_uv2_hub() ? UV2H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \
2184 is_uv3_hub() ? UV3H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS : \
2185 /*is_uv4_hub*/ UV4H_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS)
1572#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70 2186#define UVH_LB_BAU_INTD_SOFTWARE_ACKNOWLEDGE_ALIAS_32 0xa70
1573 2187
1574 2188
1575/* ========================================================================= */ 2189/* ========================================================================= */
1576/* UVH_LB_BAU_MISC_CONTROL */ 2190/* UVH_LB_BAU_MISC_CONTROL */
1577/* ========================================================================= */ 2191/* ========================================================================= */
1578#define UVH_LB_BAU_MISC_CONTROL 0x320170UL
1579#define UV1H_LB_BAU_MISC_CONTROL 0x320170UL 2192#define UV1H_LB_BAU_MISC_CONTROL 0x320170UL
1580#define UV2H_LB_BAU_MISC_CONTROL 0x320170UL 2193#define UV2H_LB_BAU_MISC_CONTROL 0x320170UL
1581#define UV3H_LB_BAU_MISC_CONTROL 0x320170UL 2194#define UV3H_LB_BAU_MISC_CONTROL 0x320170UL
1582#define UVH_LB_BAU_MISC_CONTROL_32 0xa10 2195#define UV4H_LB_BAU_MISC_CONTROL 0xc8170UL
1583#define UV1H_LB_BAU_MISC_CONTROL_32 0x320170UL 2196#define UVH_LB_BAU_MISC_CONTROL ( \
1584#define UV2H_LB_BAU_MISC_CONTROL_32 0x320170UL 2197 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL : \
1585#define UV3H_LB_BAU_MISC_CONTROL_32 0x320170UL 2198 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL : \
2199 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL : \
2200 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL)
2201
2202#define UV1H_LB_BAU_MISC_CONTROL_32 0xa10
2203#define UV2H_LB_BAU_MISC_CONTROL_32 0xa10
2204#define UV3H_LB_BAU_MISC_CONTROL_32 0xa10
2205#define UV4H_LB_BAU_MISC_CONTROL_32 0xa18
2206#define UVH_LB_BAU_MISC_CONTROL_32 ( \
2207 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_32 : \
2208 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_32 : \
2209 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_32 : \
2210 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_32)
1586 2211
1587#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0 2212#define UVH_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
1588#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8 2213#define UVH_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
@@ -1590,8 +2215,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
1590#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2215#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
1591#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2216#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1592#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2217#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1593#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1594#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1595#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2218#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1596#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2219#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1597#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2220#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
@@ -1606,8 +2229,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
1606#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2229#define UVH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1607#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2230#define UVH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1608#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2231#define UVH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1609#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1610#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1611#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2232#define UVH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1612#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2233#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1613#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2234#define UVH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
@@ -1656,8 +2277,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
1656#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10 2277#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
1657#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11 2278#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
1658#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14 2279#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
1659#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT 15
1660#define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT 16
1661#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20 2280#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
1662#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21 2281#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
1663#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22 2282#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
@@ -1679,8 +2298,6 @@ union uvh_lb_bau_intd_software_acknowledge_u {
1679#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL 2298#define UVXH_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
1680#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL 2299#define UVXH_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
1681#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL 2300#define UVXH_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
1682#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK 0x0000000000008000UL
1683#define UVXH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK 0x00000000000f0000UL
1684#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL 2301#define UVXH_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
1685#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL 2302#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
1686#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL 2303#define UVXH_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
@@ -1797,6 +2414,88 @@ union uvh_lb_bau_intd_software_acknowledge_u {
1797#define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL 2414#define UV3H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
1798#define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL 2415#define UV3H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
1799 2416
2417#define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_SHFT 0
2418#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_SHFT 8
2419#define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_SHFT 9
2420#define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_SHFT 10
2421#define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_SHFT 11
2422#define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_SHFT 14
2423#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_SHFT 15
2424#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_SHFT 20
2425#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_SHFT 21
2426#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_SHFT 22
2427#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_SHFT 23
2428#define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_SHFT 24
2429#define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_SHFT 27
2430#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_SHFT 28
2431#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_SHFT 29
2432#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_SHFT 30
2433#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_SHFT 31
2434#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_SHFT 32
2435#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_SHFT 33
2436#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_SHFT 34
2437#define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_SHFT 35
2438#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_SHFT 36
2439#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_SHFT 37
2440#define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_SHFT 38
2441#define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_SHFT 46
2442#define UV4H_LB_BAU_MISC_CONTROL_FUN_SHFT 48
2443#define UV4H_LB_BAU_MISC_CONTROL_REJECTION_DELAY_MASK 0x00000000000000ffUL
2444#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_MASK 0x0000000000000100UL
2445#define UV4H_LB_BAU_MISC_CONTROL_FORCE_BROADCAST_MASK 0x0000000000000200UL
2446#define UV4H_LB_BAU_MISC_CONTROL_FORCE_LOCK_NOP_MASK 0x0000000000000400UL
2447#define UV4H_LB_BAU_MISC_CONTROL_QPI_AGENT_PRESENCE_VECTOR_MASK 0x0000000000003800UL
2448#define UV4H_LB_BAU_MISC_CONTROL_DESCRIPTOR_FETCH_MODE_MASK 0x0000000000004000UL
2449#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_15_19_MASK 0x00000000000f8000UL
2450#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_DUAL_MAPPING_MODE_MASK 0x0000000000100000UL
2451#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_DECODE_ENABLE_MASK 0x0000000000200000UL
2452#define UV4H_LB_BAU_MISC_CONTROL_VGA_IO_PORT_16_BIT_DECODE_MASK 0x0000000000400000UL
2453#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_DEST_REGISTRATION_MASK 0x0000000000800000UL
2454#define UV4H_LB_BAU_MISC_CONTROL_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000007000000UL
2455#define UV4H_LB_BAU_MISC_CONTROL_USE_INCOMING_PRIORITY_MASK 0x0000000008000000UL
2456#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_PROGRAMMED_INITIAL_PRIORITY_MASK 0x0000000010000000UL
2457#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_AUTOMATIC_APIC_MODE_SELECTION_MASK 0x0000000020000000UL
2458#define UV4H_LB_BAU_MISC_CONTROL_APIC_MODE_STATUS_MASK 0x0000000040000000UL
2459#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INTERRUPTS_TO_SELF_MASK 0x0000000080000000UL
2460#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_LOCK_BASED_SYSTEM_FLUSH_MASK 0x0000000100000000UL
2461#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_EXTENDED_SB_STATUS_MASK 0x0000000200000000UL
2462#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_INT_PRIO_UDT_TO_SELF_MASK 0x0000000400000000UL
2463#define UV4H_LB_BAU_MISC_CONTROL_USE_LEGACY_DESCRIPTOR_FORMATS_MASK 0x0000000800000000UL
2464#define UV4H_LB_BAU_MISC_CONTROL_SUPPRESS_QUIESCE_MSGS_TO_QPI_MASK 0x0000001000000000UL
2465#define UV4H_LB_BAU_MISC_CONTROL_RESERVED_37_MASK 0x0000002000000000UL
2466#define UV4H_LB_BAU_MISC_CONTROL_THREAD_KILL_TIMEBASE_MASK 0x00003fc000000000UL
2467#define UV4H_LB_BAU_MISC_CONTROL_ADDRESS_INTERLEAVE_SELECT_MASK 0x0000400000000000UL
2468#define UV4H_LB_BAU_MISC_CONTROL_FUN_MASK 0xffff000000000000UL
2469
2470#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK \
2471 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK")
2472#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK ( \
2473 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2474 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2475 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK : \
2476 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_MASK)
2477#define UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT \
2478 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT")
2479#define UVH_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT ( \
2480 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2481 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2482 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT : \
2483 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_ENABLE_INTD_SOFT_ACK_MODE_SHFT)
2484#define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK \
2485 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK")
2486#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK ( \
2487 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2488 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2489 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK : \
2490 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_MASK)
2491#define UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT \
2492 uv_undefined("UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT")
2493#define UVH_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT ( \
2494 is_uv1_hub() ? UV1H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2495 is_uv2_hub() ? UV2H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2496 is_uv3_hub() ? UV3H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT : \
2497 /*is_uv4_hub*/ UV4H_LB_BAU_MISC_CONTROL_INTD_SOFT_ACK_TIMEOUT_PERIOD_SHFT)
2498
1800union uvh_lb_bau_misc_control_u { 2499union uvh_lb_bau_misc_control_u {
1801 unsigned long v; 2500 unsigned long v;
1802 struct uvh_lb_bau_misc_control_s { 2501 struct uvh_lb_bau_misc_control_s {
@@ -1806,8 +2505,7 @@ union uvh_lb_bau_misc_control_u {
1806 unsigned long force_lock_nop:1; /* RW */ 2505 unsigned long force_lock_nop:1; /* RW */
1807 unsigned long qpi_agent_presence_vector:3; /* RW */ 2506 unsigned long qpi_agent_presence_vector:3; /* RW */
1808 unsigned long descriptor_fetch_mode:1; /* RW */ 2507 unsigned long descriptor_fetch_mode:1; /* RW */
1809 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2508 unsigned long rsvd_15_19:5;
1810 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1811 unsigned long enable_dual_mapping_mode:1; /* RW */ 2509 unsigned long enable_dual_mapping_mode:1; /* RW */
1812 unsigned long vga_io_port_decode_enable:1; /* RW */ 2510 unsigned long vga_io_port_decode_enable:1; /* RW */
1813 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2511 unsigned long vga_io_port_16_bit_decode:1; /* RW */
@@ -1844,8 +2542,7 @@ union uvh_lb_bau_misc_control_u {
1844 unsigned long force_lock_nop:1; /* RW */ 2542 unsigned long force_lock_nop:1; /* RW */
1845 unsigned long qpi_agent_presence_vector:3; /* RW */ 2543 unsigned long qpi_agent_presence_vector:3; /* RW */
1846 unsigned long descriptor_fetch_mode:1; /* RW */ 2544 unsigned long descriptor_fetch_mode:1; /* RW */
1847 unsigned long enable_intd_soft_ack_mode:1; /* RW */ 2545 unsigned long rsvd_15_19:5;
1848 unsigned long intd_soft_ack_timeout_period:4; /* RW */
1849 unsigned long enable_dual_mapping_mode:1; /* RW */ 2546 unsigned long enable_dual_mapping_mode:1; /* RW */
1850 unsigned long vga_io_port_decode_enable:1; /* RW */ 2547 unsigned long vga_io_port_decode_enable:1; /* RW */
1851 unsigned long vga_io_port_16_bit_decode:1; /* RW */ 2548 unsigned long vga_io_port_16_bit_decode:1; /* RW */
@@ -1918,13 +2615,59 @@ union uvh_lb_bau_misc_control_u {
1918 unsigned long rsvd_46_47:2; 2615 unsigned long rsvd_46_47:2;
1919 unsigned long fun:16; /* RW */ 2616 unsigned long fun:16; /* RW */
1920 } s3; 2617 } s3;
2618 struct uv4h_lb_bau_misc_control_s {
2619 unsigned long rejection_delay:8; /* RW */
2620 unsigned long apic_mode:1; /* RW */
2621 unsigned long force_broadcast:1; /* RW */
2622 unsigned long force_lock_nop:1; /* RW */
2623 unsigned long qpi_agent_presence_vector:3; /* RW */
2624 unsigned long descriptor_fetch_mode:1; /* RW */
2625 unsigned long rsvd_15_19:5;
2626 unsigned long enable_dual_mapping_mode:1; /* RW */
2627 unsigned long vga_io_port_decode_enable:1; /* RW */
2628 unsigned long vga_io_port_16_bit_decode:1; /* RW */
2629 unsigned long suppress_dest_registration:1; /* RW */
2630 unsigned long programmed_initial_priority:3; /* RW */
2631 unsigned long use_incoming_priority:1; /* RW */
2632 unsigned long enable_programmed_initial_priority:1;/* RW */
2633 unsigned long enable_automatic_apic_mode_selection:1;/* RW */
2634 unsigned long apic_mode_status:1; /* RO */
2635 unsigned long suppress_interrupts_to_self:1; /* RW */
2636 unsigned long enable_lock_based_system_flush:1;/* RW */
2637 unsigned long enable_extended_sb_status:1; /* RW */
2638 unsigned long suppress_int_prio_udt_to_self:1;/* RW */
2639 unsigned long use_legacy_descriptor_formats:1;/* RW */
2640 unsigned long suppress_quiesce_msgs_to_qpi:1; /* RW */
2641 unsigned long rsvd_37:1;
2642 unsigned long thread_kill_timebase:8; /* RW */
2643 unsigned long address_interleave_select:1; /* RW */
2644 unsigned long rsvd_47:1;
2645 unsigned long fun:16; /* RW */
2646 } s4;
1921}; 2647};
1922 2648
1923/* ========================================================================= */ 2649/* ========================================================================= */
1924/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */ 2650/* UVH_LB_BAU_SB_ACTIVATION_CONTROL */
1925/* ========================================================================= */ 2651/* ========================================================================= */
1926#define UVH_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL 2652#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
1927#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8 2653#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2654#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL 0x320020UL
2655#define UV4H_LB_BAU_SB_ACTIVATION_CONTROL 0xc8020UL
2656#define UVH_LB_BAU_SB_ACTIVATION_CONTROL ( \
2657 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL : \
2658 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL : \
2659 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL : \
2660 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL)
2661
2662#define UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2663#define UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2664#define UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9a8
2665#define UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32 0x9c8
2666#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_32 ( \
2667 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \
2668 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \
2669 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_CONTROL_32 : \
2670 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_CONTROL_32)
1928 2671
1929#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0 2672#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INDEX_SHFT 0
1930#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62 2673#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_SHFT 62
@@ -1933,6 +2676,7 @@ union uvh_lb_bau_misc_control_u {
1933#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL 2676#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_PUSH_MASK 0x4000000000000000UL
1934#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL 2677#define UVH_LB_BAU_SB_ACTIVATION_CONTROL_INIT_MASK 0x8000000000000000UL
1935 2678
2679
1936union uvh_lb_bau_sb_activation_control_u { 2680union uvh_lb_bau_sb_activation_control_u {
1937 unsigned long v; 2681 unsigned long v;
1938 struct uvh_lb_bau_sb_activation_control_s { 2682 struct uvh_lb_bau_sb_activation_control_s {
@@ -1946,12 +2690,30 @@ union uvh_lb_bau_sb_activation_control_u {
1946/* ========================================================================= */ 2690/* ========================================================================= */
1947/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */ 2691/* UVH_LB_BAU_SB_ACTIVATION_STATUS_0 */
1948/* ========================================================================= */ 2692/* ========================================================================= */
1949#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL 2693#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
1950#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0 2694#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2695#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 0x320030UL
2696#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0 0xc8030UL
2697#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0 ( \
2698 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0 : \
2699 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0 : \
2700 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0 : \
2701 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0)
2702
2703#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2704#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2705#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9b0
2706#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32 0x9d0
2707#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_32 ( \
2708 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \
2709 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \
2710 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_0_32 : \
2711 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_0_32)
1951 2712
1952#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0 2713#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_SHFT 0
1953#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL 2714#define UVH_LB_BAU_SB_ACTIVATION_STATUS_0_STATUS_MASK 0xffffffffffffffffUL
1954 2715
2716
1955union uvh_lb_bau_sb_activation_status_0_u { 2717union uvh_lb_bau_sb_activation_status_0_u {
1956 unsigned long v; 2718 unsigned long v;
1957 struct uvh_lb_bau_sb_activation_status_0_s { 2719 struct uvh_lb_bau_sb_activation_status_0_s {
@@ -1962,12 +2724,30 @@ union uvh_lb_bau_sb_activation_status_0_u {
1962/* ========================================================================= */ 2724/* ========================================================================= */
1963/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */ 2725/* UVH_LB_BAU_SB_ACTIVATION_STATUS_1 */
1964/* ========================================================================= */ 2726/* ========================================================================= */
1965#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL 2727#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
1966#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8 2728#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2729#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 0x320040UL
2730#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1 0xc8040UL
2731#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1 ( \
2732 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1 : \
2733 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1 : \
2734 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1 : \
2735 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1)
2736
2737#define UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2738#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2739#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9b8
2740#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32 0x9d8
2741#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_32 ( \
2742 is_uv1_hub() ? UV1H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \
2743 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \
2744 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_1_32 : \
2745 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_1_32)
1967 2746
1968#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0 2747#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_SHFT 0
1969#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL 2748#define UVH_LB_BAU_SB_ACTIVATION_STATUS_1_STATUS_MASK 0xffffffffffffffffUL
1970 2749
2750
1971union uvh_lb_bau_sb_activation_status_1_u { 2751union uvh_lb_bau_sb_activation_status_1_u {
1972 unsigned long v; 2752 unsigned long v;
1973 struct uvh_lb_bau_sb_activation_status_1_s { 2753 struct uvh_lb_bau_sb_activation_status_1_s {
@@ -1978,23 +2758,55 @@ union uvh_lb_bau_sb_activation_status_1_u {
1978/* ========================================================================= */ 2758/* ========================================================================= */
1979/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */ 2759/* UVH_LB_BAU_SB_DESCRIPTOR_BASE */
1980/* ========================================================================= */ 2760/* ========================================================================= */
1981#define UVH_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL 2761#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
1982#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0 2762#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2763#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE 0x320010UL
2764#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE 0xc8010UL
2765#define UVH_LB_BAU_SB_DESCRIPTOR_BASE ( \
2766 is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE : \
2767 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE : \
2768 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE : \
2769 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE)
2770
2771#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2772#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2773#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9a0
2774#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32 0x9c0
2775#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_32 ( \
2776 is_uv1_hub() ? UV1H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \
2777 is_uv2_hub() ? UV2H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \
2778 is_uv3_hub() ? UV3H_LB_BAU_SB_DESCRIPTOR_BASE_32 : \
2779 /*is_uv4_hub*/ UV4H_LB_BAU_SB_DESCRIPTOR_BASE_32)
1983 2780
1984#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12 2781#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_SHFT 12
1985#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49 2782#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_SHFT 49
1986#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
1987#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL 2783#define UVH_LB_BAU_SB_DESCRIPTOR_BASE_NODE_ID_MASK 0x7ffe000000000000UL
1988 2784
2785#define UV1H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2786
2787
2788#define UV2H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2789
2790#define UV3H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x000007fffffff000UL
2791
2792#define UV4H_LB_BAU_SB_DESCRIPTOR_BASE_PAGE_ADDRESS_MASK 0x00003ffffffff000UL
2793
2794
1989union uvh_lb_bau_sb_descriptor_base_u { 2795union uvh_lb_bau_sb_descriptor_base_u {
1990 unsigned long v; 2796 unsigned long v;
1991 struct uvh_lb_bau_sb_descriptor_base_s { 2797 struct uvh_lb_bau_sb_descriptor_base_s {
1992 unsigned long rsvd_0_11:12; 2798 unsigned long rsvd_0_11:12;
1993 unsigned long page_address:31; /* RW */ 2799 unsigned long rsvd_12_48:37;
1994 unsigned long rsvd_43_48:6;
1995 unsigned long node_id:14; /* RW */ 2800 unsigned long node_id:14; /* RW */
1996 unsigned long rsvd_63:1; 2801 unsigned long rsvd_63:1;
1997 } s; 2802 } s;
2803 struct uv4h_lb_bau_sb_descriptor_base_s {
2804 unsigned long rsvd_0_11:12;
2805 unsigned long page_address:34; /* RW */
2806 unsigned long rsvd_46_48:3;
2807 unsigned long node_id:14; /* RW */
2808 unsigned long rsvd_63:1;
2809 } s4;
1998}; 2810};
1999 2811
2000/* ========================================================================= */ 2812/* ========================================================================= */
@@ -2004,6 +2816,7 @@ union uvh_lb_bau_sb_descriptor_base_u {
2004#define UV1H_NODE_ID 0x0UL 2816#define UV1H_NODE_ID 0x0UL
2005#define UV2H_NODE_ID 0x0UL 2817#define UV2H_NODE_ID 0x0UL
2006#define UV3H_NODE_ID 0x0UL 2818#define UV3H_NODE_ID 0x0UL
2819#define UV4H_NODE_ID 0x0UL
2007 2820
2008#define UVH_NODE_ID_FORCE1_SHFT 0 2821#define UVH_NODE_ID_FORCE1_SHFT 0
2009#define UVH_NODE_ID_MANUFACTURER_SHFT 1 2822#define UVH_NODE_ID_MANUFACTURER_SHFT 1
@@ -2080,6 +2893,26 @@ union uvh_lb_bau_sb_descriptor_base_u {
2080#define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL 2893#define UV3H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
2081#define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL 2894#define UV3H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
2082 2895
2896#define UV4H_NODE_ID_FORCE1_SHFT 0
2897#define UV4H_NODE_ID_MANUFACTURER_SHFT 1
2898#define UV4H_NODE_ID_PART_NUMBER_SHFT 12
2899#define UV4H_NODE_ID_REVISION_SHFT 28
2900#define UV4H_NODE_ID_NODE_ID_SHFT 32
2901#define UV4H_NODE_ID_ROUTER_SELECT_SHFT 48
2902#define UV4H_NODE_ID_RESERVED_2_SHFT 49
2903#define UV4H_NODE_ID_NODES_PER_BIT_SHFT 50
2904#define UV4H_NODE_ID_NI_PORT_SHFT 57
2905#define UV4H_NODE_ID_FORCE1_MASK 0x0000000000000001UL
2906#define UV4H_NODE_ID_MANUFACTURER_MASK 0x0000000000000ffeUL
2907#define UV4H_NODE_ID_PART_NUMBER_MASK 0x000000000ffff000UL
2908#define UV4H_NODE_ID_REVISION_MASK 0x00000000f0000000UL
2909#define UV4H_NODE_ID_NODE_ID_MASK 0x00007fff00000000UL
2910#define UV4H_NODE_ID_ROUTER_SELECT_MASK 0x0001000000000000UL
2911#define UV4H_NODE_ID_RESERVED_2_MASK 0x0002000000000000UL
2912#define UV4H_NODE_ID_NODES_PER_BIT_MASK 0x01fc000000000000UL
2913#define UV4H_NODE_ID_NI_PORT_MASK 0x3e00000000000000UL
2914
2915
2083union uvh_node_id_u { 2916union uvh_node_id_u {
2084 unsigned long v; 2917 unsigned long v;
2085 struct uvh_node_id_s { 2918 struct uvh_node_id_s {
@@ -2137,17 +2970,40 @@ union uvh_node_id_u {
2137 unsigned long ni_port:5; /* RO */ 2970 unsigned long ni_port:5; /* RO */
2138 unsigned long rsvd_62_63:2; 2971 unsigned long rsvd_62_63:2;
2139 } s3; 2972 } s3;
2973 struct uv4h_node_id_s {
2974 unsigned long force1:1; /* RO */
2975 unsigned long manufacturer:11; /* RO */
2976 unsigned long part_number:16; /* RO */
2977 unsigned long revision:4; /* RO */
2978 unsigned long node_id:15; /* RW */
2979 unsigned long rsvd_47:1;
2980 unsigned long router_select:1; /* RO */
2981 unsigned long rsvd_49:1;
2982 unsigned long nodes_per_bit:7; /* RO */
2983 unsigned long ni_port:5; /* RO */
2984 unsigned long rsvd_62_63:2;
2985 } s4;
2140}; 2986};
2141 2987
2142/* ========================================================================= */ 2988/* ========================================================================= */
2143/* UVH_NODE_PRESENT_TABLE */ 2989/* UVH_NODE_PRESENT_TABLE */
2144/* ========================================================================= */ 2990/* ========================================================================= */
2145#define UVH_NODE_PRESENT_TABLE 0x1400UL 2991#define UVH_NODE_PRESENT_TABLE 0x1400UL
2146#define UVH_NODE_PRESENT_TABLE_DEPTH 16 2992
2993#define UV1H_NODE_PRESENT_TABLE_DEPTH 16
2994#define UV2H_NODE_PRESENT_TABLE_DEPTH 16
2995#define UV3H_NODE_PRESENT_TABLE_DEPTH 16
2996#define UV4H_NODE_PRESENT_TABLE_DEPTH 4
2997#define UVH_NODE_PRESENT_TABLE_DEPTH ( \
2998 is_uv1_hub() ? UV1H_NODE_PRESENT_TABLE_DEPTH : \
2999 is_uv2_hub() ? UV2H_NODE_PRESENT_TABLE_DEPTH : \
3000 is_uv3_hub() ? UV3H_NODE_PRESENT_TABLE_DEPTH : \
3001 /*is_uv4_hub*/ UV4H_NODE_PRESENT_TABLE_DEPTH)
2147 3002
2148#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0 3003#define UVH_NODE_PRESENT_TABLE_NODES_SHFT 0
2149#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL 3004#define UVH_NODE_PRESENT_TABLE_NODES_MASK 0xffffffffffffffffUL
2150 3005
3006
2151union uvh_node_present_table_u { 3007union uvh_node_present_table_u {
2152 unsigned long v; 3008 unsigned long v;
2153 struct uvh_node_present_table_s { 3009 struct uvh_node_present_table_s {
@@ -2158,7 +3014,15 @@ union uvh_node_present_table_u {
2158/* ========================================================================= */ 3014/* ========================================================================= */
2159/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */ 3015/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR */
2160/* ========================================================================= */ 3016/* ========================================================================= */
2161#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL 3017#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3018#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3019#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x16000c8UL
3020#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR 0x4800c8UL
3021#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR ( \
3022 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \
3023 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \
3024 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR : \
3025 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR)
2162 3026
2163#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24 3027#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_BASE_SHFT 24
2164#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48 3028#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_SHFT 48
@@ -2167,6 +3031,7 @@ union uvh_node_present_table_u {
2167#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL 3031#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_M_ALIAS_MASK 0x001f000000000000UL
2168#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL 3032#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR_ENABLE_MASK 0x8000000000000000UL
2169 3033
3034
2170union uvh_rh_gam_alias210_overlay_config_0_mmr_u { 3035union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
2171 unsigned long v; 3036 unsigned long v;
2172 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s { 3037 struct uvh_rh_gam_alias210_overlay_config_0_mmr_s {
@@ -2182,7 +3047,15 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
2182/* ========================================================================= */ 3047/* ========================================================================= */
2183/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */ 3048/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR */
2184/* ========================================================================= */ 3049/* ========================================================================= */
2185#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL 3050#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3051#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3052#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x16000d8UL
3053#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR 0x4800d8UL
3054#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR ( \
3055 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \
3056 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \
3057 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR : \
3058 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR)
2186 3059
2187#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24 3060#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_BASE_SHFT 24
2188#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48 3061#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_SHFT 48
@@ -2191,6 +3064,7 @@ union uvh_rh_gam_alias210_overlay_config_0_mmr_u {
2191#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL 3064#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_M_ALIAS_MASK 0x001f000000000000UL
2192#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL 3065#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR_ENABLE_MASK 0x8000000000000000UL
2193 3066
3067
2194union uvh_rh_gam_alias210_overlay_config_1_mmr_u { 3068union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
2195 unsigned long v; 3069 unsigned long v;
2196 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s { 3070 struct uvh_rh_gam_alias210_overlay_config_1_mmr_s {
@@ -2206,7 +3080,15 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
2206/* ========================================================================= */ 3080/* ========================================================================= */
2207/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */ 3081/* UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR */
2208/* ========================================================================= */ 3082/* ========================================================================= */
2209#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL 3083#define UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3084#define UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3085#define UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x16000e8UL
3086#define UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR 0x4800e8UL
3087#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR ( \
3088 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \
3089 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \
3090 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR : \
3091 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR)
2210 3092
2211#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24 3093#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_BASE_SHFT 24
2212#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48 3094#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_SHFT 48
@@ -2215,6 +3097,7 @@ union uvh_rh_gam_alias210_overlay_config_1_mmr_u {
2215#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL 3097#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_M_ALIAS_MASK 0x001f000000000000UL
2216#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL 3098#define UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR_ENABLE_MASK 0x8000000000000000UL
2217 3099
3100
2218union uvh_rh_gam_alias210_overlay_config_2_mmr_u { 3101union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
2219 unsigned long v; 3102 unsigned long v;
2220 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s { 3103 struct uvh_rh_gam_alias210_overlay_config_2_mmr_s {
@@ -2230,11 +3113,20 @@ union uvh_rh_gam_alias210_overlay_config_2_mmr_u {
2230/* ========================================================================= */ 3113/* ========================================================================= */
2231/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */ 3114/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR */
2232/* ========================================================================= */ 3115/* ========================================================================= */
2233#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL 3116#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3117#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3118#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x16000d0UL
3119#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR 0x4800d0UL
3120#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR ( \
3121 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \
3122 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \
3123 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR : \
3124 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR)
2234 3125
2235#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24 3126#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 24
2236#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3127#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_MASK 0x00003fffff000000UL
2237 3128
3129
2238union uvh_rh_gam_alias210_redirect_config_0_mmr_u { 3130union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
2239 unsigned long v; 3131 unsigned long v;
2240 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s { 3132 struct uvh_rh_gam_alias210_redirect_config_0_mmr_s {
@@ -2247,11 +3139,20 @@ union uvh_rh_gam_alias210_redirect_config_0_mmr_u {
2247/* ========================================================================= */ 3139/* ========================================================================= */
2248/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */ 3140/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR */
2249/* ========================================================================= */ 3141/* ========================================================================= */
2250#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL 3142#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3143#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3144#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x16000e0UL
3145#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR 0x4800e0UL
3146#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR ( \
3147 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \
3148 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \
3149 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR : \
3150 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR)
2251 3151
2252#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24 3152#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_SHFT 24
2253#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3153#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR_DEST_BASE_MASK 0x00003fffff000000UL
2254 3154
3155
2255union uvh_rh_gam_alias210_redirect_config_1_mmr_u { 3156union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
2256 unsigned long v; 3157 unsigned long v;
2257 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s { 3158 struct uvh_rh_gam_alias210_redirect_config_1_mmr_s {
@@ -2264,11 +3165,20 @@ union uvh_rh_gam_alias210_redirect_config_1_mmr_u {
2264/* ========================================================================= */ 3165/* ========================================================================= */
2265/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */ 3166/* UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR */
2266/* ========================================================================= */ 3167/* ========================================================================= */
2267#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL 3168#define UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3169#define UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3170#define UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x16000f0UL
3171#define UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR 0x4800f0UL
3172#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR ( \
3173 is_uv1_hub() ? UV1H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \
3174 is_uv2_hub() ? UV2H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \
3175 is_uv3_hub() ? UV3H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR : \
3176 /*is_uv4_hub*/ UV4H_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR)
2268 3177
2269#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24 3178#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_SHFT 24
2270#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL 3179#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR_DEST_BASE_MASK 0x00003fffff000000UL
2271 3180
3181
2272union uvh_rh_gam_alias210_redirect_config_2_mmr_u { 3182union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
2273 unsigned long v; 3183 unsigned long v;
2274 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s { 3184 struct uvh_rh_gam_alias210_redirect_config_2_mmr_s {
@@ -2281,14 +3191,17 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
2281/* ========================================================================= */ 3191/* ========================================================================= */
2282/* UVH_RH_GAM_CONFIG_MMR */ 3192/* UVH_RH_GAM_CONFIG_MMR */
2283/* ========================================================================= */ 3193/* ========================================================================= */
2284#define UVH_RH_GAM_CONFIG_MMR 0x1600000UL
2285#define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL 3194#define UV1H_RH_GAM_CONFIG_MMR 0x1600000UL
2286#define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL 3195#define UV2H_RH_GAM_CONFIG_MMR 0x1600000UL
2287#define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL 3196#define UV3H_RH_GAM_CONFIG_MMR 0x1600000UL
3197#define UV4H_RH_GAM_CONFIG_MMR 0x480000UL
3198#define UVH_RH_GAM_CONFIG_MMR ( \
3199 is_uv1_hub() ? UV1H_RH_GAM_CONFIG_MMR : \
3200 is_uv2_hub() ? UV2H_RH_GAM_CONFIG_MMR : \
3201 is_uv3_hub() ? UV3H_RH_GAM_CONFIG_MMR : \
3202 /*is_uv4_hub*/ UV4H_RH_GAM_CONFIG_MMR)
2288 3203
2289#define UVH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
2290#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3204#define UVH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
2291#define UVH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
2292#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3205#define UVH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
2293 3206
2294#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3207#define UV1H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
@@ -2298,9 +3211,7 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
2298#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3211#define UV1H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
2299#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL 3212#define UV1H_RH_GAM_CONFIG_MMR_MMIOL_CFG_MASK 0x0000000000001000UL
2300 3213
2301#define UVXH_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
2302#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6 3214#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
2303#define UVXH_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
2304#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3215#define UVXH_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
2305 3216
2306#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0 3217#define UV2H_RH_GAM_CONFIG_MMR_M_SKT_SHFT 0
@@ -2313,10 +3224,14 @@ union uvh_rh_gam_alias210_redirect_config_2_mmr_u {
2313#define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL 3224#define UV3H_RH_GAM_CONFIG_MMR_M_SKT_MASK 0x000000000000003fUL
2314#define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL 3225#define UV3H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
2315 3226
3227#define UV4H_RH_GAM_CONFIG_MMR_N_SKT_SHFT 6
3228#define UV4H_RH_GAM_CONFIG_MMR_N_SKT_MASK 0x00000000000003c0UL
3229
3230
2316union uvh_rh_gam_config_mmr_u { 3231union uvh_rh_gam_config_mmr_u {
2317 unsigned long v; 3232 unsigned long v;
2318 struct uvh_rh_gam_config_mmr_s { 3233 struct uvh_rh_gam_config_mmr_s {
2319 unsigned long m_skt:6; /* RW */ 3234 unsigned long rsvd_0_5:6;
2320 unsigned long n_skt:4; /* RW */ 3235 unsigned long n_skt:4; /* RW */
2321 unsigned long rsvd_10_63:54; 3236 unsigned long rsvd_10_63:54;
2322 } s; 3237 } s;
@@ -2328,7 +3243,7 @@ union uvh_rh_gam_config_mmr_u {
2328 unsigned long rsvd_13_63:51; 3243 unsigned long rsvd_13_63:51;
2329 } s1; 3244 } s1;
2330 struct uvxh_rh_gam_config_mmr_s { 3245 struct uvxh_rh_gam_config_mmr_s {
2331 unsigned long m_skt:6; /* RW */ 3246 unsigned long rsvd_0_5:6;
2332 unsigned long n_skt:4; /* RW */ 3247 unsigned long n_skt:4; /* RW */
2333 unsigned long rsvd_10_63:54; 3248 unsigned long rsvd_10_63:54;
2334 } sx; 3249 } sx;
@@ -2342,20 +3257,28 @@ union uvh_rh_gam_config_mmr_u {
2342 unsigned long n_skt:4; /* RW */ 3257 unsigned long n_skt:4; /* RW */
2343 unsigned long rsvd_10_63:54; 3258 unsigned long rsvd_10_63:54;
2344 } s3; 3259 } s3;
3260 struct uv4h_rh_gam_config_mmr_s {
3261 unsigned long rsvd_0_5:6;
3262 unsigned long n_skt:4; /* RW */
3263 unsigned long rsvd_10_63:54;
3264 } s4;
2345}; 3265};
2346 3266
2347/* ========================================================================= */ 3267/* ========================================================================= */
2348/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */ 3268/* UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR */
2349/* ========================================================================= */ 3269/* ========================================================================= */
2350#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
2351#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3270#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
2352#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3271#define UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
2353#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL 3272#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x1600010UL
3273#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR 0x480010UL
3274#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR ( \
3275 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \
3276 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \
3277 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR : \
3278 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR)
2354 3279
2355#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
2356#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3280#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
2357#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3281#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
2358#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
2359#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3282#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
2360#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3283#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2361 3284
@@ -2368,10 +3291,8 @@ union uvh_rh_gam_config_mmr_u {
2368#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3291#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
2369#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3292#define UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2370 3293
2371#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 28
2372#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52 3294#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
2373#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3295#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
2374#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffff0000000UL
2375#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL 3296#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
2376#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3297#define UVXH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2377 3298
@@ -2391,12 +3312,28 @@ union uvh_rh_gam_config_mmr_u {
2391#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL 3312#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_MODE_MASK 0x4000000000000000UL
2392#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3313#define UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2393 3314
3315#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT 26
3316#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_SHFT 52
3317#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3318#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
3319#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_N_GRU_MASK 0x00f0000000000000UL
3320#define UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3321
3322#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK ( \
3323 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \
3324 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \
3325 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK : \
3326 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK)
3327#define UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT ( \
3328 is_uv1_hub() ? UV1H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \
3329 is_uv2_hub() ? UV2H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \
3330 is_uv3_hub() ? UV3H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT : \
3331 /*is_uv4_hub*/ UV4H_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT)
3332
2394union uvh_rh_gam_gru_overlay_config_mmr_u { 3333union uvh_rh_gam_gru_overlay_config_mmr_u {
2395 unsigned long v; 3334 unsigned long v;
2396 struct uvh_rh_gam_gru_overlay_config_mmr_s { 3335 struct uvh_rh_gam_gru_overlay_config_mmr_s {
2397 unsigned long rsvd_0_27:28; 3336 unsigned long rsvd_0_51:52;
2398 unsigned long base:18; /* RW */
2399 unsigned long rsvd_46_51:6;
2400 unsigned long n_gru:4; /* RW */ 3337 unsigned long n_gru:4; /* RW */
2401 unsigned long rsvd_56_62:7; 3338 unsigned long rsvd_56_62:7;
2402 unsigned long enable:1; /* RW */ 3339 unsigned long enable:1; /* RW */
@@ -2412,8 +3349,7 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
2412 unsigned long enable:1; /* RW */ 3349 unsigned long enable:1; /* RW */
2413 } s1; 3350 } s1;
2414 struct uvxh_rh_gam_gru_overlay_config_mmr_s { 3351 struct uvxh_rh_gam_gru_overlay_config_mmr_s {
2415 unsigned long rsvd_0_27:28; 3352 unsigned long rsvd_0_45:46;
2416 unsigned long base:18; /* RW */
2417 unsigned long rsvd_46_51:6; 3353 unsigned long rsvd_46_51:6;
2418 unsigned long n_gru:4; /* RW */ 3354 unsigned long n_gru:4; /* RW */
2419 unsigned long rsvd_56_62:7; 3355 unsigned long rsvd_56_62:7;
@@ -2436,6 +3372,15 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
2436 unsigned long mode:1; /* RW */ 3372 unsigned long mode:1; /* RW */
2437 unsigned long enable:1; /* RW */ 3373 unsigned long enable:1; /* RW */
2438 } s3; 3374 } s3;
3375 struct uv4h_rh_gam_gru_overlay_config_mmr_s {
3376 unsigned long rsvd_0_24:25;
3377 unsigned long undef_25:1; /* Undefined */
3378 unsigned long base:20; /* RW */
3379 unsigned long rsvd_46_51:6;
3380 unsigned long n_gru:4; /* RW */
3381 unsigned long rsvd_56_62:7;
3382 unsigned long enable:1; /* RW */
3383 } s4;
2439}; 3384};
2440 3385
2441/* ========================================================================= */ 3386/* ========================================================================= */
@@ -2443,6 +3388,14 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
2443/* ========================================================================= */ 3388/* ========================================================================= */
2444#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3389#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
2445#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL 3390#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
3391#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3392#define UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR uv_undefined("UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR")
3393#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR ( \
3394 is_uv1_hub() ? UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \
3395 is_uv2_hub() ? UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \
3396 is_uv3_hub() ? UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR : \
3397 /*is_uv4_hub*/ UV4H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR)
3398
2446 3399
2447#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30 3400#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
2448#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3401#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
@@ -2453,6 +3406,7 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
2453#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3406#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
2454#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3407#define UV1H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2455 3408
3409
2456#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27 3410#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 27
2457#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46 3411#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
2458#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52 3412#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
@@ -2462,6 +3416,7 @@ union uvh_rh_gam_gru_overlay_config_mmr_u {
2462#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL 3416#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
2463#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3417#define UV2H_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2464 3418
3419
2465union uvh_rh_gam_mmioh_overlay_config_mmr_u { 3420union uvh_rh_gam_mmioh_overlay_config_mmr_u {
2466 unsigned long v; 3421 unsigned long v;
2467 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s { 3422 struct uv1h_rh_gam_mmioh_overlay_config_mmr_s {
@@ -2485,10 +3440,15 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
2485/* ========================================================================= */ 3440/* ========================================================================= */
2486/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 3441/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
2487/* ========================================================================= */ 3442/* ========================================================================= */
2488#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
2489#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3443#define UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
2490#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3444#define UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
2491#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 3445#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL
3446#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x480028UL
3447#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR ( \
3448 is_uv1_hub() ? UV1H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \
3449 is_uv2_hub() ? UV2H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \
3450 is_uv3_hub() ? UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR : \
3451 /*is_uv4_hub*/ UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR)
2492 3452
2493#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26 3453#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
2494#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63 3454#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
@@ -2517,6 +3477,12 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
2517#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL 3477#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
2518#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL 3478#define UV3H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
2519 3479
3480#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_SHFT 26
3481#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
3482#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003ffffc000000UL
3483#define UV4H_RH_GAM_MMR_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
3484
3485
2520union uvh_rh_gam_mmr_overlay_config_mmr_u { 3486union uvh_rh_gam_mmr_overlay_config_mmr_u {
2521 unsigned long v; 3487 unsigned long v;
2522 struct uvh_rh_gam_mmr_overlay_config_mmr_s { 3488 struct uvh_rh_gam_mmr_overlay_config_mmr_s {
@@ -2550,16 +3516,31 @@ union uvh_rh_gam_mmr_overlay_config_mmr_u {
2550 unsigned long rsvd_46_62:17; 3516 unsigned long rsvd_46_62:17;
2551 unsigned long enable:1; /* RW */ 3517 unsigned long enable:1; /* RW */
2552 } s3; 3518 } s3;
3519 struct uv4h_rh_gam_mmr_overlay_config_mmr_s {
3520 unsigned long rsvd_0_25:26;
3521 unsigned long base:20; /* RW */
3522 unsigned long rsvd_46_62:17;
3523 unsigned long enable:1; /* RW */
3524 } s4;
2553}; 3525};
2554 3526
2555/* ========================================================================= */ 3527/* ========================================================================= */
2556/* UVH_RTC */ 3528/* UVH_RTC */
2557/* ========================================================================= */ 3529/* ========================================================================= */
2558#define UVH_RTC 0x340000UL 3530#define UV1H_RTC 0x340000UL
3531#define UV2H_RTC 0x340000UL
3532#define UV3H_RTC 0x340000UL
3533#define UV4H_RTC 0xe0000UL
3534#define UVH_RTC ( \
3535 is_uv1_hub() ? UV1H_RTC : \
3536 is_uv2_hub() ? UV2H_RTC : \
3537 is_uv3_hub() ? UV3H_RTC : \
3538 /*is_uv4_hub*/ UV4H_RTC)
2559 3539
2560#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0 3540#define UVH_RTC_REAL_TIME_CLOCK_SHFT 0
2561#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL 3541#define UVH_RTC_REAL_TIME_CLOCK_MASK 0x00ffffffffffffffUL
2562 3542
3543
2563union uvh_rtc_u { 3544union uvh_rtc_u {
2564 unsigned long v; 3545 unsigned long v;
2565 struct uvh_rtc_s { 3546 struct uvh_rtc_s {
@@ -2590,6 +3571,7 @@ union uvh_rtc_u {
2590#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL 3571#define UVH_RTC1_INT_CONFIG_M_MASK 0x0000000000010000UL
2591#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL 3572#define UVH_RTC1_INT_CONFIG_APIC_ID_MASK 0xffffffff00000000UL
2592 3573
3574
2593union uvh_rtc1_int_config_u { 3575union uvh_rtc1_int_config_u {
2594 unsigned long v; 3576 unsigned long v;
2595 struct uvh_rtc1_int_config_s { 3577 struct uvh_rtc1_int_config_s {
@@ -2609,12 +3591,30 @@ union uvh_rtc1_int_config_u {
2609/* ========================================================================= */ 3591/* ========================================================================= */
2610/* UVH_SCRATCH5 */ 3592/* UVH_SCRATCH5 */
2611/* ========================================================================= */ 3593/* ========================================================================= */
2612#define UVH_SCRATCH5 0x2d0200UL 3594#define UV1H_SCRATCH5 0x2d0200UL
2613#define UVH_SCRATCH5_32 0x778 3595#define UV2H_SCRATCH5 0x2d0200UL
3596#define UV3H_SCRATCH5 0x2d0200UL
3597#define UV4H_SCRATCH5 0xb0200UL
3598#define UVH_SCRATCH5 ( \
3599 is_uv1_hub() ? UV1H_SCRATCH5 : \
3600 is_uv2_hub() ? UV2H_SCRATCH5 : \
3601 is_uv3_hub() ? UV3H_SCRATCH5 : \
3602 /*is_uv4_hub*/ UV4H_SCRATCH5)
3603
3604#define UV1H_SCRATCH5_32 0x778
3605#define UV2H_SCRATCH5_32 0x778
3606#define UV3H_SCRATCH5_32 0x778
3607#define UV4H_SCRATCH5_32 0x798
3608#define UVH_SCRATCH5_32 ( \
3609 is_uv1_hub() ? UV1H_SCRATCH5_32 : \
3610 is_uv2_hub() ? UV2H_SCRATCH5_32 : \
3611 is_uv3_hub() ? UV3H_SCRATCH5_32 : \
3612 /*is_uv4_hub*/ UV4H_SCRATCH5_32)
2614 3613
2615#define UVH_SCRATCH5_SCRATCH5_SHFT 0 3614#define UVH_SCRATCH5_SCRATCH5_SHFT 0
2616#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL 3615#define UVH_SCRATCH5_SCRATCH5_MASK 0xffffffffffffffffUL
2617 3616
3617
2618union uvh_scratch5_u { 3618union uvh_scratch5_u {
2619 unsigned long v; 3619 unsigned long v;
2620 struct uvh_scratch5_s { 3620 struct uvh_scratch5_s {
@@ -2625,14 +3625,39 @@ union uvh_scratch5_u {
2625/* ========================================================================= */ 3625/* ========================================================================= */
2626/* UVH_SCRATCH5_ALIAS */ 3626/* UVH_SCRATCH5_ALIAS */
2627/* ========================================================================= */ 3627/* ========================================================================= */
2628#define UVH_SCRATCH5_ALIAS 0x2d0208UL 3628#define UV1H_SCRATCH5_ALIAS 0x2d0208UL
2629#define UVH_SCRATCH5_ALIAS_32 0x780 3629#define UV2H_SCRATCH5_ALIAS 0x2d0208UL
3630#define UV3H_SCRATCH5_ALIAS 0x2d0208UL
3631#define UV4H_SCRATCH5_ALIAS 0xb0208UL
3632#define UVH_SCRATCH5_ALIAS ( \
3633 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS : \
3634 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS : \
3635 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS : \
3636 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS)
3637
3638#define UV1H_SCRATCH5_ALIAS_32 0x780
3639#define UV2H_SCRATCH5_ALIAS_32 0x780
3640#define UV3H_SCRATCH5_ALIAS_32 0x780
3641#define UV4H_SCRATCH5_ALIAS_32 0x7a0
3642#define UVH_SCRATCH5_ALIAS_32 ( \
3643 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_32 : \
3644 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_32 : \
3645 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_32 : \
3646 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_32)
2630 3647
2631 3648
2632/* ========================================================================= */ 3649/* ========================================================================= */
2633/* UVH_SCRATCH5_ALIAS_2 */ 3650/* UVH_SCRATCH5_ALIAS_2 */
2634/* ========================================================================= */ 3651/* ========================================================================= */
2635#define UVH_SCRATCH5_ALIAS_2 0x2d0210UL 3652#define UV1H_SCRATCH5_ALIAS_2 0x2d0210UL
3653#define UV2H_SCRATCH5_ALIAS_2 0x2d0210UL
3654#define UV3H_SCRATCH5_ALIAS_2 0x2d0210UL
3655#define UV4H_SCRATCH5_ALIAS_2 0xb0210UL
3656#define UVH_SCRATCH5_ALIAS_2 ( \
3657 is_uv1_hub() ? UV1H_SCRATCH5_ALIAS_2 : \
3658 is_uv2_hub() ? UV2H_SCRATCH5_ALIAS_2 : \
3659 is_uv3_hub() ? UV3H_SCRATCH5_ALIAS_2 : \
3660 /*is_uv4_hub*/ UV4H_SCRATCH5_ALIAS_2)
2636#define UVH_SCRATCH5_ALIAS_2_32 0x788 3661#define UVH_SCRATCH5_ALIAS_2_32 0x788
2637 3662
2638 3663
@@ -2640,76 +3665,255 @@ union uvh_scratch5_u {
2640/* UVXH_EVENT_OCCURRED2 */ 3665/* UVXH_EVENT_OCCURRED2 */
2641/* ========================================================================= */ 3666/* ========================================================================= */
2642#define UVXH_EVENT_OCCURRED2 0x70100UL 3667#define UVXH_EVENT_OCCURRED2 0x70100UL
2643#define UVXH_EVENT_OCCURRED2_32 0xb68 3668
2644 3669#define UV2H_EVENT_OCCURRED2_32 0xb68
2645#define UVXH_EVENT_OCCURRED2_RTC_0_SHFT 0 3670#define UV3H_EVENT_OCCURRED2_32 0xb68
2646#define UVXH_EVENT_OCCURRED2_RTC_1_SHFT 1 3671#define UV4H_EVENT_OCCURRED2_32 0x608
2647#define UVXH_EVENT_OCCURRED2_RTC_2_SHFT 2 3672#define UVH_EVENT_OCCURRED2_32 ( \
2648#define UVXH_EVENT_OCCURRED2_RTC_3_SHFT 3 3673 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_32 : \
2649#define UVXH_EVENT_OCCURRED2_RTC_4_SHFT 4 3674 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_32 : \
2650#define UVXH_EVENT_OCCURRED2_RTC_5_SHFT 5 3675 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_32)
2651#define UVXH_EVENT_OCCURRED2_RTC_6_SHFT 6 3676
2652#define UVXH_EVENT_OCCURRED2_RTC_7_SHFT 7 3677
2653#define UVXH_EVENT_OCCURRED2_RTC_8_SHFT 8 3678#define UV2H_EVENT_OCCURRED2_RTC_0_SHFT 0
2654#define UVXH_EVENT_OCCURRED2_RTC_9_SHFT 9 3679#define UV2H_EVENT_OCCURRED2_RTC_1_SHFT 1
2655#define UVXH_EVENT_OCCURRED2_RTC_10_SHFT 10 3680#define UV2H_EVENT_OCCURRED2_RTC_2_SHFT 2
2656#define UVXH_EVENT_OCCURRED2_RTC_11_SHFT 11 3681#define UV2H_EVENT_OCCURRED2_RTC_3_SHFT 3
2657#define UVXH_EVENT_OCCURRED2_RTC_12_SHFT 12 3682#define UV2H_EVENT_OCCURRED2_RTC_4_SHFT 4
2658#define UVXH_EVENT_OCCURRED2_RTC_13_SHFT 13 3683#define UV2H_EVENT_OCCURRED2_RTC_5_SHFT 5
2659#define UVXH_EVENT_OCCURRED2_RTC_14_SHFT 14 3684#define UV2H_EVENT_OCCURRED2_RTC_6_SHFT 6
2660#define UVXH_EVENT_OCCURRED2_RTC_15_SHFT 15 3685#define UV2H_EVENT_OCCURRED2_RTC_7_SHFT 7
2661#define UVXH_EVENT_OCCURRED2_RTC_16_SHFT 16 3686#define UV2H_EVENT_OCCURRED2_RTC_8_SHFT 8
2662#define UVXH_EVENT_OCCURRED2_RTC_17_SHFT 17 3687#define UV2H_EVENT_OCCURRED2_RTC_9_SHFT 9
2663#define UVXH_EVENT_OCCURRED2_RTC_18_SHFT 18 3688#define UV2H_EVENT_OCCURRED2_RTC_10_SHFT 10
2664#define UVXH_EVENT_OCCURRED2_RTC_19_SHFT 19 3689#define UV2H_EVENT_OCCURRED2_RTC_11_SHFT 11
2665#define UVXH_EVENT_OCCURRED2_RTC_20_SHFT 20 3690#define UV2H_EVENT_OCCURRED2_RTC_12_SHFT 12
2666#define UVXH_EVENT_OCCURRED2_RTC_21_SHFT 21 3691#define UV2H_EVENT_OCCURRED2_RTC_13_SHFT 13
2667#define UVXH_EVENT_OCCURRED2_RTC_22_SHFT 22 3692#define UV2H_EVENT_OCCURRED2_RTC_14_SHFT 14
2668#define UVXH_EVENT_OCCURRED2_RTC_23_SHFT 23 3693#define UV2H_EVENT_OCCURRED2_RTC_15_SHFT 15
2669#define UVXH_EVENT_OCCURRED2_RTC_24_SHFT 24 3694#define UV2H_EVENT_OCCURRED2_RTC_16_SHFT 16
2670#define UVXH_EVENT_OCCURRED2_RTC_25_SHFT 25 3695#define UV2H_EVENT_OCCURRED2_RTC_17_SHFT 17
2671#define UVXH_EVENT_OCCURRED2_RTC_26_SHFT 26 3696#define UV2H_EVENT_OCCURRED2_RTC_18_SHFT 18
2672#define UVXH_EVENT_OCCURRED2_RTC_27_SHFT 27 3697#define UV2H_EVENT_OCCURRED2_RTC_19_SHFT 19
2673#define UVXH_EVENT_OCCURRED2_RTC_28_SHFT 28 3698#define UV2H_EVENT_OCCURRED2_RTC_20_SHFT 20
2674#define UVXH_EVENT_OCCURRED2_RTC_29_SHFT 29 3699#define UV2H_EVENT_OCCURRED2_RTC_21_SHFT 21
2675#define UVXH_EVENT_OCCURRED2_RTC_30_SHFT 30 3700#define UV2H_EVENT_OCCURRED2_RTC_22_SHFT 22
2676#define UVXH_EVENT_OCCURRED2_RTC_31_SHFT 31 3701#define UV2H_EVENT_OCCURRED2_RTC_23_SHFT 23
2677#define UVXH_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL 3702#define UV2H_EVENT_OCCURRED2_RTC_24_SHFT 24
2678#define UVXH_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL 3703#define UV2H_EVENT_OCCURRED2_RTC_25_SHFT 25
2679#define UVXH_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL 3704#define UV2H_EVENT_OCCURRED2_RTC_26_SHFT 26
2680#define UVXH_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL 3705#define UV2H_EVENT_OCCURRED2_RTC_27_SHFT 27
2681#define UVXH_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL 3706#define UV2H_EVENT_OCCURRED2_RTC_28_SHFT 28
2682#define UVXH_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL 3707#define UV2H_EVENT_OCCURRED2_RTC_29_SHFT 29
2683#define UVXH_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL 3708#define UV2H_EVENT_OCCURRED2_RTC_30_SHFT 30
2684#define UVXH_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL 3709#define UV2H_EVENT_OCCURRED2_RTC_31_SHFT 31
2685#define UVXH_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL 3710#define UV2H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
2686#define UVXH_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL 3711#define UV2H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
2687#define UVXH_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL 3712#define UV2H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
2688#define UVXH_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL 3713#define UV2H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
2689#define UVXH_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL 3714#define UV2H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
2690#define UVXH_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL 3715#define UV2H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
2691#define UVXH_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL 3716#define UV2H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
2692#define UVXH_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL 3717#define UV2H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
2693#define UVXH_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL 3718#define UV2H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
2694#define UVXH_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL 3719#define UV2H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
2695#define UVXH_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL 3720#define UV2H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
2696#define UVXH_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL 3721#define UV2H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
2697#define UVXH_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL 3722#define UV2H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
2698#define UVXH_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL 3723#define UV2H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
2699#define UVXH_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL 3724#define UV2H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
2700#define UVXH_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL 3725#define UV2H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
2701#define UVXH_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL 3726#define UV2H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
2702#define UVXH_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL 3727#define UV2H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
2703#define UVXH_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL 3728#define UV2H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
2704#define UVXH_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL 3729#define UV2H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
2705#define UVXH_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL 3730#define UV2H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
2706#define UVXH_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL 3731#define UV2H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
2707#define UVXH_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL 3732#define UV2H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
2708#define UVXH_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL 3733#define UV2H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
2709 3734#define UV2H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
2710union uvxh_event_occurred2_u { 3735#define UV2H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
3736#define UV2H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
3737#define UV2H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
3738#define UV2H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
3739#define UV2H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
3740#define UV2H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
3741#define UV2H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
3742
3743#define UV3H_EVENT_OCCURRED2_RTC_0_SHFT 0
3744#define UV3H_EVENT_OCCURRED2_RTC_1_SHFT 1
3745#define UV3H_EVENT_OCCURRED2_RTC_2_SHFT 2
3746#define UV3H_EVENT_OCCURRED2_RTC_3_SHFT 3
3747#define UV3H_EVENT_OCCURRED2_RTC_4_SHFT 4
3748#define UV3H_EVENT_OCCURRED2_RTC_5_SHFT 5
3749#define UV3H_EVENT_OCCURRED2_RTC_6_SHFT 6
3750#define UV3H_EVENT_OCCURRED2_RTC_7_SHFT 7
3751#define UV3H_EVENT_OCCURRED2_RTC_8_SHFT 8
3752#define UV3H_EVENT_OCCURRED2_RTC_9_SHFT 9
3753#define UV3H_EVENT_OCCURRED2_RTC_10_SHFT 10
3754#define UV3H_EVENT_OCCURRED2_RTC_11_SHFT 11
3755#define UV3H_EVENT_OCCURRED2_RTC_12_SHFT 12
3756#define UV3H_EVENT_OCCURRED2_RTC_13_SHFT 13
3757#define UV3H_EVENT_OCCURRED2_RTC_14_SHFT 14
3758#define UV3H_EVENT_OCCURRED2_RTC_15_SHFT 15
3759#define UV3H_EVENT_OCCURRED2_RTC_16_SHFT 16
3760#define UV3H_EVENT_OCCURRED2_RTC_17_SHFT 17
3761#define UV3H_EVENT_OCCURRED2_RTC_18_SHFT 18
3762#define UV3H_EVENT_OCCURRED2_RTC_19_SHFT 19
3763#define UV3H_EVENT_OCCURRED2_RTC_20_SHFT 20
3764#define UV3H_EVENT_OCCURRED2_RTC_21_SHFT 21
3765#define UV3H_EVENT_OCCURRED2_RTC_22_SHFT 22
3766#define UV3H_EVENT_OCCURRED2_RTC_23_SHFT 23
3767#define UV3H_EVENT_OCCURRED2_RTC_24_SHFT 24
3768#define UV3H_EVENT_OCCURRED2_RTC_25_SHFT 25
3769#define UV3H_EVENT_OCCURRED2_RTC_26_SHFT 26
3770#define UV3H_EVENT_OCCURRED2_RTC_27_SHFT 27
3771#define UV3H_EVENT_OCCURRED2_RTC_28_SHFT 28
3772#define UV3H_EVENT_OCCURRED2_RTC_29_SHFT 29
3773#define UV3H_EVENT_OCCURRED2_RTC_30_SHFT 30
3774#define UV3H_EVENT_OCCURRED2_RTC_31_SHFT 31
3775#define UV3H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000000001UL
3776#define UV3H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000000002UL
3777#define UV3H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000000004UL
3778#define UV3H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000000008UL
3779#define UV3H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000000010UL
3780#define UV3H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000000020UL
3781#define UV3H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000000000040UL
3782#define UV3H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000000000080UL
3783#define UV3H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000000000100UL
3784#define UV3H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000000000200UL
3785#define UV3H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000000000400UL
3786#define UV3H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000000000800UL
3787#define UV3H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000000001000UL
3788#define UV3H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000000002000UL
3789#define UV3H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000000004000UL
3790#define UV3H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000000008000UL
3791#define UV3H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000000010000UL
3792#define UV3H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000000020000UL
3793#define UV3H_EVENT_OCCURRED2_RTC_18_MASK 0x0000000000040000UL
3794#define UV3H_EVENT_OCCURRED2_RTC_19_MASK 0x0000000000080000UL
3795#define UV3H_EVENT_OCCURRED2_RTC_20_MASK 0x0000000000100000UL
3796#define UV3H_EVENT_OCCURRED2_RTC_21_MASK 0x0000000000200000UL
3797#define UV3H_EVENT_OCCURRED2_RTC_22_MASK 0x0000000000400000UL
3798#define UV3H_EVENT_OCCURRED2_RTC_23_MASK 0x0000000000800000UL
3799#define UV3H_EVENT_OCCURRED2_RTC_24_MASK 0x0000000001000000UL
3800#define UV3H_EVENT_OCCURRED2_RTC_25_MASK 0x0000000002000000UL
3801#define UV3H_EVENT_OCCURRED2_RTC_26_MASK 0x0000000004000000UL
3802#define UV3H_EVENT_OCCURRED2_RTC_27_MASK 0x0000000008000000UL
3803#define UV3H_EVENT_OCCURRED2_RTC_28_MASK 0x0000000010000000UL
3804#define UV3H_EVENT_OCCURRED2_RTC_29_MASK 0x0000000020000000UL
3805#define UV3H_EVENT_OCCURRED2_RTC_30_MASK 0x0000000040000000UL
3806#define UV3H_EVENT_OCCURRED2_RTC_31_MASK 0x0000000080000000UL
3807
3808#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_SHFT 0
3809#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_SHFT 1
3810#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_SHFT 2
3811#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_SHFT 3
3812#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_SHFT 4
3813#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_SHFT 5
3814#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_SHFT 6
3815#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_SHFT 7
3816#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_SHFT 8
3817#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_SHFT 9
3818#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_SHFT 10
3819#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_SHFT 11
3820#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_SHFT 12
3821#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_SHFT 13
3822#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_SHFT 14
3823#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_SHFT 15
3824#define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_SHFT 16
3825#define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_SHFT 17
3826#define UV4H_EVENT_OCCURRED2_RTC_0_SHFT 18
3827#define UV4H_EVENT_OCCURRED2_RTC_1_SHFT 19
3828#define UV4H_EVENT_OCCURRED2_RTC_2_SHFT 20
3829#define UV4H_EVENT_OCCURRED2_RTC_3_SHFT 21
3830#define UV4H_EVENT_OCCURRED2_RTC_4_SHFT 22
3831#define UV4H_EVENT_OCCURRED2_RTC_5_SHFT 23
3832#define UV4H_EVENT_OCCURRED2_RTC_6_SHFT 24
3833#define UV4H_EVENT_OCCURRED2_RTC_7_SHFT 25
3834#define UV4H_EVENT_OCCURRED2_RTC_8_SHFT 26
3835#define UV4H_EVENT_OCCURRED2_RTC_9_SHFT 27
3836#define UV4H_EVENT_OCCURRED2_RTC_10_SHFT 28
3837#define UV4H_EVENT_OCCURRED2_RTC_11_SHFT 29
3838#define UV4H_EVENT_OCCURRED2_RTC_12_SHFT 30
3839#define UV4H_EVENT_OCCURRED2_RTC_13_SHFT 31
3840#define UV4H_EVENT_OCCURRED2_RTC_14_SHFT 32
3841#define UV4H_EVENT_OCCURRED2_RTC_15_SHFT 33
3842#define UV4H_EVENT_OCCURRED2_RTC_16_SHFT 34
3843#define UV4H_EVENT_OCCURRED2_RTC_17_SHFT 35
3844#define UV4H_EVENT_OCCURRED2_RTC_18_SHFT 36
3845#define UV4H_EVENT_OCCURRED2_RTC_19_SHFT 37
3846#define UV4H_EVENT_OCCURRED2_RTC_20_SHFT 38
3847#define UV4H_EVENT_OCCURRED2_RTC_21_SHFT 39
3848#define UV4H_EVENT_OCCURRED2_RTC_22_SHFT 40
3849#define UV4H_EVENT_OCCURRED2_RTC_23_SHFT 41
3850#define UV4H_EVENT_OCCURRED2_RTC_24_SHFT 42
3851#define UV4H_EVENT_OCCURRED2_RTC_25_SHFT 43
3852#define UV4H_EVENT_OCCURRED2_RTC_26_SHFT 44
3853#define UV4H_EVENT_OCCURRED2_RTC_27_SHFT 45
3854#define UV4H_EVENT_OCCURRED2_RTC_28_SHFT 46
3855#define UV4H_EVENT_OCCURRED2_RTC_29_SHFT 47
3856#define UV4H_EVENT_OCCURRED2_RTC_30_SHFT 48
3857#define UV4H_EVENT_OCCURRED2_RTC_31_SHFT 49
3858#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT0_MASK 0x0000000000000001UL
3859#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT1_MASK 0x0000000000000002UL
3860#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT2_MASK 0x0000000000000004UL
3861#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT3_MASK 0x0000000000000008UL
3862#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT4_MASK 0x0000000000000010UL
3863#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT5_MASK 0x0000000000000020UL
3864#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT6_MASK 0x0000000000000040UL
3865#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT7_MASK 0x0000000000000080UL
3866#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT8_MASK 0x0000000000000100UL
3867#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT9_MASK 0x0000000000000200UL
3868#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT10_MASK 0x0000000000000400UL
3869#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT11_MASK 0x0000000000000800UL
3870#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT12_MASK 0x0000000000001000UL
3871#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT13_MASK 0x0000000000002000UL
3872#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT14_MASK 0x0000000000004000UL
3873#define UV4H_EVENT_OCCURRED2_MESSAGE_ACCELERATOR_INT15_MASK 0x0000000000008000UL
3874#define UV4H_EVENT_OCCURRED2_RTC_INTERVAL_INT_MASK 0x0000000000010000UL
3875#define UV4H_EVENT_OCCURRED2_BAU_DASHBOARD_INT_MASK 0x0000000000020000UL
3876#define UV4H_EVENT_OCCURRED2_RTC_0_MASK 0x0000000000040000UL
3877#define UV4H_EVENT_OCCURRED2_RTC_1_MASK 0x0000000000080000UL
3878#define UV4H_EVENT_OCCURRED2_RTC_2_MASK 0x0000000000100000UL
3879#define UV4H_EVENT_OCCURRED2_RTC_3_MASK 0x0000000000200000UL
3880#define UV4H_EVENT_OCCURRED2_RTC_4_MASK 0x0000000000400000UL
3881#define UV4H_EVENT_OCCURRED2_RTC_5_MASK 0x0000000000800000UL
3882#define UV4H_EVENT_OCCURRED2_RTC_6_MASK 0x0000000001000000UL
3883#define UV4H_EVENT_OCCURRED2_RTC_7_MASK 0x0000000002000000UL
3884#define UV4H_EVENT_OCCURRED2_RTC_8_MASK 0x0000000004000000UL
3885#define UV4H_EVENT_OCCURRED2_RTC_9_MASK 0x0000000008000000UL
3886#define UV4H_EVENT_OCCURRED2_RTC_10_MASK 0x0000000010000000UL
3887#define UV4H_EVENT_OCCURRED2_RTC_11_MASK 0x0000000020000000UL
3888#define UV4H_EVENT_OCCURRED2_RTC_12_MASK 0x0000000040000000UL
3889#define UV4H_EVENT_OCCURRED2_RTC_13_MASK 0x0000000080000000UL
3890#define UV4H_EVENT_OCCURRED2_RTC_14_MASK 0x0000000100000000UL
3891#define UV4H_EVENT_OCCURRED2_RTC_15_MASK 0x0000000200000000UL
3892#define UV4H_EVENT_OCCURRED2_RTC_16_MASK 0x0000000400000000UL
3893#define UV4H_EVENT_OCCURRED2_RTC_17_MASK 0x0000000800000000UL
3894#define UV4H_EVENT_OCCURRED2_RTC_18_MASK 0x0000001000000000UL
3895#define UV4H_EVENT_OCCURRED2_RTC_19_MASK 0x0000002000000000UL
3896#define UV4H_EVENT_OCCURRED2_RTC_20_MASK 0x0000004000000000UL
3897#define UV4H_EVENT_OCCURRED2_RTC_21_MASK 0x0000008000000000UL
3898#define UV4H_EVENT_OCCURRED2_RTC_22_MASK 0x0000010000000000UL
3899#define UV4H_EVENT_OCCURRED2_RTC_23_MASK 0x0000020000000000UL
3900#define UV4H_EVENT_OCCURRED2_RTC_24_MASK 0x0000040000000000UL
3901#define UV4H_EVENT_OCCURRED2_RTC_25_MASK 0x0000080000000000UL
3902#define UV4H_EVENT_OCCURRED2_RTC_26_MASK 0x0000100000000000UL
3903#define UV4H_EVENT_OCCURRED2_RTC_27_MASK 0x0000200000000000UL
3904#define UV4H_EVENT_OCCURRED2_RTC_28_MASK 0x0000400000000000UL
3905#define UV4H_EVENT_OCCURRED2_RTC_29_MASK 0x0000800000000000UL
3906#define UV4H_EVENT_OCCURRED2_RTC_30_MASK 0x0001000000000000UL
3907#define UV4H_EVENT_OCCURRED2_RTC_31_MASK 0x0002000000000000UL
3908
3909#define UVXH_EVENT_OCCURRED2_RTC_1_MASK ( \
3910 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_RTC_1_MASK : \
3911 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_RTC_1_MASK : \
3912 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_RTC_1_MASK)
3913
3914union uvh_event_occurred2_u {
2711 unsigned long v; 3915 unsigned long v;
2712 struct uvxh_event_occurred2_s { 3916 struct uv2h_event_occurred2_s {
2713 unsigned long rtc_0:1; /* RW */ 3917 unsigned long rtc_0:1; /* RW */
2714 unsigned long rtc_1:1; /* RW */ 3918 unsigned long rtc_1:1; /* RW */
2715 unsigned long rtc_2:1; /* RW */ 3919 unsigned long rtc_2:1; /* RW */
@@ -2743,25 +3947,129 @@ union uvxh_event_occurred2_u {
2743 unsigned long rtc_30:1; /* RW */ 3947 unsigned long rtc_30:1; /* RW */
2744 unsigned long rtc_31:1; /* RW */ 3948 unsigned long rtc_31:1; /* RW */
2745 unsigned long rsvd_32_63:32; 3949 unsigned long rsvd_32_63:32;
2746 } sx; 3950 } s2;
3951 struct uv3h_event_occurred2_s {
3952 unsigned long rtc_0:1; /* RW */
3953 unsigned long rtc_1:1; /* RW */
3954 unsigned long rtc_2:1; /* RW */
3955 unsigned long rtc_3:1; /* RW */
3956 unsigned long rtc_4:1; /* RW */
3957 unsigned long rtc_5:1; /* RW */
3958 unsigned long rtc_6:1; /* RW */
3959 unsigned long rtc_7:1; /* RW */
3960 unsigned long rtc_8:1; /* RW */
3961 unsigned long rtc_9:1; /* RW */
3962 unsigned long rtc_10:1; /* RW */
3963 unsigned long rtc_11:1; /* RW */
3964 unsigned long rtc_12:1; /* RW */
3965 unsigned long rtc_13:1; /* RW */
3966 unsigned long rtc_14:1; /* RW */
3967 unsigned long rtc_15:1; /* RW */
3968 unsigned long rtc_16:1; /* RW */
3969 unsigned long rtc_17:1; /* RW */
3970 unsigned long rtc_18:1; /* RW */
3971 unsigned long rtc_19:1; /* RW */
3972 unsigned long rtc_20:1; /* RW */
3973 unsigned long rtc_21:1; /* RW */
3974 unsigned long rtc_22:1; /* RW */
3975 unsigned long rtc_23:1; /* RW */
3976 unsigned long rtc_24:1; /* RW */
3977 unsigned long rtc_25:1; /* RW */
3978 unsigned long rtc_26:1; /* RW */
3979 unsigned long rtc_27:1; /* RW */
3980 unsigned long rtc_28:1; /* RW */
3981 unsigned long rtc_29:1; /* RW */
3982 unsigned long rtc_30:1; /* RW */
3983 unsigned long rtc_31:1; /* RW */
3984 unsigned long rsvd_32_63:32;
3985 } s3;
3986 struct uv4h_event_occurred2_s {
3987 unsigned long message_accelerator_int0:1; /* RW */
3988 unsigned long message_accelerator_int1:1; /* RW */
3989 unsigned long message_accelerator_int2:1; /* RW */
3990 unsigned long message_accelerator_int3:1; /* RW */
3991 unsigned long message_accelerator_int4:1; /* RW */
3992 unsigned long message_accelerator_int5:1; /* RW */
3993 unsigned long message_accelerator_int6:1; /* RW */
3994 unsigned long message_accelerator_int7:1; /* RW */
3995 unsigned long message_accelerator_int8:1; /* RW */
3996 unsigned long message_accelerator_int9:1; /* RW */
3997 unsigned long message_accelerator_int10:1; /* RW */
3998 unsigned long message_accelerator_int11:1; /* RW */
3999 unsigned long message_accelerator_int12:1; /* RW */
4000 unsigned long message_accelerator_int13:1; /* RW */
4001 unsigned long message_accelerator_int14:1; /* RW */
4002 unsigned long message_accelerator_int15:1; /* RW */
4003 unsigned long rtc_interval_int:1; /* RW */
4004 unsigned long bau_dashboard_int:1; /* RW */
4005 unsigned long rtc_0:1; /* RW */
4006 unsigned long rtc_1:1; /* RW */
4007 unsigned long rtc_2:1; /* RW */
4008 unsigned long rtc_3:1; /* RW */
4009 unsigned long rtc_4:1; /* RW */
4010 unsigned long rtc_5:1; /* RW */
4011 unsigned long rtc_6:1; /* RW */
4012 unsigned long rtc_7:1; /* RW */
4013 unsigned long rtc_8:1; /* RW */
4014 unsigned long rtc_9:1; /* RW */
4015 unsigned long rtc_10:1; /* RW */
4016 unsigned long rtc_11:1; /* RW */
4017 unsigned long rtc_12:1; /* RW */
4018 unsigned long rtc_13:1; /* RW */
4019 unsigned long rtc_14:1; /* RW */
4020 unsigned long rtc_15:1; /* RW */
4021 unsigned long rtc_16:1; /* RW */
4022 unsigned long rtc_17:1; /* RW */
4023 unsigned long rtc_18:1; /* RW */
4024 unsigned long rtc_19:1; /* RW */
4025 unsigned long rtc_20:1; /* RW */
4026 unsigned long rtc_21:1; /* RW */
4027 unsigned long rtc_22:1; /* RW */
4028 unsigned long rtc_23:1; /* RW */
4029 unsigned long rtc_24:1; /* RW */
4030 unsigned long rtc_25:1; /* RW */
4031 unsigned long rtc_26:1; /* RW */
4032 unsigned long rtc_27:1; /* RW */
4033 unsigned long rtc_28:1; /* RW */
4034 unsigned long rtc_29:1; /* RW */
4035 unsigned long rtc_30:1; /* RW */
4036 unsigned long rtc_31:1; /* RW */
4037 unsigned long rsvd_50_63:14;
4038 } s4;
2747}; 4039};
2748 4040
2749/* ========================================================================= */ 4041/* ========================================================================= */
2750/* UVXH_EVENT_OCCURRED2_ALIAS */ 4042/* UVXH_EVENT_OCCURRED2_ALIAS */
2751/* ========================================================================= */ 4043/* ========================================================================= */
2752#define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL 4044#define UVXH_EVENT_OCCURRED2_ALIAS 0x70108UL
2753#define UVXH_EVENT_OCCURRED2_ALIAS_32 0xb70 4045
4046#define UV2H_EVENT_OCCURRED2_ALIAS_32 0xb70
4047#define UV3H_EVENT_OCCURRED2_ALIAS_32 0xb70
4048#define UV4H_EVENT_OCCURRED2_ALIAS_32 0x610
4049#define UVH_EVENT_OCCURRED2_ALIAS_32 ( \
4050 is_uv2_hub() ? UV2H_EVENT_OCCURRED2_ALIAS_32 : \
4051 is_uv3_hub() ? UV3H_EVENT_OCCURRED2_ALIAS_32 : \
4052 /*is_uv4_hub*/ UV4H_EVENT_OCCURRED2_ALIAS_32)
2754 4053
2755 4054
2756/* ========================================================================= */ 4055/* ========================================================================= */
2757/* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */ 4056/* UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 */
2758/* ========================================================================= */ 4057/* ========================================================================= */
2759#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
2760#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 4058#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
2761#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL 4059#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 0x320130UL
2762#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0 4060#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2 0xc8130UL
2763#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL 4061#define UVH_LB_BAU_SB_ACTIVATION_STATUS_2 ( \
2764#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x320130UL 4062 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2 : \
4063 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2 : \
4064 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2)
4065
4066#define UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4067#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0x9f0
4068#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32 0xa10
4069#define UVH_LB_BAU_SB_ACTIVATION_STATUS_2_32 ( \
4070 is_uv2_hub() ? UV2H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \
4071 is_uv3_hub() ? UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_32 : \
4072 /*is_uv4_hub*/ UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_32)
2765 4073
2766#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4074#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
2767#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4075#define UVXH_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
@@ -2772,6 +4080,10 @@ union uvxh_event_occurred2_u {
2772#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0 4080#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
2773#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL 4081#define UV3H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
2774 4082
4083#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_SHFT 0
4084#define UV4H_LB_BAU_SB_ACTIVATION_STATUS_2_AUX_ERROR_MASK 0xffffffffffffffffUL
4085
4086
2775union uvxh_lb_bau_sb_activation_status_2_u { 4087union uvxh_lb_bau_sb_activation_status_2_u {
2776 unsigned long v; 4088 unsigned long v;
2777 struct uvxh_lb_bau_sb_activation_status_2_s { 4089 struct uvxh_lb_bau_sb_activation_status_2_s {
@@ -2783,6 +4095,9 @@ union uvxh_lb_bau_sb_activation_status_2_u {
2783 struct uv3h_lb_bau_sb_activation_status_2_s { 4095 struct uv3h_lb_bau_sb_activation_status_2_s {
2784 unsigned long aux_error:64; /* RW */ 4096 unsigned long aux_error:64; /* RW */
2785 } s3; 4097 } s3;
4098 struct uv4h_lb_bau_sb_activation_status_2_s {
4099 unsigned long aux_error:64; /* RW */
4100 } s4;
2786}; 4101};
2787 4102
2788/* ========================================================================= */ 4103/* ========================================================================= */
@@ -2823,26 +4138,6 @@ union uv3h_gr0_gam_gr_config_u {
2823}; 4138};
2824 4139
2825/* ========================================================================= */ 4140/* ========================================================================= */
2826/* UV3H_GR1_GAM_GR_CONFIG */
2827/* ========================================================================= */
2828#define UV3H_GR1_GAM_GR_CONFIG 0x1000028UL
2829
2830#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_SHFT 0
2831#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_SHFT 10
2832#define UV3H_GR1_GAM_GR_CONFIG_M_SKT_MASK 0x000000000000003fUL
2833#define UV3H_GR1_GAM_GR_CONFIG_SUBSPACE_MASK 0x0000000000000400UL
2834
2835union uv3h_gr1_gam_gr_config_u {
2836 unsigned long v;
2837 struct uv3h_gr1_gam_gr_config_s {
2838 unsigned long m_skt:6; /* RW */
2839 unsigned long undef_6_9:4; /* Undefined */
2840 unsigned long subspace:1; /* RW */
2841 unsigned long reserved:53;
2842 } s3;
2843};
2844
2845/* ========================================================================= */
2846/* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */ 4141/* UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR */
2847/* ========================================================================= */ 4142/* ========================================================================= */
2848#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL 4143#define UV3H_RH_GAM_MMIOH_OVERLAY_CONFIG0_MMR 0x1603000UL
@@ -2924,5 +4219,67 @@ union uv3h_rh_gam_mmioh_redirect_config1_mmr_u {
2924 } s3; 4219 } s3;
2925}; 4220};
2926 4221
4222/* ========================================================================= */
4223/* UV4H_LB_PROC_INTD_QUEUE_FIRST */
4224/* ========================================================================= */
4225#define UV4H_LB_PROC_INTD_QUEUE_FIRST 0xa4100UL
4226
4227#define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_SHFT 6
4228#define UV4H_LB_PROC_INTD_QUEUE_FIRST_FIRST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffc0UL
4229
4230union uv4h_lb_proc_intd_queue_first_u {
4231 unsigned long v;
4232 struct uv4h_lb_proc_intd_queue_first_s {
4233 unsigned long undef_0_5:6; /* Undefined */
4234 unsigned long first_payload_address:40; /* RW */
4235 } s4;
4236};
4237
4238/* ========================================================================= */
4239/* UV4H_LB_PROC_INTD_QUEUE_LAST */
4240/* ========================================================================= */
4241#define UV4H_LB_PROC_INTD_QUEUE_LAST 0xa4108UL
4242
4243#define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_SHFT 5
4244#define UV4H_LB_PROC_INTD_QUEUE_LAST_LAST_PAYLOAD_ADDRESS_MASK 0x00003fffffffffe0UL
4245
4246union uv4h_lb_proc_intd_queue_last_u {
4247 unsigned long v;
4248 struct uv4h_lb_proc_intd_queue_last_s {
4249 unsigned long undef_0_4:5; /* Undefined */
4250 unsigned long last_payload_address:41; /* RW */
4251 } s4;
4252};
4253
4254/* ========================================================================= */
4255/* UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR */
4256/* ========================================================================= */
4257#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR 0xa4118UL
4258
4259#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_SHFT 0
4260#define UV4H_LB_PROC_INTD_SOFT_ACK_CLEAR_SOFT_ACK_PENDING_FLAGS_MASK 0x00000000000000ffUL
4261
4262union uv4h_lb_proc_intd_soft_ack_clear_u {
4263 unsigned long v;
4264 struct uv4h_lb_proc_intd_soft_ack_clear_s {
4265 unsigned long soft_ack_pending_flags:8; /* WP */
4266 } s4;
4267};
4268
4269/* ========================================================================= */
4270/* UV4H_LB_PROC_INTD_SOFT_ACK_PENDING */
4271/* ========================================================================= */
4272#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING 0xa4110UL
4273
4274#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_SHFT 0
4275#define UV4H_LB_PROC_INTD_SOFT_ACK_PENDING_SOFT_ACK_FLAGS_MASK 0x00000000000000ffUL
4276
4277union uv4h_lb_proc_intd_soft_ack_pending_u {
4278 unsigned long v;
4279 struct uv4h_lb_proc_intd_soft_ack_pending_s {
4280 unsigned long soft_ack_flags:8; /* RW */
4281 } s4;
4282};
4283
2927 4284
2928#endif /* _ASM_X86_UV_UV_MMRS_H */ 4285#endif /* _ASM_X86_UV_UV_MMRS_H */
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index d7ce96a7daca..29003154fafd 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -48,12 +48,35 @@ static u64 gru_start_paddr, gru_end_paddr;
48static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr; 48static u64 gru_dist_base, gru_first_node_paddr = -1LL, gru_last_node_paddr;
49static u64 gru_dist_lmask, gru_dist_umask; 49static u64 gru_dist_lmask, gru_dist_umask;
50static union uvh_apicid uvh_apicid; 50static union uvh_apicid uvh_apicid;
51
52/* info derived from CPUID */
53static struct {
54 unsigned int apicid_shift;
55 unsigned int apicid_mask;
56 unsigned int socketid_shift; /* aka pnode_shift for UV1/2/3 */
57 unsigned int pnode_mask;
58 unsigned int gpa_shift;
59} uv_cpuid;
60
51int uv_min_hub_revision_id; 61int uv_min_hub_revision_id;
52EXPORT_SYMBOL_GPL(uv_min_hub_revision_id); 62EXPORT_SYMBOL_GPL(uv_min_hub_revision_id);
53unsigned int uv_apicid_hibits; 63unsigned int uv_apicid_hibits;
54EXPORT_SYMBOL_GPL(uv_apicid_hibits); 64EXPORT_SYMBOL_GPL(uv_apicid_hibits);
55 65
56static struct apic apic_x2apic_uv_x; 66static struct apic apic_x2apic_uv_x;
67static struct uv_hub_info_s uv_hub_info_node0;
68
69/* Set this to use hardware error handler instead of kernel panic */
70static int disable_uv_undefined_panic = 1;
71unsigned long uv_undefined(char *str)
72{
73 if (likely(!disable_uv_undefined_panic))
74 panic("UV: error: undefined MMR: %s\n", str);
75 else
76 pr_crit("UV: error: undefined MMR: %s\n", str);
77 return ~0ul; /* cause a machine fault */
78}
79EXPORT_SYMBOL(uv_undefined);
57 80
58static unsigned long __init uv_early_read_mmr(unsigned long addr) 81static unsigned long __init uv_early_read_mmr(unsigned long addr)
59{ 82{
@@ -108,21 +131,71 @@ static int __init early_get_pnodeid(void)
108 case UV3_HUB_PART_NUMBER_X: 131 case UV3_HUB_PART_NUMBER_X:
109 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE; 132 uv_min_hub_revision_id += UV3_HUB_REVISION_BASE;
110 break; 133 break;
134 case UV4_HUB_PART_NUMBER:
135 uv_min_hub_revision_id += UV4_HUB_REVISION_BASE - 1;
136 break;
111 } 137 }
112 138
113 uv_hub_info->hub_revision = uv_min_hub_revision_id; 139 uv_hub_info->hub_revision = uv_min_hub_revision_id;
114 pnode = (node_id.s.node_id >> 1) & ((1 << m_n_config.s.n_skt) - 1); 140 uv_cpuid.pnode_mask = (1 << m_n_config.s.n_skt) - 1;
141 pnode = (node_id.s.node_id >> 1) & uv_cpuid.pnode_mask;
142 uv_cpuid.gpa_shift = 46; /* default unless changed */
143
144 pr_info("UV: rev:%d part#:%x nodeid:%04x n_skt:%d pnmsk:%x pn:%x\n",
145 node_id.s.revision, node_id.s.part_number, node_id.s.node_id,
146 m_n_config.s.n_skt, uv_cpuid.pnode_mask, pnode);
115 return pnode; 147 return pnode;
116} 148}
117 149
118static void __init early_get_apic_pnode_shift(void) 150/* [copied from arch/x86/kernel/cpu/topology.c:detect_extended_topology()] */
151#define SMT_LEVEL 0 /* leaf 0xb SMT level */
152#define INVALID_TYPE 0 /* leaf 0xb sub-leaf types */
153#define SMT_TYPE 1
154#define CORE_TYPE 2
155#define LEAFB_SUBTYPE(ecx) (((ecx) >> 8) & 0xff)
156#define BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
157
158static void set_x2apic_bits(void)
159{
160 unsigned int eax, ebx, ecx, edx, sub_index;
161 unsigned int sid_shift;
162
163 cpuid(0, &eax, &ebx, &ecx, &edx);
164 if (eax < 0xb) {
165 pr_info("UV: CPU does not have CPUID.11\n");
166 return;
167 }
168 cpuid_count(0xb, SMT_LEVEL, &eax, &ebx, &ecx, &edx);
169 if (ebx == 0 || (LEAFB_SUBTYPE(ecx) != SMT_TYPE)) {
170 pr_info("UV: CPUID.11 not implemented\n");
171 return;
172 }
173 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
174 sub_index = 1;
175 do {
176 cpuid_count(0xb, sub_index, &eax, &ebx, &ecx, &edx);
177 if (LEAFB_SUBTYPE(ecx) == CORE_TYPE) {
178 sid_shift = BITS_SHIFT_NEXT_LEVEL(eax);
179 break;
180 }
181 sub_index++;
182 } while (LEAFB_SUBTYPE(ecx) != INVALID_TYPE);
183 uv_cpuid.apicid_shift = 0;
184 uv_cpuid.apicid_mask = (~(-1 << sid_shift));
185 uv_cpuid.socketid_shift = sid_shift;
186}
187
188static void __init early_get_apic_socketid_shift(void)
119{ 189{
120 uvh_apicid.v = uv_early_read_mmr(UVH_APICID); 190 if (is_uv2_hub() || is_uv3_hub())
121 if (!uvh_apicid.v) 191 uvh_apicid.v = uv_early_read_mmr(UVH_APICID);
122 /* 192
123 * Old bios, use default value 193 set_x2apic_bits();
124 */ 194
125 uvh_apicid.s.pnode_shift = UV_APIC_PNODE_SHIFT; 195 pr_info("UV: apicid_shift:%d apicid_mask:0x%x\n",
196 uv_cpuid.apicid_shift, uv_cpuid.apicid_mask);
197 pr_info("UV: socketid_shift:%d pnode_mask:0x%x\n",
198 uv_cpuid.socketid_shift, uv_cpuid.pnode_mask);
126} 199}
127 200
128/* 201/*
@@ -150,13 +223,18 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
150 if (strncmp(oem_id, "SGI", 3) != 0) 223 if (strncmp(oem_id, "SGI", 3) != 0)
151 return 0; 224 return 0;
152 225
226 /* Setup early hub type field in uv_hub_info for Node 0 */
227 uv_cpu_info->p_uv_hub_info = &uv_hub_info_node0;
228
153 /* 229 /*
154 * Determine UV arch type. 230 * Determine UV arch type.
155 * SGI: UV100/1000 231 * SGI: UV100/1000
156 * SGI2: UV2000/3000 232 * SGI2: UV2000/3000
157 * SGI3: UV300 (truncated to 4 chars because of different varieties) 233 * SGI3: UV300 (truncated to 4 chars because of different varieties)
234 * SGI4: UV400 (truncated to 4 chars because of different varieties)
158 */ 235 */
159 uv_hub_info->hub_revision = 236 uv_hub_info->hub_revision =
237 !strncmp(oem_id, "SGI4", 4) ? UV4_HUB_REVISION_BASE :
160 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE : 238 !strncmp(oem_id, "SGI3", 4) ? UV3_HUB_REVISION_BASE :
161 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE : 239 !strcmp(oem_id, "SGI2") ? UV2_HUB_REVISION_BASE :
162 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0; 240 !strcmp(oem_id, "SGI") ? UV1_HUB_REVISION_BASE : 0;
@@ -165,7 +243,7 @@ static int __init uv_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
165 goto badbios; 243 goto badbios;
166 244
167 pnodeid = early_get_pnodeid(); 245 pnodeid = early_get_pnodeid();
168 early_get_apic_pnode_shift(); 246 early_get_apic_socketid_shift();
169 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range; 247 x86_platform.is_untracked_pat_range = uv_is_untracked_pat_range;
170 x86_platform.nmi_init = uv_nmi_init; 248 x86_platform.nmi_init = uv_nmi_init;
171 249
@@ -211,17 +289,11 @@ int is_uv_system(void)
211} 289}
212EXPORT_SYMBOL_GPL(is_uv_system); 290EXPORT_SYMBOL_GPL(is_uv_system);
213 291
214DEFINE_PER_CPU(struct uv_hub_info_s, __uv_hub_info); 292void **__uv_hub_info_list;
215EXPORT_PER_CPU_SYMBOL_GPL(__uv_hub_info); 293EXPORT_SYMBOL_GPL(__uv_hub_info_list);
216
217struct uv_blade_info *uv_blade_info;
218EXPORT_SYMBOL_GPL(uv_blade_info);
219
220short *uv_node_to_blade;
221EXPORT_SYMBOL_GPL(uv_node_to_blade);
222 294
223short *uv_cpu_to_blade; 295DEFINE_PER_CPU(struct uv_cpu_info_s, __uv_cpu_info);
224EXPORT_SYMBOL_GPL(uv_cpu_to_blade); 296EXPORT_PER_CPU_SYMBOL_GPL(__uv_cpu_info);
225 297
226short uv_possible_blades; 298short uv_possible_blades;
227EXPORT_SYMBOL_GPL(uv_possible_blades); 299EXPORT_SYMBOL_GPL(uv_possible_blades);
@@ -229,6 +301,115 @@ EXPORT_SYMBOL_GPL(uv_possible_blades);
229unsigned long sn_rtc_cycles_per_second; 301unsigned long sn_rtc_cycles_per_second;
230EXPORT_SYMBOL(sn_rtc_cycles_per_second); 302EXPORT_SYMBOL(sn_rtc_cycles_per_second);
231 303
304/* the following values are used for the per node hub info struct */
305static __initdata unsigned short *_node_to_pnode;
306static __initdata unsigned short _min_socket, _max_socket;
307static __initdata unsigned short _min_pnode, _max_pnode, _gr_table_len;
308static __initdata struct uv_gam_range_entry *uv_gre_table;
309static __initdata struct uv_gam_parameters *uv_gp_table;
310static __initdata unsigned short *_socket_to_node;
311static __initdata unsigned short *_socket_to_pnode;
312static __initdata unsigned short *_pnode_to_socket;
313static __initdata struct uv_gam_range_s *_gr_table;
314#define SOCK_EMPTY ((unsigned short)~0)
315
316extern int uv_hub_info_version(void)
317{
318 return UV_HUB_INFO_VERSION;
319}
320EXPORT_SYMBOL(uv_hub_info_version);
321
322/* Build GAM range lookup table */
323static __init void build_uv_gr_table(void)
324{
325 struct uv_gam_range_entry *gre = uv_gre_table;
326 struct uv_gam_range_s *grt;
327 unsigned long last_limit = 0, ram_limit = 0;
328 int bytes, i, sid, lsid = -1;
329
330 if (!gre)
331 return;
332
333 bytes = _gr_table_len * sizeof(struct uv_gam_range_s);
334 grt = kzalloc(bytes, GFP_KERNEL);
335 BUG_ON(!grt);
336 _gr_table = grt;
337
338 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
339 if (gre->type == UV_GAM_RANGE_TYPE_HOLE) {
340 if (!ram_limit) { /* mark hole between ram/non-ram */
341 ram_limit = last_limit;
342 last_limit = gre->limit;
343 lsid++;
344 continue;
345 }
346 last_limit = gre->limit;
347 pr_info("UV: extra hole in GAM RE table @%d\n",
348 (int)(gre - uv_gre_table));
349 continue;
350 }
351 if (_max_socket < gre->sockid) {
352 pr_err("UV: GAM table sockid(%d) too large(>%d) @%d\n",
353 gre->sockid, _max_socket,
354 (int)(gre - uv_gre_table));
355 continue;
356 }
357 sid = gre->sockid - _min_socket;
358 if (lsid < sid) { /* new range */
359 grt = &_gr_table[sid];
360 grt->base = lsid;
361 grt->nasid = gre->nasid;
362 grt->limit = last_limit = gre->limit;
363 lsid = sid;
364 continue;
365 }
366 if (lsid == sid && !ram_limit) { /* update range */
367 if (grt->limit == last_limit) { /* .. if contiguous */
368 grt->limit = last_limit = gre->limit;
369 continue;
370 }
371 }
372 if (!ram_limit) { /* non-contiguous ram range */
373 grt++;
374 grt->base = sid - 1;
375 grt->nasid = gre->nasid;
376 grt->limit = last_limit = gre->limit;
377 continue;
378 }
379 grt++; /* non-contiguous/non-ram */
380 grt->base = grt - _gr_table; /* base is this entry */
381 grt->nasid = gre->nasid;
382 grt->limit = last_limit = gre->limit;
383 lsid++;
384 }
385
386 /* shorten table if possible */
387 grt++;
388 i = grt - _gr_table;
389 if (i < _gr_table_len) {
390 void *ret;
391
392 bytes = i * sizeof(struct uv_gam_range_s);
393 ret = krealloc(_gr_table, bytes, GFP_KERNEL);
394 if (ret) {
395 _gr_table = ret;
396 _gr_table_len = i;
397 }
398 }
399
400 /* display resultant gam range table */
401 for (i = 0, grt = _gr_table; i < _gr_table_len; i++, grt++) {
402 int gb = grt->base;
403 unsigned long start = gb < 0 ? 0 :
404 (unsigned long)_gr_table[gb].limit << UV_GAM_RANGE_SHFT;
405 unsigned long end =
406 (unsigned long)grt->limit << UV_GAM_RANGE_SHFT;
407
408 pr_info("UV: GAM Range %2d %04x 0x%013lx-0x%013lx (%d)\n",
409 i, grt->nasid, start, end, gb);
410 }
411}
412
232static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip) 413static int uv_wakeup_secondary(int phys_apicid, unsigned long start_rip)
233{ 414{
234 unsigned long val; 415 unsigned long val;
@@ -355,7 +536,6 @@ static unsigned long set_apic_id(unsigned int id)
355 536
356static unsigned int uv_read_apic_id(void) 537static unsigned int uv_read_apic_id(void)
357{ 538{
358
359 return x2apic_get_apic_id(apic_read(APIC_ID)); 539 return x2apic_get_apic_id(apic_read(APIC_ID));
360} 540}
361 541
@@ -430,58 +610,38 @@ static void set_x2apic_extra_bits(int pnode)
430 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift); 610 __this_cpu_write(x2apic_extra_bits, pnode << uvh_apicid.s.pnode_shift);
431} 611}
432 612
433/* 613#define UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH 3
434 * Called on boot cpu.
435 */
436static __init int boot_pnode_to_blade(int pnode)
437{
438 int blade;
439
440 for (blade = 0; blade < uv_num_possible_blades(); blade++)
441 if (pnode == uv_blade_info[blade].pnode)
442 return blade;
443 BUG();
444}
445
446struct redir_addr {
447 unsigned long redirect;
448 unsigned long alias;
449};
450
451#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT 614#define DEST_SHIFT UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR_DEST_BASE_SHFT
452 615
453static __initdata struct redir_addr redir_addrs[] = {
454 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR},
455 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR},
456 {UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR, UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR},
457};
458
459static unsigned char get_n_lshift(int m_val)
460{
461 union uv3h_gr0_gam_gr_config_u m_gr_config;
462
463 if (is_uv1_hub())
464 return m_val;
465
466 if (is_uv2_hub())
467 return m_val == 40 ? 40 : 39;
468
469 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
470 return m_gr_config.s3.m_skt;
471}
472
473static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size) 616static __init void get_lowmem_redirect(unsigned long *base, unsigned long *size)
474{ 617{
475 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias; 618 union uvh_rh_gam_alias210_overlay_config_2_mmr_u alias;
476 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect; 619 union uvh_rh_gam_alias210_redirect_config_2_mmr_u redirect;
620 unsigned long m_redirect;
621 unsigned long m_overlay;
477 int i; 622 int i;
478 623
479 for (i = 0; i < ARRAY_SIZE(redir_addrs); i++) { 624 for (i = 0; i < UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_LENGTH; i++) {
480 alias.v = uv_read_local_mmr(redir_addrs[i].alias); 625 switch (i) {
626 case 0:
627 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_0_MMR;
628 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_0_MMR;
629 break;
630 case 1:
631 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_1_MMR;
632 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_1_MMR;
633 break;
634 case 2:
635 m_redirect = UVH_RH_GAM_ALIAS210_REDIRECT_CONFIG_2_MMR;
636 m_overlay = UVH_RH_GAM_ALIAS210_OVERLAY_CONFIG_2_MMR;
637 break;
638 }
639 alias.v = uv_read_local_mmr(m_overlay);
481 if (alias.s.enable && alias.s.base == 0) { 640 if (alias.s.enable && alias.s.base == 0) {
482 *size = (1UL << alias.s.m_alias); 641 *size = (1UL << alias.s.m_alias);
483 redirect.v = uv_read_local_mmr(redir_addrs[i].redirect); 642 redirect.v = uv_read_local_mmr(m_redirect);
484 *base = (unsigned long)redirect.s.dest_base << DEST_SHIFT; 643 *base = (unsigned long)redirect.s.dest_base
644 << DEST_SHIFT;
485 return; 645 return;
486 } 646 }
487 } 647 }
@@ -544,6 +704,8 @@ static __init void map_gru_high(int max_pnode)
544{ 704{
545 union uvh_rh_gam_gru_overlay_config_mmr_u gru; 705 union uvh_rh_gam_gru_overlay_config_mmr_u gru;
546 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT; 706 int shift = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_SHFT;
707 unsigned long mask = UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR_BASE_MASK;
708 unsigned long base;
547 709
548 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR); 710 gru.v = uv_read_local_mmr(UVH_RH_GAM_GRU_OVERLAY_CONFIG_MMR);
549 if (!gru.s.enable) { 711 if (!gru.s.enable) {
@@ -555,8 +717,9 @@ static __init void map_gru_high(int max_pnode)
555 map_gru_distributed(gru.v); 717 map_gru_distributed(gru.v);
556 return; 718 return;
557 } 719 }
558 map_high("GRU", gru.s.base, shift, shift, max_pnode, map_wb); 720 base = (gru.v & mask) >> shift;
559 gru_start_paddr = ((u64)gru.s.base << shift); 721 map_high("GRU", base, shift, shift, max_pnode, map_wb);
722 gru_start_paddr = ((u64)base << shift);
560 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1); 723 gru_end_paddr = gru_start_paddr + (1UL << shift) * (max_pnode + 1);
561} 724}
562 725
@@ -595,6 +758,7 @@ static __initdata struct mmioh_config mmiohs[] = {
595 }, 758 },
596}; 759};
597 760
761/* UV3 & UV4 have identical MMIOH overlay configs */
598static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode) 762static __init void map_mmioh_high_uv3(int index, int min_pnode, int max_pnode)
599{ 763{
600 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay; 764 union uv3h_rh_gam_mmioh_overlay_config0_mmr_u overlay;
@@ -674,7 +838,7 @@ static __init void map_mmioh_high(int min_pnode, int max_pnode)
674 unsigned long mmr, base; 838 unsigned long mmr, base;
675 int shift, enable, m_io, n_io; 839 int shift, enable, m_io, n_io;
676 840
677 if (is_uv3_hub()) { 841 if (is_uv3_hub() || is_uv4_hub()) {
678 /* Map both MMIOH Regions */ 842 /* Map both MMIOH Regions */
679 map_mmioh_high_uv3(0, min_pnode, max_pnode); 843 map_mmioh_high_uv3(0, min_pnode, max_pnode);
680 map_mmioh_high_uv3(1, min_pnode, max_pnode); 844 map_mmioh_high_uv3(1, min_pnode, max_pnode);
@@ -739,8 +903,8 @@ static __init void uv_rtc_init(void)
739 */ 903 */
740static void uv_heartbeat(unsigned long ignored) 904static void uv_heartbeat(unsigned long ignored)
741{ 905{
742 struct timer_list *timer = &uv_hub_info->scir.timer; 906 struct timer_list *timer = &uv_scir_info->timer;
743 unsigned char bits = uv_hub_info->scir.state; 907 unsigned char bits = uv_scir_info->state;
744 908
745 /* flip heartbeat bit */ 909 /* flip heartbeat bit */
746 bits ^= SCIR_CPU_HEARTBEAT; 910 bits ^= SCIR_CPU_HEARTBEAT;
@@ -760,14 +924,14 @@ static void uv_heartbeat(unsigned long ignored)
760 924
761static void uv_heartbeat_enable(int cpu) 925static void uv_heartbeat_enable(int cpu)
762{ 926{
763 while (!uv_cpu_hub_info(cpu)->scir.enabled) { 927 while (!uv_cpu_scir_info(cpu)->enabled) {
764 struct timer_list *timer = &uv_cpu_hub_info(cpu)->scir.timer; 928 struct timer_list *timer = &uv_cpu_scir_info(cpu)->timer;
765 929
766 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY); 930 uv_set_cpu_scir_bits(cpu, SCIR_CPU_HEARTBEAT|SCIR_CPU_ACTIVITY);
767 setup_timer(timer, uv_heartbeat, cpu); 931 setup_timer(timer, uv_heartbeat, cpu);
768 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL; 932 timer->expires = jiffies + SCIR_CPU_HB_INTERVAL;
769 add_timer_on(timer, cpu); 933 add_timer_on(timer, cpu);
770 uv_cpu_hub_info(cpu)->scir.enabled = 1; 934 uv_cpu_scir_info(cpu)->enabled = 1;
771 935
772 /* also ensure that boot cpu is enabled */ 936 /* also ensure that boot cpu is enabled */
773 cpu = 0; 937 cpu = 0;
@@ -777,9 +941,9 @@ static void uv_heartbeat_enable(int cpu)
777#ifdef CONFIG_HOTPLUG_CPU 941#ifdef CONFIG_HOTPLUG_CPU
778static void uv_heartbeat_disable(int cpu) 942static void uv_heartbeat_disable(int cpu)
779{ 943{
780 if (uv_cpu_hub_info(cpu)->scir.enabled) { 944 if (uv_cpu_scir_info(cpu)->enabled) {
781 uv_cpu_hub_info(cpu)->scir.enabled = 0; 945 uv_cpu_scir_info(cpu)->enabled = 0;
782 del_timer(&uv_cpu_hub_info(cpu)->scir.timer); 946 del_timer(&uv_cpu_scir_info(cpu)->timer);
783 } 947 }
784 uv_set_cpu_scir_bits(cpu, 0xff); 948 uv_set_cpu_scir_bits(cpu, 0xff);
785} 949}
@@ -862,155 +1026,475 @@ int uv_set_vga_state(struct pci_dev *pdev, bool decode,
862void uv_cpu_init(void) 1026void uv_cpu_init(void)
863{ 1027{
864 /* CPU 0 initialization will be done via uv_system_init. */ 1028 /* CPU 0 initialization will be done via uv_system_init. */
865 if (!uv_blade_info) 1029 if (smp_processor_id() == 0)
866 return; 1030 return;
867 1031
868 uv_blade_info[uv_numa_blade_id()].nr_online_cpus++; 1032 uv_hub_info->nr_online_cpus++;
869 1033
870 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) 1034 if (get_uv_system_type() == UV_NON_UNIQUE_APIC)
871 set_x2apic_extra_bits(uv_hub_info->pnode); 1035 set_x2apic_extra_bits(uv_hub_info->pnode);
872} 1036}
873 1037
874void __init uv_system_init(void) 1038struct mn {
1039 unsigned char m_val;
1040 unsigned char n_val;
1041 unsigned char m_shift;
1042 unsigned char n_lshift;
1043};
1044
1045static void get_mn(struct mn *mnp)
875{ 1046{
876 union uvh_rh_gam_config_mmr_u m_n_config; 1047 union uvh_rh_gam_config_mmr_u m_n_config;
877 union uvh_node_id_u node_id; 1048 union uv3h_gr0_gam_gr_config_u m_gr_config;
878 unsigned long gnode_upper, lowmem_redir_base, lowmem_redir_size;
879 int bytes, nid, cpu, lcpu, pnode, blade, i, j, m_val, n_val;
880 int gnode_extra, min_pnode = 999999, max_pnode = -1;
881 unsigned long mmr_base, present, paddr;
882 unsigned short pnode_mask;
883 unsigned char n_lshift;
884 char *hub = (is_uv1_hub() ? "UV100/1000" :
885 (is_uv2_hub() ? "UV2000/3000" :
886 (is_uv3_hub() ? "UV300" : NULL)));
887 1049
888 if (!hub) { 1050 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR);
889 pr_err("UV: Unknown/unsupported UV hub\n"); 1051 mnp->n_val = m_n_config.s.n_skt;
890 return; 1052 if (is_uv4_hub()) {
1053 mnp->m_val = 0;
1054 mnp->n_lshift = 0;
1055 } else if (is_uv3_hub()) {
1056 mnp->m_val = m_n_config.s3.m_skt;
1057 m_gr_config.v = uv_read_local_mmr(UV3H_GR0_GAM_GR_CONFIG);
1058 mnp->n_lshift = m_gr_config.s3.m_skt;
1059 } else if (is_uv2_hub()) {
1060 mnp->m_val = m_n_config.s2.m_skt;
1061 mnp->n_lshift = mnp->m_val == 40 ? 40 : 39;
1062 } else if (is_uv1_hub()) {
1063 mnp->m_val = m_n_config.s1.m_skt;
1064 mnp->n_lshift = mnp->m_val;
891 } 1065 }
892 pr_info("UV: Found %s hub\n", hub); 1066 mnp->m_shift = mnp->m_val ? 64 - mnp->m_val : 0;
1067}
893 1068
894 map_low_mmrs(); 1069void __init uv_init_hub_info(struct uv_hub_info_s *hub_info)
1070{
1071 struct mn mn = {0}; /* avoid unitialized warnings */
1072 union uvh_node_id_u node_id;
895 1073
896 m_n_config.v = uv_read_local_mmr(UVH_RH_GAM_CONFIG_MMR ); 1074 get_mn(&mn);
897 m_val = m_n_config.s.m_skt; 1075 hub_info->m_val = mn.m_val;
898 n_val = m_n_config.s.n_skt; 1076 hub_info->n_val = mn.n_val;
899 pnode_mask = (1 << n_val) - 1; 1077 hub_info->m_shift = mn.m_shift;
900 n_lshift = get_n_lshift(m_val); 1078 hub_info->n_lshift = mn.n_lshift ? mn.n_lshift : 0;
901 mmr_base = 1079
902 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) & 1080 hub_info->hub_revision = uv_hub_info->hub_revision;
903 ~UV_MMR_ENABLE; 1081 hub_info->pnode_mask = uv_cpuid.pnode_mask;
1082 hub_info->min_pnode = _min_pnode;
1083 hub_info->min_socket = _min_socket;
1084 hub_info->pnode_to_socket = _pnode_to_socket;
1085 hub_info->socket_to_node = _socket_to_node;
1086 hub_info->socket_to_pnode = _socket_to_pnode;
1087 hub_info->gr_table_len = _gr_table_len;
1088 hub_info->gr_table = _gr_table;
1089 hub_info->gpa_mask = mn.m_val ?
1090 (1UL << (mn.m_val + mn.n_val)) - 1 :
1091 (1UL << uv_cpuid.gpa_shift) - 1;
904 1092
905 node_id.v = uv_read_local_mmr(UVH_NODE_ID); 1093 node_id.v = uv_read_local_mmr(UVH_NODE_ID);
906 gnode_extra = (node_id.s.node_id & ~((1 << n_val) - 1)) >> 1; 1094 hub_info->gnode_extra =
907 gnode_upper = ((unsigned long)gnode_extra << m_val); 1095 (node_id.s.node_id & ~((1 << mn.n_val) - 1)) >> 1;
908 pr_info("UV: N:%d M:%d pnode_mask:0x%x gnode_upper/extra:0x%lx/0x%x n_lshift 0x%x\n", 1096
909 n_val, m_val, pnode_mask, gnode_upper, gnode_extra, 1097 hub_info->gnode_upper =
910 n_lshift); 1098 ((unsigned long)hub_info->gnode_extra << mn.m_val);
1099
1100 if (uv_gp_table) {
1101 hub_info->global_mmr_base = uv_gp_table->mmr_base;
1102 hub_info->global_mmr_shift = uv_gp_table->mmr_shift;
1103 hub_info->global_gru_base = uv_gp_table->gru_base;
1104 hub_info->global_gru_shift = uv_gp_table->gru_shift;
1105 hub_info->gpa_shift = uv_gp_table->gpa_shift;
1106 hub_info->gpa_mask = (1UL << hub_info->gpa_shift) - 1;
1107 } else {
1108 hub_info->global_mmr_base =
1109 uv_read_local_mmr(UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR) &
1110 ~UV_MMR_ENABLE;
1111 hub_info->global_mmr_shift = _UV_GLOBAL_MMR64_PNODE_SHIFT;
1112 }
911 1113
912 pr_info("UV: global MMR base 0x%lx\n", mmr_base); 1114 get_lowmem_redirect(
1115 &hub_info->lowmem_remap_base, &hub_info->lowmem_remap_top);
913 1116
914 for(i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) 1117 hub_info->apic_pnode_shift = uv_cpuid.socketid_shift;
915 uv_possible_blades +=
916 hweight64(uv_read_local_mmr( UVH_NODE_PRESENT_TABLE + i * 8));
917 1118
918 /* uv_num_possible_blades() is really the hub count */ 1119 /* show system specific info */
919 pr_info("UV: Found %d blades, %d hubs\n", 1120 pr_info("UV: N:%d M:%d m_shift:%d n_lshift:%d\n",
920 is_uv1_hub() ? uv_num_possible_blades() : 1121 hub_info->n_val, hub_info->m_val,
921 (uv_num_possible_blades() + 1) / 2, 1122 hub_info->m_shift, hub_info->n_lshift);
922 uv_num_possible_blades());
923 1123
924 bytes = sizeof(struct uv_blade_info) * uv_num_possible_blades(); 1124 pr_info("UV: gpa_mask/shift:0x%lx/%d pnode_mask:0x%x apic_pns:%d\n",
925 uv_blade_info = kzalloc(bytes, GFP_KERNEL); 1125 hub_info->gpa_mask, hub_info->gpa_shift,
926 BUG_ON(!uv_blade_info); 1126 hub_info->pnode_mask, hub_info->apic_pnode_shift);
927 1127
928 for (blade = 0; blade < uv_num_possible_blades(); blade++) 1128 pr_info("UV: mmr_base/shift:0x%lx/%ld gru_base/shift:0x%lx/%ld\n",
929 uv_blade_info[blade].memory_nid = -1; 1129 hub_info->global_mmr_base, hub_info->global_mmr_shift,
1130 hub_info->global_gru_base, hub_info->global_gru_shift);
930 1131
931 get_lowmem_redirect(&lowmem_redir_base, &lowmem_redir_size); 1132 pr_info("UV: gnode_upper:0x%lx gnode_extra:0x%x\n",
1133 hub_info->gnode_upper, hub_info->gnode_extra);
1134}
1135
1136static void __init decode_gam_params(unsigned long ptr)
1137{
1138 uv_gp_table = (struct uv_gam_parameters *)ptr;
1139
1140 pr_info("UV: GAM Params...\n");
1141 pr_info("UV: mmr_base/shift:0x%llx/%d gru_base/shift:0x%llx/%d gpa_shift:%d\n",
1142 uv_gp_table->mmr_base, uv_gp_table->mmr_shift,
1143 uv_gp_table->gru_base, uv_gp_table->gru_shift,
1144 uv_gp_table->gpa_shift);
1145}
1146
1147static void __init decode_gam_rng_tbl(unsigned long ptr)
1148{
1149 struct uv_gam_range_entry *gre = (struct uv_gam_range_entry *)ptr;
1150 unsigned long lgre = 0;
1151 int index = 0;
1152 int sock_min = 999999, pnode_min = 99999;
1153 int sock_max = -1, pnode_max = -1;
1154
1155 uv_gre_table = gre;
1156 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1157 if (!index) {
1158 pr_info("UV: GAM Range Table...\n");
1159 pr_info("UV: # %20s %14s %5s %4s %5s %3s %2s %3s\n",
1160 "Range", "", "Size", "Type", "NASID",
1161 "SID", "PN", "PXM");
1162 }
1163 pr_info(
1164 "UV: %2d: 0x%014lx-0x%014lx %5luG %3d %04x %02x %02x %3d\n",
1165 index++,
1166 (unsigned long)lgre << UV_GAM_RANGE_SHFT,
1167 (unsigned long)gre->limit << UV_GAM_RANGE_SHFT,
1168 ((unsigned long)(gre->limit - lgre)) >>
1169 (30 - UV_GAM_RANGE_SHFT), /* 64M -> 1G */
1170 gre->type, gre->nasid, gre->sockid,
1171 gre->pnode, gre->pxm);
1172
1173 lgre = gre->limit;
1174 if (sock_min > gre->sockid)
1175 sock_min = gre->sockid;
1176 if (sock_max < gre->sockid)
1177 sock_max = gre->sockid;
1178 if (pnode_min > gre->pnode)
1179 pnode_min = gre->pnode;
1180 if (pnode_max < gre->pnode)
1181 pnode_max = gre->pnode;
1182 }
1183 _min_socket = sock_min;
1184 _max_socket = sock_max;
1185 _min_pnode = pnode_min;
1186 _max_pnode = pnode_max;
1187 _gr_table_len = index;
1188 pr_info(
1189 "UV: GRT: %d entries, sockets(min:%x,max:%x) pnodes(min:%x,max:%x)\n",
1190 index, _min_socket, _max_socket, _min_pnode, _max_pnode);
1191}
1192
1193static void __init decode_uv_systab(void)
1194{
1195 struct uv_systab *st;
1196 int i;
1197
1198 st = uv_systab;
1199 if ((!st || st->revision < UV_SYSTAB_VERSION_UV4) && !is_uv4_hub())
1200 return;
1201 if (st->revision != UV_SYSTAB_VERSION_UV4_LATEST) {
1202 pr_crit(
1203 "UV: BIOS UVsystab version(%x) mismatch, expecting(%x)\n",
1204 st->revision, UV_SYSTAB_VERSION_UV4_LATEST);
1205 BUG();
1206 }
1207
1208 for (i = 0; st->entry[i].type != UV_SYSTAB_TYPE_UNUSED; i++) {
1209 unsigned long ptr = st->entry[i].offset;
932 1210
933 bytes = sizeof(uv_node_to_blade[0]) * num_possible_nodes(); 1211 if (!ptr)
934 uv_node_to_blade = kmalloc(bytes, GFP_KERNEL); 1212 continue;
935 BUG_ON(!uv_node_to_blade); 1213
936 memset(uv_node_to_blade, 255, bytes); 1214 ptr = ptr + (unsigned long)st;
1215
1216 switch (st->entry[i].type) {
1217 case UV_SYSTAB_TYPE_GAM_PARAMS:
1218 decode_gam_params(ptr);
1219 break;
1220
1221 case UV_SYSTAB_TYPE_GAM_RNG_TBL:
1222 decode_gam_rng_tbl(ptr);
1223 break;
1224 }
1225 }
1226}
937 1227
938 bytes = sizeof(uv_cpu_to_blade[0]) * num_possible_cpus(); 1228/*
939 uv_cpu_to_blade = kmalloc(bytes, GFP_KERNEL); 1229 * Setup physical blade translations from UVH_NODE_PRESENT_TABLE
940 BUG_ON(!uv_cpu_to_blade); 1230 * .. NB: UVH_NODE_PRESENT_TABLE is going away,
941 memset(uv_cpu_to_blade, 255, bytes); 1231 * .. being replaced by GAM Range Table
1232 */
1233static __init void boot_init_possible_blades(struct uv_hub_info_s *hub_info)
1234{
1235 int i, uv_pb = 0;
942 1236
943 blade = 0; 1237 pr_info("UV: NODE_PRESENT_DEPTH = %d\n", UVH_NODE_PRESENT_TABLE_DEPTH);
944 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) { 1238 for (i = 0; i < UVH_NODE_PRESENT_TABLE_DEPTH; i++) {
945 present = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8); 1239 unsigned long np;
946 for (j = 0; j < 64; j++) { 1240
947 if (!test_bit(j, &present)) 1241 np = uv_read_local_mmr(UVH_NODE_PRESENT_TABLE + i * 8);
948 continue; 1242 if (np)
949 pnode = (i * 64 + j) & pnode_mask; 1243 pr_info("UV: NODE_PRESENT(%d) = 0x%016lx\n", i, np);
950 uv_blade_info[blade].pnode = pnode; 1244
951 uv_blade_info[blade].nr_possible_cpus = 0; 1245 uv_pb += hweight64(np);
952 uv_blade_info[blade].nr_online_cpus = 0; 1246 }
953 spin_lock_init(&uv_blade_info[blade].nmi_lock); 1247 if (uv_possible_blades != uv_pb)
954 min_pnode = min(pnode, min_pnode); 1248 uv_possible_blades = uv_pb;
955 max_pnode = max(pnode, max_pnode); 1249}
956 blade++; 1250
1251static void __init build_socket_tables(void)
1252{
1253 struct uv_gam_range_entry *gre = uv_gre_table;
1254 int num, nump;
1255 int cpu, i, lnid;
1256 int minsock = _min_socket;
1257 int maxsock = _max_socket;
1258 int minpnode = _min_pnode;
1259 int maxpnode = _max_pnode;
1260 size_t bytes;
1261
1262 if (!gre) {
1263 if (is_uv1_hub() || is_uv2_hub() || is_uv3_hub()) {
1264 pr_info("UV: No UVsystab socket table, ignoring\n");
1265 return; /* not required */
957 } 1266 }
1267 pr_crit(
1268 "UV: Error: UVsystab address translations not available!\n");
1269 BUG();
1270 }
1271
1272 /* build socket id -> node id, pnode */
1273 num = maxsock - minsock + 1;
1274 bytes = num * sizeof(_socket_to_node[0]);
1275 _socket_to_node = kmalloc(bytes, GFP_KERNEL);
1276 _socket_to_pnode = kmalloc(bytes, GFP_KERNEL);
1277
1278 nump = maxpnode - minpnode + 1;
1279 bytes = nump * sizeof(_pnode_to_socket[0]);
1280 _pnode_to_socket = kmalloc(bytes, GFP_KERNEL);
1281 BUG_ON(!_socket_to_node || !_socket_to_pnode || !_pnode_to_socket);
1282
1283 for (i = 0; i < num; i++)
1284 _socket_to_node[i] = _socket_to_pnode[i] = SOCK_EMPTY;
1285
1286 for (i = 0; i < nump; i++)
1287 _pnode_to_socket[i] = SOCK_EMPTY;
1288
1289 /* fill in pnode/node/addr conversion list values */
1290 pr_info("UV: GAM Building socket/pnode/pxm conversion tables\n");
1291 for (; gre->type != UV_GAM_RANGE_TYPE_UNUSED; gre++) {
1292 if (gre->type == UV_GAM_RANGE_TYPE_HOLE)
1293 continue;
1294 i = gre->sockid - minsock;
1295 if (_socket_to_pnode[i] != SOCK_EMPTY)
1296 continue; /* duplicate */
1297 _socket_to_pnode[i] = gre->pnode;
1298 _socket_to_node[i] = gre->pxm;
1299
1300 i = gre->pnode - minpnode;
1301 _pnode_to_socket[i] = gre->sockid;
1302
1303 pr_info(
1304 "UV: sid:%02x type:%d nasid:%04x pn:%02x pxm:%2d pn2s:%2x\n",
1305 gre->sockid, gre->type, gre->nasid,
1306 _socket_to_pnode[gre->sockid - minsock],
1307 _socket_to_node[gre->sockid - minsock],
1308 _pnode_to_socket[gre->pnode - minpnode]);
958 } 1309 }
959 1310
960 uv_bios_init(); 1311 /* check socket -> node values */
1312 lnid = -1;
1313 for_each_present_cpu(cpu) {
1314 int nid = cpu_to_node(cpu);
1315 int apicid, sockid;
1316
1317 if (lnid == nid)
1318 continue;
1319 lnid = nid;
1320 apicid = per_cpu(x86_cpu_to_apicid, cpu);
1321 sockid = apicid >> uv_cpuid.socketid_shift;
1322 i = sockid - minsock;
1323
1324 if (nid != _socket_to_node[i]) {
1325 pr_warn(
1326 "UV: %02x: type:%d socket:%02x PXM:%02x != node:%2d\n",
1327 i, sockid, gre->type, _socket_to_node[i], nid);
1328 _socket_to_node[i] = nid;
1329 }
1330 }
1331
1332 /* Setup physical blade to pnode translation from GAM Range Table */
1333 bytes = num_possible_nodes() * sizeof(_node_to_pnode[0]);
1334 _node_to_pnode = kmalloc(bytes, GFP_KERNEL);
1335 BUG_ON(!_node_to_pnode);
1336
1337 for (lnid = 0; lnid < num_possible_nodes(); lnid++) {
1338 unsigned short sockid;
1339
1340 for (sockid = minsock; sockid <= maxsock; sockid++) {
1341 if (lnid == _socket_to_node[sockid - minsock]) {
1342 _node_to_pnode[lnid] =
1343 _socket_to_pnode[sockid - minsock];
1344 break;
1345 }
1346 }
1347 if (sockid > maxsock) {
1348 pr_err("UV: socket for node %d not found!\n", lnid);
1349 BUG();
1350 }
1351 }
1352
1353 /*
1354 * If socket id == pnode or socket id == node for all nodes,
1355 * system runs faster by removing corresponding conversion table.
1356 */
1357 pr_info("UV: Checking socket->node/pnode for identity maps\n");
1358 if (minsock == 0) {
1359 for (i = 0; i < num; i++)
1360 if (_socket_to_node[i] == SOCK_EMPTY ||
1361 i != _socket_to_node[i])
1362 break;
1363 if (i >= num) {
1364 kfree(_socket_to_node);
1365 _socket_to_node = NULL;
1366 pr_info("UV: 1:1 socket_to_node table removed\n");
1367 }
1368 }
1369 if (minsock == minpnode) {
1370 for (i = 0; i < num; i++)
1371 if (_socket_to_pnode[i] != SOCK_EMPTY &&
1372 _socket_to_pnode[i] != i + minpnode)
1373 break;
1374 if (i >= num) {
1375 kfree(_socket_to_pnode);
1376 _socket_to_pnode = NULL;
1377 pr_info("UV: 1:1 socket_to_pnode table removed\n");
1378 }
1379 }
1380}
1381
1382void __init uv_system_init(void)
1383{
1384 struct uv_hub_info_s hub_info = {0};
1385 int bytes, cpu, nodeid;
1386 unsigned short min_pnode = 9999, max_pnode = 0;
1387 char *hub = is_uv4_hub() ? "UV400" :
1388 is_uv3_hub() ? "UV300" :
1389 is_uv2_hub() ? "UV2000/3000" :
1390 is_uv1_hub() ? "UV100/1000" : NULL;
1391
1392 if (!hub) {
1393 pr_err("UV: Unknown/unsupported UV hub\n");
1394 return;
1395 }
1396 pr_info("UV: Found %s hub\n", hub);
1397
1398 map_low_mmrs();
1399
1400 uv_bios_init(); /* get uv_systab for decoding */
1401 decode_uv_systab();
1402 build_socket_tables();
1403 build_uv_gr_table();
1404 uv_init_hub_info(&hub_info);
1405 uv_possible_blades = num_possible_nodes();
1406 if (!_node_to_pnode)
1407 boot_init_possible_blades(&hub_info);
1408
1409 /* uv_num_possible_blades() is really the hub count */
1410 pr_info("UV: Found %d hubs, %d nodes, %d cpus\n",
1411 uv_num_possible_blades(),
1412 num_possible_nodes(),
1413 num_possible_cpus());
1414
961 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id, 1415 uv_bios_get_sn_info(0, &uv_type, &sn_partition_id, &sn_coherency_id,
962 &sn_region_size, &system_serial_number); 1416 &sn_region_size, &system_serial_number);
1417 hub_info.coherency_domain_number = sn_coherency_id;
963 uv_rtc_init(); 1418 uv_rtc_init();
964 1419
965 for_each_present_cpu(cpu) { 1420 bytes = sizeof(void *) * uv_num_possible_blades();
966 int apicid = per_cpu(x86_cpu_to_apicid, cpu); 1421 __uv_hub_info_list = kzalloc(bytes, GFP_KERNEL);
1422 BUG_ON(!__uv_hub_info_list);
967 1423
968 nid = cpu_to_node(cpu); 1424 bytes = sizeof(struct uv_hub_info_s);
969 /* 1425 for_each_node(nodeid) {
970 * apic_pnode_shift must be set before calling uv_apicid_to_pnode(); 1426 struct uv_hub_info_s *new_hub;
971 */
972 uv_cpu_hub_info(cpu)->pnode_mask = pnode_mask;
973 uv_cpu_hub_info(cpu)->apic_pnode_shift = uvh_apicid.s.pnode_shift;
974 uv_cpu_hub_info(cpu)->hub_revision = uv_hub_info->hub_revision;
975 1427
976 uv_cpu_hub_info(cpu)->m_shift = 64 - m_val; 1428 if (__uv_hub_info_list[nodeid]) {
977 uv_cpu_hub_info(cpu)->n_lshift = n_lshift; 1429 pr_err("UV: Node %d UV HUB already initialized!?\n",
1430 nodeid);
1431 BUG();
1432 }
1433
1434 /* Allocate new per hub info list */
1435 new_hub = (nodeid == 0) ?
1436 &uv_hub_info_node0 :
1437 kzalloc_node(bytes, GFP_KERNEL, nodeid);
1438 BUG_ON(!new_hub);
1439 __uv_hub_info_list[nodeid] = new_hub;
1440 new_hub = uv_hub_info_list(nodeid);
1441 BUG_ON(!new_hub);
1442 *new_hub = hub_info;
1443
1444 /* Use information from GAM table if available */
1445 if (_node_to_pnode)
1446 new_hub->pnode = _node_to_pnode[nodeid];
1447 else /* Fill in during cpu loop */
1448 new_hub->pnode = 0xffff;
1449 new_hub->numa_blade_id = uv_node_to_blade_id(nodeid);
1450 new_hub->memory_nid = -1;
1451 new_hub->nr_possible_cpus = 0;
1452 new_hub->nr_online_cpus = 0;
1453 }
978 1454
1455 /* Initialize per cpu info */
1456 for_each_possible_cpu(cpu) {
1457 int apicid = per_cpu(x86_cpu_to_apicid, cpu);
1458 int numa_node_id;
1459 unsigned short pnode;
1460
1461 nodeid = cpu_to_node(cpu);
1462 numa_node_id = numa_cpu_node(cpu);
979 pnode = uv_apicid_to_pnode(apicid); 1463 pnode = uv_apicid_to_pnode(apicid);
980 blade = boot_pnode_to_blade(pnode); 1464
981 lcpu = uv_blade_info[blade].nr_possible_cpus; 1465 uv_cpu_info_per(cpu)->p_uv_hub_info = uv_hub_info_list(nodeid);
982 uv_blade_info[blade].nr_possible_cpus++; 1466 uv_cpu_info_per(cpu)->blade_cpu_id =
983 1467 uv_cpu_hub_info(cpu)->nr_possible_cpus++;
984 /* Any node on the blade, else will contain -1. */ 1468 if (uv_cpu_hub_info(cpu)->memory_nid == -1)
985 uv_blade_info[blade].memory_nid = nid; 1469 uv_cpu_hub_info(cpu)->memory_nid = cpu_to_node(cpu);
986 1470 if (nodeid != numa_node_id && /* init memoryless node */
987 uv_cpu_hub_info(cpu)->lowmem_remap_base = lowmem_redir_base; 1471 uv_hub_info_list(numa_node_id)->pnode == 0xffff)
988 uv_cpu_hub_info(cpu)->lowmem_remap_top = lowmem_redir_size; 1472 uv_hub_info_list(numa_node_id)->pnode = pnode;
989 uv_cpu_hub_info(cpu)->m_val = m_val; 1473 else if (uv_cpu_hub_info(cpu)->pnode == 0xffff)
990 uv_cpu_hub_info(cpu)->n_val = n_val; 1474 uv_cpu_hub_info(cpu)->pnode = pnode;
991 uv_cpu_hub_info(cpu)->numa_blade_id = blade; 1475 uv_cpu_scir_info(cpu)->offset = uv_scir_offset(apicid);
992 uv_cpu_hub_info(cpu)->blade_processor_id = lcpu;
993 uv_cpu_hub_info(cpu)->pnode = pnode;
994 uv_cpu_hub_info(cpu)->gpa_mask = (1UL << (m_val + n_val)) - 1;
995 uv_cpu_hub_info(cpu)->gnode_upper = gnode_upper;
996 uv_cpu_hub_info(cpu)->gnode_extra = gnode_extra;
997 uv_cpu_hub_info(cpu)->global_mmr_base = mmr_base;
998 uv_cpu_hub_info(cpu)->coherency_domain_number = sn_coherency_id;
999 uv_cpu_hub_info(cpu)->scir.offset = uv_scir_offset(apicid);
1000 uv_node_to_blade[nid] = blade;
1001 uv_cpu_to_blade[cpu] = blade;
1002 } 1476 }
1003 1477
1004 /* Add blade/pnode info for nodes without cpus */ 1478 for_each_node(nodeid) {
1005 for_each_online_node(nid) { 1479 unsigned short pnode = uv_hub_info_list(nodeid)->pnode;
1006 if (uv_node_to_blade[nid] >= 0) 1480
1007 continue; 1481 /* Add pnode info for pre-GAM list nodes without cpus */
1008 paddr = node_start_pfn(nid) << PAGE_SHIFT; 1482 if (pnode == 0xffff) {
1009 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr)); 1483 unsigned long paddr;
1010 blade = boot_pnode_to_blade(pnode); 1484
1011 uv_node_to_blade[nid] = blade; 1485 paddr = node_start_pfn(nodeid) << PAGE_SHIFT;
1486 pnode = uv_gpa_to_pnode(uv_soc_phys_ram_to_gpa(paddr));
1487 uv_hub_info_list(nodeid)->pnode = pnode;
1488 }
1489 min_pnode = min(pnode, min_pnode);
1490 max_pnode = max(pnode, max_pnode);
1491 pr_info("UV: UVHUB node:%2d pn:%02x nrcpus:%d\n",
1492 nodeid,
1493 uv_hub_info_list(nodeid)->pnode,
1494 uv_hub_info_list(nodeid)->nr_possible_cpus);
1012 } 1495 }
1013 1496
1497 pr_info("UV: min_pnode:%02x max_pnode:%02x\n", min_pnode, max_pnode);
1014 map_gru_high(max_pnode); 1498 map_gru_high(max_pnode);
1015 map_mmr_high(max_pnode); 1499 map_mmr_high(max_pnode);
1016 map_mmioh_high(min_pnode, max_pnode); 1500 map_mmioh_high(min_pnode, max_pnode);
diff --git a/arch/x86/platform/uv/bios_uv.c b/arch/x86/platform/uv/bios_uv.c
index 1584cbed0dce..815fec6e05e2 100644
--- a/arch/x86/platform/uv/bios_uv.c
+++ b/arch/x86/platform/uv/bios_uv.c
@@ -21,19 +21,20 @@
21 21
22#include <linux/efi.h> 22#include <linux/efi.h>
23#include <linux/export.h> 23#include <linux/export.h>
24#include <linux/slab.h>
24#include <asm/efi.h> 25#include <asm/efi.h>
25#include <linux/io.h> 26#include <linux/io.h>
26#include <asm/uv/bios.h> 27#include <asm/uv/bios.h>
27#include <asm/uv/uv_hub.h> 28#include <asm/uv/uv_hub.h>
28 29
29static struct uv_systab uv_systab; 30struct uv_systab *uv_systab;
30 31
31s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5) 32s64 uv_bios_call(enum uv_bios_cmd which, u64 a1, u64 a2, u64 a3, u64 a4, u64 a5)
32{ 33{
33 struct uv_systab *tab = &uv_systab; 34 struct uv_systab *tab = uv_systab;
34 s64 ret; 35 s64 ret;
35 36
36 if (!tab->function) 37 if (!tab || !tab->function)
37 /* 38 /*
38 * BIOS does not support UV systab 39 * BIOS does not support UV systab
39 */ 40 */
@@ -183,34 +184,31 @@ int uv_bios_set_legacy_vga_target(bool decode, int domain, int bus)
183} 184}
184EXPORT_SYMBOL_GPL(uv_bios_set_legacy_vga_target); 185EXPORT_SYMBOL_GPL(uv_bios_set_legacy_vga_target);
185 186
186
187#ifdef CONFIG_EFI 187#ifdef CONFIG_EFI
188void uv_bios_init(void) 188void uv_bios_init(void)
189{ 189{
190 struct uv_systab *tab; 190 uv_systab = NULL;
191 191 if ((efi.uv_systab == EFI_INVALID_TABLE_ADDR) || !efi.uv_systab) {
192 if ((efi.uv_systab == EFI_INVALID_TABLE_ADDR) || 192 pr_crit("UV: UVsystab: missing\n");
193 (efi.uv_systab == (unsigned long)NULL)) {
194 printk(KERN_CRIT "No EFI UV System Table.\n");
195 uv_systab.function = (unsigned long)NULL;
196 return; 193 return;
197 } 194 }
198 195
199 tab = (struct uv_systab *)ioremap(efi.uv_systab, 196 uv_systab = ioremap(efi.uv_systab, sizeof(struct uv_systab));
200 sizeof(struct uv_systab)); 197 if (!uv_systab || strncmp(uv_systab->signature, UV_SYSTAB_SIG, 4)) {
201 if (strncmp(tab->signature, "UVST", 4) != 0) 198 pr_err("UV: UVsystab: bad signature!\n");
202 printk(KERN_ERR "bad signature in UV system table!"); 199 iounmap(uv_systab);
203 200 return;
204 /* 201 }
205 * Copy table to permanent spot for later use.
206 */
207 memcpy(&uv_systab, tab, sizeof(struct uv_systab));
208 iounmap(tab);
209 202
210 printk(KERN_INFO "EFI UV System Table Revision %d\n", 203 if (uv_systab->revision >= UV_SYSTAB_VERSION_UV4) {
211 uv_systab.revision); 204 iounmap(uv_systab);
205 uv_systab = ioremap(efi.uv_systab, uv_systab->size);
206 if (!uv_systab) {
207 pr_err("UV: UVsystab: ioremap(%d) failed!\n",
208 uv_systab->size);
209 return;
210 }
211 }
212 pr_info("UV: UVsystab: Revision:%x\n", uv_systab->revision);
212} 213}
213#else /* !CONFIG_EFI */
214
215void uv_bios_init(void) { }
216#endif 214#endif
diff --git a/arch/x86/platform/uv/tlb_uv.c b/arch/x86/platform/uv/tlb_uv.c
index 3b6ec42718e4..fdb4d42b4ce5 100644
--- a/arch/x86/platform/uv/tlb_uv.c
+++ b/arch/x86/platform/uv/tlb_uv.c
@@ -37,7 +37,7 @@ static int timeout_base_ns[] = {
37}; 37};
38 38
39static int timeout_us; 39static int timeout_us;
40static int nobau; 40static bool nobau = true;
41static int nobau_perm; 41static int nobau_perm;
42static cycles_t congested_cycles; 42static cycles_t congested_cycles;
43 43
@@ -106,13 +106,28 @@ static char *stat_description[] = {
106 "enable: number times use of the BAU was re-enabled" 106 "enable: number times use of the BAU was re-enabled"
107}; 107};
108 108
109static int __init 109static int __init setup_bau(char *arg)
110setup_nobau(char *arg)
111{ 110{
112 nobau = 1; 111 int result;
112
113 if (!arg)
114 return -EINVAL;
115
116 result = strtobool(arg, &nobau);
117 if (result)
118 return result;
119
120 /* we need to flip the logic here, so that bau=y sets nobau to false */
121 nobau = !nobau;
122
123 if (!nobau)
124 pr_info("UV BAU Enabled\n");
125 else
126 pr_info("UV BAU Disabled\n");
127
113 return 0; 128 return 0;
114} 129}
115early_param("nobau", setup_nobau); 130early_param("bau", setup_bau);
116 131
117/* base pnode in this partition */ 132/* base pnode in this partition */
118static int uv_base_pnode __read_mostly; 133static int uv_base_pnode __read_mostly;
@@ -131,10 +146,10 @@ set_bau_on(void)
131 pr_info("BAU not initialized; cannot be turned on\n"); 146 pr_info("BAU not initialized; cannot be turned on\n");
132 return; 147 return;
133 } 148 }
134 nobau = 0; 149 nobau = false;
135 for_each_present_cpu(cpu) { 150 for_each_present_cpu(cpu) {
136 bcp = &per_cpu(bau_control, cpu); 151 bcp = &per_cpu(bau_control, cpu);
137 bcp->nobau = 0; 152 bcp->nobau = false;
138 } 153 }
139 pr_info("BAU turned on\n"); 154 pr_info("BAU turned on\n");
140 return; 155 return;
@@ -146,10 +161,10 @@ set_bau_off(void)
146 int cpu; 161 int cpu;
147 struct bau_control *bcp; 162 struct bau_control *bcp;
148 163
149 nobau = 1; 164 nobau = true;
150 for_each_present_cpu(cpu) { 165 for_each_present_cpu(cpu) {
151 bcp = &per_cpu(bau_control, cpu); 166 bcp = &per_cpu(bau_control, cpu);
152 bcp->nobau = 1; 167 bcp->nobau = true;
153 } 168 }
154 pr_info("BAU turned off\n"); 169 pr_info("BAU turned off\n");
155 return; 170 return;
@@ -1886,7 +1901,7 @@ static void __init init_per_cpu_tunables(void)
1886 bcp = &per_cpu(bau_control, cpu); 1901 bcp = &per_cpu(bau_control, cpu);
1887 bcp->baudisabled = 0; 1902 bcp->baudisabled = 0;
1888 if (nobau) 1903 if (nobau)
1889 bcp->nobau = 1; 1904 bcp->nobau = true;
1890 bcp->statp = &per_cpu(ptcstats, cpu); 1905 bcp->statp = &per_cpu(ptcstats, cpu);
1891 /* time interval to catch a hardware stay-busy bug */ 1906 /* time interval to catch a hardware stay-busy bug */
1892 bcp->timeout_interval = usec_2_cycles(2*timeout_us); 1907 bcp->timeout_interval = usec_2_cycles(2*timeout_us);
@@ -2025,7 +2040,8 @@ static int scan_sock(struct socket_desc *sdp, struct uvhub_desc *bdp,
2025 return 1; 2040 return 1;
2026 } 2041 }
2027 bcp->uvhub_master = *hmasterp; 2042 bcp->uvhub_master = *hmasterp;
2028 bcp->uvhub_cpu = uv_cpu_hub_info(cpu)->blade_processor_id; 2043 bcp->uvhub_cpu = uv_cpu_blade_processor_id(cpu);
2044
2029 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) { 2045 if (bcp->uvhub_cpu >= MAX_CPUS_PER_UVHUB) {
2030 printk(KERN_EMERG "%d cpus per uvhub invalid\n", 2046 printk(KERN_EMERG "%d cpus per uvhub invalid\n",
2031 bcp->uvhub_cpu); 2047 bcp->uvhub_cpu);
diff --git a/arch/x86/platform/uv/uv_sysfs.c b/arch/x86/platform/uv/uv_sysfs.c
index 5d4ba301e776..e9da9ebd924a 100644
--- a/arch/x86/platform/uv/uv_sysfs.c
+++ b/arch/x86/platform/uv/uv_sysfs.c
@@ -34,7 +34,7 @@ static ssize_t partition_id_show(struct kobject *kobj,
34static ssize_t coherence_id_show(struct kobject *kobj, 34static ssize_t coherence_id_show(struct kobject *kobj,
35 struct kobj_attribute *attr, char *buf) 35 struct kobj_attribute *attr, char *buf)
36{ 36{
37 return snprintf(buf, PAGE_SIZE, "%ld\n", partition_coherence_id()); 37 return snprintf(buf, PAGE_SIZE, "%ld\n", uv_partition_coherence_id());
38} 38}
39 39
40static struct kobj_attribute partition_id_attr = 40static struct kobj_attribute partition_id_attr =
diff --git a/arch/x86/platform/uv/uv_time.c b/arch/x86/platform/uv/uv_time.c
index 2b158a9fa1d7..b333fc45f9ec 100644
--- a/arch/x86/platform/uv/uv_time.c
+++ b/arch/x86/platform/uv/uv_time.c
@@ -165,7 +165,7 @@ static __init int uv_rtc_allocate_timers(void)
165 for_each_present_cpu(cpu) { 165 for_each_present_cpu(cpu) {
166 int nid = cpu_to_node(cpu); 166 int nid = cpu_to_node(cpu);
167 int bid = uv_cpu_to_blade_id(cpu); 167 int bid = uv_cpu_to_blade_id(cpu);
168 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 168 int bcpu = uv_cpu_blade_processor_id(cpu);
169 struct uv_rtc_timer_head *head = blade_info[bid]; 169 struct uv_rtc_timer_head *head = blade_info[bid];
170 170
171 if (!head) { 171 if (!head) {
@@ -226,7 +226,7 @@ static int uv_rtc_set_timer(int cpu, u64 expires)
226 int pnode = uv_cpu_to_pnode(cpu); 226 int pnode = uv_cpu_to_pnode(cpu);
227 int bid = uv_cpu_to_blade_id(cpu); 227 int bid = uv_cpu_to_blade_id(cpu);
228 struct uv_rtc_timer_head *head = blade_info[bid]; 228 struct uv_rtc_timer_head *head = blade_info[bid];
229 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 229 int bcpu = uv_cpu_blade_processor_id(cpu);
230 u64 *t = &head->cpu[bcpu].expires; 230 u64 *t = &head->cpu[bcpu].expires;
231 unsigned long flags; 231 unsigned long flags;
232 int next_cpu; 232 int next_cpu;
@@ -262,7 +262,7 @@ static int uv_rtc_unset_timer(int cpu, int force)
262 int pnode = uv_cpu_to_pnode(cpu); 262 int pnode = uv_cpu_to_pnode(cpu);
263 int bid = uv_cpu_to_blade_id(cpu); 263 int bid = uv_cpu_to_blade_id(cpu);
264 struct uv_rtc_timer_head *head = blade_info[bid]; 264 struct uv_rtc_timer_head *head = blade_info[bid];
265 int bcpu = uv_cpu_hub_info(cpu)->blade_processor_id; 265 int bcpu = uv_cpu_blade_processor_id(cpu);
266 u64 *t = &head->cpu[bcpu].expires; 266 u64 *t = &head->cpu[bcpu].expires;
267 unsigned long flags; 267 unsigned long flags;
268 int rc = 0; 268 int rc = 0;
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-24 11:04:55 -0500