diff options
Diffstat (limited to 'arch')
272 files changed, 1339 insertions, 13458 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d31c500653a2..31b17f3fe2b4 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig | |||
@@ -239,13 +239,6 @@ config ARM_PATCH_PHYS_VIRT | |||
239 | this feature (eg, building a kernel for a single machine) and | 239 | this feature (eg, building a kernel for a single machine) and |
240 | you need to shrink the kernel to the minimal size. | 240 | you need to shrink the kernel to the minimal size. |
241 | 241 | ||
242 | config NEED_MACH_GPIO_H | ||
243 | bool | ||
244 | help | ||
245 | Select this when mach/gpio.h is required to provide special | ||
246 | definitions for this platform. The need for mach/gpio.h should | ||
247 | be avoided when possible. | ||
248 | |||
249 | config NEED_MACH_IO_H | 242 | config NEED_MACH_IO_H |
250 | bool | 243 | bool |
251 | help | 244 | help |
@@ -334,7 +327,6 @@ config ARCH_INTEGRATOR | |||
334 | select HAVE_TCM | 327 | select HAVE_TCM |
335 | select ICST | 328 | select ICST |
336 | select MULTI_IRQ_HANDLER | 329 | select MULTI_IRQ_HANDLER |
337 | select NEED_MACH_MEMORY_H | ||
338 | select PLAT_VERSATILE | 330 | select PLAT_VERSATILE |
339 | select SPARSE_IRQ | 331 | select SPARSE_IRQ |
340 | select USE_OF | 332 | select USE_OF |
@@ -354,7 +346,6 @@ config ARCH_REALVIEW | |||
354 | select ICST | 346 | select ICST |
355 | select NEED_MACH_MEMORY_H | 347 | select NEED_MACH_MEMORY_H |
356 | select PLAT_VERSATILE | 348 | select PLAT_VERSATILE |
357 | select PLAT_VERSATILE_CLCD | ||
358 | help | 349 | help |
359 | This enables support for ARM Ltd RealView boards. | 350 | This enables support for ARM Ltd RealView boards. |
360 | 351 | ||
@@ -369,7 +360,6 @@ config ARCH_VERSATILE | |||
369 | select HAVE_MACH_CLKDEV | 360 | select HAVE_MACH_CLKDEV |
370 | select ICST | 361 | select ICST |
371 | select PLAT_VERSATILE | 362 | select PLAT_VERSATILE |
372 | select PLAT_VERSATILE_CLCD | ||
373 | select PLAT_VERSATILE_CLOCK | 363 | select PLAT_VERSATILE_CLOCK |
374 | select VERSATILE_FPGA_IRQ | 364 | select VERSATILE_FPGA_IRQ |
375 | help | 365 | help |
@@ -772,42 +762,6 @@ config ARCH_S3C64XX | |||
772 | help | 762 | help |
773 | Samsung S3C64XX series based systems | 763 | Samsung S3C64XX series based systems |
774 | 764 | ||
775 | config ARCH_S5P64X0 | ||
776 | bool "Samsung S5P6440 S5P6450" | ||
777 | select ATAGS | ||
778 | select CLKDEV_LOOKUP | ||
779 | select CLKSRC_SAMSUNG_PWM | ||
780 | select CPU_V6 | ||
781 | select GENERIC_CLOCKEVENTS | ||
782 | select GPIO_SAMSUNG | ||
783 | select HAVE_S3C2410_I2C if I2C | ||
784 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | ||
785 | select HAVE_S3C_RTC if RTC_CLASS | ||
786 | select NEED_MACH_GPIO_H | ||
787 | select SAMSUNG_ATAGS | ||
788 | select SAMSUNG_WDT_RESET | ||
789 | help | ||
790 | Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440, | ||
791 | SMDK6450. | ||
792 | |||
793 | config ARCH_S5PC100 | ||
794 | bool "Samsung S5PC100" | ||
795 | select ARCH_REQUIRE_GPIOLIB | ||
796 | select ATAGS | ||
797 | select CLKDEV_LOOKUP | ||
798 | select CLKSRC_SAMSUNG_PWM | ||
799 | select CPU_V7 | ||
800 | select GENERIC_CLOCKEVENTS | ||
801 | select GPIO_SAMSUNG | ||
802 | select HAVE_S3C2410_I2C if I2C | ||
803 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | ||
804 | select HAVE_S3C_RTC if RTC_CLASS | ||
805 | select NEED_MACH_GPIO_H | ||
806 | select SAMSUNG_ATAGS | ||
807 | select SAMSUNG_WDT_RESET | ||
808 | help | ||
809 | Samsung S5PC100 series based systems | ||
810 | |||
811 | config ARCH_S5PV210 | 765 | config ARCH_S5PV210 |
812 | bool "Samsung S5PV210/S5PC110" | 766 | bool "Samsung S5PV210/S5PC110" |
813 | select ARCH_HAS_HOLES_MEMORYMODEL | 767 | select ARCH_HAS_HOLES_MEMORYMODEL |
@@ -821,7 +775,6 @@ config ARCH_S5PV210 | |||
821 | select HAVE_S3C2410_I2C if I2C | 775 | select HAVE_S3C2410_I2C if I2C |
822 | select HAVE_S3C2410_WATCHDOG if WATCHDOG | 776 | select HAVE_S3C2410_WATCHDOG if WATCHDOG |
823 | select HAVE_S3C_RTC if RTC_CLASS | 777 | select HAVE_S3C_RTC if RTC_CLASS |
824 | select NEED_MACH_GPIO_H | ||
825 | select NEED_MACH_MEMORY_H | 778 | select NEED_MACH_MEMORY_H |
826 | select SAMSUNG_ATAGS | 779 | select SAMSUNG_ATAGS |
827 | help | 780 | help |
@@ -1018,10 +971,6 @@ source "arch/arm/mach-s3c24xx/Kconfig" | |||
1018 | 971 | ||
1019 | source "arch/arm/mach-s3c64xx/Kconfig" | 972 | source "arch/arm/mach-s3c64xx/Kconfig" |
1020 | 973 | ||
1021 | source "arch/arm/mach-s5p64x0/Kconfig" | ||
1022 | |||
1023 | source "arch/arm/mach-s5pc100/Kconfig" | ||
1024 | |||
1025 | source "arch/arm/mach-s5pv210/Kconfig" | 974 | source "arch/arm/mach-s5pv210/Kconfig" |
1026 | 975 | ||
1027 | source "arch/arm/mach-exynos/Kconfig" | 976 | source "arch/arm/mach-exynos/Kconfig" |
@@ -1583,7 +1532,7 @@ source kernel/Kconfig.preempt | |||
1583 | 1532 | ||
1584 | config HZ_FIXED | 1533 | config HZ_FIXED |
1585 | int | 1534 | int |
1586 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ | 1535 | default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \ |
1587 | ARCH_S5PV210 || ARCH_EXYNOS4 | 1536 | ARCH_S5PV210 || ARCH_EXYNOS4 |
1588 | default AT91_TIMER_HZ if ARCH_AT91 | 1537 | default AT91_TIMER_HZ if ARCH_AT91 |
1589 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY | 1538 | default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY |
@@ -2208,7 +2157,6 @@ menu "Power management options" | |||
2208 | source "kernel/power/Kconfig" | 2157 | source "kernel/power/Kconfig" |
2209 | 2158 | ||
2210 | config ARCH_SUSPEND_POSSIBLE | 2159 | config ARCH_SUSPEND_POSSIBLE |
2211 | depends on !ARCH_S5PC100 | ||
2212 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ | 2160 | depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ |
2213 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK | 2161 | CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK |
2214 | def_bool y | 2162 | def_bool y |
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index 8f90595069a1..b24b5dc720e4 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug | |||
@@ -617,53 +617,41 @@ choice | |||
617 | depends on PLAT_SAMSUNG | 617 | depends on PLAT_SAMSUNG |
618 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS | 618 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS |
619 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX | 619 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX |
620 | bool "Use S3C UART 0 for low-level debug" | 620 | bool "Use Samsung S3C UART 0 for low-level debug" |
621 | help | 621 | help |
622 | Say Y here if you want the debug print routines to direct | 622 | Say Y here if you want the debug print routines to direct |
623 | their output to UART 0. The port must have been initialised | 623 | their output to UART 0. The port must have been initialised |
624 | by the boot-loader before use. | 624 | by the boot-loader before use. |
625 | 625 | ||
626 | The uncompressor code port configuration is now handled | ||
627 | by CONFIG_S3C_LOWLEVEL_UART_PORT. | ||
628 | |||
629 | config DEBUG_S3C_UART1 | 626 | config DEBUG_S3C_UART1 |
630 | depends on PLAT_SAMSUNG | 627 | depends on PLAT_SAMSUNG |
631 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS | 628 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS |
632 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX | 629 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX |
633 | bool "Use S3C UART 1 for low-level debug" | 630 | bool "Use Samsung S3C UART 1 for low-level debug" |
634 | help | 631 | help |
635 | Say Y here if you want the debug print routines to direct | 632 | Say Y here if you want the debug print routines to direct |
636 | their output to UART 1. The port must have been initialised | 633 | their output to UART 1. The port must have been initialised |
637 | by the boot-loader before use. | 634 | by the boot-loader before use. |
638 | 635 | ||
639 | The uncompressor code port configuration is now handled | ||
640 | by CONFIG_S3C_LOWLEVEL_UART_PORT. | ||
641 | |||
642 | config DEBUG_S3C_UART2 | 636 | config DEBUG_S3C_UART2 |
643 | depends on PLAT_SAMSUNG | 637 | depends on PLAT_SAMSUNG |
644 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS | 638 | select DEBUG_EXYNOS_UART if ARCH_EXYNOS |
645 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX | 639 | select DEBUG_S3C24XX_UART if ARCH_S3C24XX |
646 | bool "Use S3C UART 2 for low-level debug" | 640 | bool "Use Samsung S3C UART 2 for low-level debug" |
647 | help | 641 | help |
648 | Say Y here if you want the debug print routines to direct | 642 | Say Y here if you want the debug print routines to direct |
649 | their output to UART 2. The port must have been initialised | 643 | their output to UART 2. The port must have been initialised |
650 | by the boot-loader before use. | 644 | by the boot-loader before use. |
651 | 645 | ||
652 | The uncompressor code port configuration is now handled | ||
653 | by CONFIG_S3C_LOWLEVEL_UART_PORT. | ||
654 | |||
655 | config DEBUG_S3C_UART3 | 646 | config DEBUG_S3C_UART3 |
656 | depends on PLAT_SAMSUNG && ARCH_EXYNOS | 647 | depends on PLAT_SAMSUNG && ARCH_EXYNOS |
657 | select DEBUG_EXYNOS_UART | 648 | select DEBUG_EXYNOS_UART |
658 | bool "Use S3C UART 3 for low-level debug" | 649 | bool "Use Samsung S3C UART 3 for low-level debug" |
659 | help | 650 | help |
660 | Say Y here if you want the debug print routines to direct | 651 | Say Y here if you want the debug print routines to direct |
661 | their output to UART 3. The port must have been initialised | 652 | their output to UART 3. The port must have been initialised |
662 | by the boot-loader before use. | 653 | by the boot-loader before use. |
663 | 654 | ||
664 | The uncompressor code port configuration is now handled | ||
665 | by CONFIG_S3C_LOWLEVEL_UART_PORT. | ||
666 | |||
667 | config DEBUG_S3C2410_UART0 | 655 | config DEBUG_S3C2410_UART0 |
668 | depends on ARCH_S3C24XX | 656 | depends on ARCH_S3C24XX |
669 | select DEBUG_S3C2410_UART | 657 | select DEBUG_S3C2410_UART |
@@ -991,6 +979,7 @@ config DEBUG_STI_UART | |||
991 | config DEBUG_LL_INCLUDE | 979 | config DEBUG_LL_INCLUDE |
992 | string | 980 | string |
993 | default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 | 981 | default "debug/8250.S" if DEBUG_LL_UART_8250 || DEBUG_UART_8250 |
982 | default "debug/clps711x.S" if DEBUG_CLPS711X_UART1 || DEBUG_CLPS711X_UART2 | ||
994 | default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X | 983 | default "debug/pl01x.S" if DEBUG_LL_UART_PL01X || DEBUG_UART_PL01X |
995 | default "debug/exynos.S" if DEBUG_EXYNOS_UART | 984 | default "debug/exynos.S" if DEBUG_EXYNOS_UART |
996 | default "debug/efm32.S" if DEBUG_LL_UART_EFM32 | 985 | default "debug/efm32.S" if DEBUG_LL_UART_EFM32 |
diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 718913dfe815..1e42de45110b 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile | |||
@@ -190,8 +190,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip | |||
190 | machine-$(CONFIG_ARCH_RPC) += rpc | 190 | machine-$(CONFIG_ARCH_RPC) += rpc |
191 | machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx | 191 | machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx |
192 | machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx | 192 | machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx |
193 | machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0 | ||
194 | machine-$(CONFIG_ARCH_S5PC100) += s5pc100 | ||
195 | machine-$(CONFIG_ARCH_S5PV210) += s5pv210 | 193 | machine-$(CONFIG_ARCH_S5PV210) += s5pv210 |
196 | machine-$(CONFIG_ARCH_SA1100) += sa1100 | 194 | machine-$(CONFIG_ARCH_SA1100) += sa1100 |
197 | machine-$(CONFIG_ARCH_SHMOBILE) += shmobile | 195 | machine-$(CONFIG_ARCH_SHMOBILE) += shmobile |
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi index e37985fa10e2..00eeed3721b6 100644 --- a/arch/arm/boot/dts/emev2.dtsi +++ b/arch/arm/boot/dts/emev2.dtsi | |||
@@ -31,11 +31,13 @@ | |||
31 | device_type = "cpu"; | 31 | device_type = "cpu"; |
32 | compatible = "arm,cortex-a9"; | 32 | compatible = "arm,cortex-a9"; |
33 | reg = <0>; | 33 | reg = <0>; |
34 | clock-frequency = <533000000>; | ||
34 | }; | 35 | }; |
35 | cpu@1 { | 36 | cpu@1 { |
36 | device_type = "cpu"; | 37 | device_type = "cpu"; |
37 | compatible = "arm,cortex-a9"; | 38 | compatible = "arm,cortex-a9"; |
38 | reg = <1>; | 39 | reg = <1>; |
40 | clock-frequency = <533000000>; | ||
39 | }; | 41 | }; |
40 | }; | 42 | }; |
41 | 43 | ||
diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index b10e6351da53..cf06e32ee108 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts | |||
@@ -8,6 +8,7 @@ | |||
8 | / { | 8 | / { |
9 | model = "ARM Integrator/AP"; | 9 | model = "ARM Integrator/AP"; |
10 | compatible = "arm,integrator-ap"; | 10 | compatible = "arm,integrator-ap"; |
11 | dma-ranges = <0x80000000 0x0 0x80000000>; | ||
11 | 12 | ||
12 | aliases { | 13 | aliases { |
13 | arm,timer-primary = &timer2; | 14 | arm,timer-primary = &timer2; |
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index a4ed54988866..8eee6fbef7ad 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi | |||
@@ -985,6 +985,66 @@ | |||
985 | dma-names = "audio_tx"; | 985 | dma-names = "audio_tx"; |
986 | }; | 986 | }; |
987 | }; | 987 | }; |
988 | |||
989 | abb_mpu: regulator-abb-mpu { | ||
990 | compatible = "ti,abb-v2"; | ||
991 | regulator-name = "abb_mpu"; | ||
992 | #address-cells = <0>; | ||
993 | #size-cells = <0>; | ||
994 | clocks = <&sys_clkin>; | ||
995 | ti,settling-time = <50>; | ||
996 | ti,clock-cycles = <16>; | ||
997 | |||
998 | reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>, | ||
999 | <0x4a0021c4 0x8>, <0x4ae0c318 0x4>; | ||
1000 | reg-names = "base-address", "int-address", | ||
1001 | "efuse-address", "ldo-address"; | ||
1002 | ti,tranxdone-status-mask = <0x80>; | ||
1003 | /* LDOVBBMPU_MUX_CTRL */ | ||
1004 | ti,ldovbb-override-mask = <0x400>; | ||
1005 | /* LDOVBBMPU_VSET_OUT */ | ||
1006 | ti,ldovbb-vset-mask = <0x1F>; | ||
1007 | |||
1008 | /* | ||
1009 | * NOTE: only FBB mode used but actual vset will | ||
1010 | * determine final biasing | ||
1011 | */ | ||
1012 | ti,abb_info = < | ||
1013 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
1014 | 1060000 0 0x0 0 0x02000000 0x01F00000 | ||
1015 | 1250000 0 0x4 0 0x02000000 0x01F00000 | ||
1016 | >; | ||
1017 | }; | ||
1018 | |||
1019 | abb_mm: regulator-abb-mm { | ||
1020 | compatible = "ti,abb-v2"; | ||
1021 | regulator-name = "abb_mm"; | ||
1022 | #address-cells = <0>; | ||
1023 | #size-cells = <0>; | ||
1024 | clocks = <&sys_clkin>; | ||
1025 | ti,settling-time = <50>; | ||
1026 | ti,clock-cycles = <16>; | ||
1027 | |||
1028 | reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>, | ||
1029 | <0x4a0021a4 0x8>, <0x4ae0c314 0x4>; | ||
1030 | reg-names = "base-address", "int-address", | ||
1031 | "efuse-address", "ldo-address"; | ||
1032 | ti,tranxdone-status-mask = <0x80000000>; | ||
1033 | /* LDOVBBMM_MUX_CTRL */ | ||
1034 | ti,ldovbb-override-mask = <0x400>; | ||
1035 | /* LDOVBBMM_VSET_OUT */ | ||
1036 | ti,ldovbb-vset-mask = <0x1F>; | ||
1037 | |||
1038 | /* | ||
1039 | * NOTE: only FBB mode used but actual vset will | ||
1040 | * determine final biasing | ||
1041 | */ | ||
1042 | ti,abb_info = < | ||
1043 | /*uV ABB efuse rbb_m fbb_m vset_m*/ | ||
1044 | 1025000 0 0x0 0 0x02000000 0x01F00000 | ||
1045 | 1120000 0 0x4 0 0x02000000 0x01F00000 | ||
1046 | >; | ||
1047 | }; | ||
988 | }; | 1048 | }; |
989 | }; | 1049 | }; |
990 | 1050 | ||
diff --git a/arch/arm/boot/dts/r7s72100.dtsi b/arch/arm/boot/dts/r7s72100.dtsi index f50fbc8f3bd9..bdee22541189 100644 --- a/arch/arm/boot/dts/r7s72100.dtsi +++ b/arch/arm/boot/dts/r7s72100.dtsi | |||
@@ -144,6 +144,7 @@ | |||
144 | device_type = "cpu"; | 144 | device_type = "cpu"; |
145 | compatible = "arm,cortex-a9"; | 145 | compatible = "arm,cortex-a9"; |
146 | reg = <0>; | 146 | reg = <0>; |
147 | clock-frequency = <400000000>; | ||
147 | }; | 148 | }; |
148 | }; | 149 | }; |
149 | 150 | ||
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi index 7da20ca633dd..80b8eddb4105 100644 --- a/arch/arm/boot/dts/tegra114.dtsi +++ b/arch/arm/boot/dts/tegra114.dtsi | |||
@@ -220,6 +220,12 @@ | |||
220 | interrupt-controller; | 220 | interrupt-controller; |
221 | }; | 221 | }; |
222 | 222 | ||
223 | apbmisc@70000800 { | ||
224 | compatible = "nvidia,tegra114-apbmisc", "nvidia,tegra20-apbmisc"; | ||
225 | reg = <0x70000800 0x64 /* Chip revision */ | ||
226 | 0x70000008 0x04>; /* Strapping options */ | ||
227 | }; | ||
228 | |||
223 | pinmux: pinmux@70000868 { | 229 | pinmux: pinmux@70000868 { |
224 | compatible = "nvidia,tegra114-pinmux"; | 230 | compatible = "nvidia,tegra114-pinmux"; |
225 | reg = <0x70000868 0x148 /* Pad control registers */ | 231 | reg = <0x70000868 0x148 /* Pad control registers */ |
@@ -485,6 +491,15 @@ | |||
485 | clock-names = "pclk", "clk32k_in"; | 491 | clock-names = "pclk", "clk32k_in"; |
486 | }; | 492 | }; |
487 | 493 | ||
494 | fuse@7000f800 { | ||
495 | compatible = "nvidia,tegra114-efuse"; | ||
496 | reg = <0x7000f800 0x400>; | ||
497 | clocks = <&tegra_car TEGRA114_CLK_FUSE>; | ||
498 | clock-names = "fuse"; | ||
499 | resets = <&tegra_car 39>; | ||
500 | reset-names = "fuse"; | ||
501 | }; | ||
502 | |||
488 | iommu@70019010 { | 503 | iommu@70019010 { |
489 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; | 504 | compatible = "nvidia,tegra114-smmu", "nvidia,tegra30-smmu"; |
490 | reg = <0x70019010 0x02c | 505 | reg = <0x70019010 0x02c |
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index aa8753a7c211..d44e9b91e207 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi | |||
@@ -179,6 +179,12 @@ | |||
179 | #dma-cells = <1>; | 179 | #dma-cells = <1>; |
180 | }; | 180 | }; |
181 | 181 | ||
182 | apbmisc@0,70000800 { | ||
183 | compatible = "nvidia,tegra124-apbmisc", "nvidia,tegra20-apbmisc"; | ||
184 | reg = <0x0 0x70000800 0x0 0x64>, /* Chip revision */ | ||
185 | <0x0 0x7000E864 0x0 0x04>; /* Strapping options */ | ||
186 | }; | ||
187 | |||
182 | pinmux: pinmux@0,70000868 { | 188 | pinmux: pinmux@0,70000868 { |
183 | compatible = "nvidia,tegra124-pinmux"; | 189 | compatible = "nvidia,tegra124-pinmux"; |
184 | reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ | 190 | reg = <0x0 0x70000868 0x0 0x164>, /* Pad control registers */ |
@@ -449,6 +455,15 @@ | |||
449 | clock-names = "pclk", "clk32k_in"; | 455 | clock-names = "pclk", "clk32k_in"; |
450 | }; | 456 | }; |
451 | 457 | ||
458 | fuse@0,7000f800 { | ||
459 | compatible = "nvidia,tegra124-efuse"; | ||
460 | reg = <0x0 0x7000f800 0x0 0x400>; | ||
461 | clocks = <&tegra_car TEGRA124_CLK_FUSE>; | ||
462 | clock-names = "fuse"; | ||
463 | resets = <&tegra_car 39>; | ||
464 | reset-names = "fuse"; | ||
465 | }; | ||
466 | |||
452 | sdhci@0,700b0000 { | 467 | sdhci@0,700b0000 { |
453 | compatible = "nvidia,tegra124-sdhci"; | 468 | compatible = "nvidia,tegra124-sdhci"; |
454 | reg = <0x0 0x700b0000 0x0 0x200>; | 469 | reg = <0x0 0x700b0000 0x0 0x200>; |
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 935df8906f25..1908f6937e53 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi | |||
@@ -236,6 +236,12 @@ | |||
236 | interrupt-controller; | 236 | interrupt-controller; |
237 | }; | 237 | }; |
238 | 238 | ||
239 | apbmisc@70000800 { | ||
240 | compatible = "nvidia,tegra20-apbmisc"; | ||
241 | reg = <0x70000800 0x64 /* Chip revision */ | ||
242 | 0x70000008 0x04>; /* Strapping options */ | ||
243 | }; | ||
244 | |||
239 | pinmux: pinmux@70000014 { | 245 | pinmux: pinmux@70000014 { |
240 | compatible = "nvidia,tegra20-pinmux"; | 246 | compatible = "nvidia,tegra20-pinmux"; |
241 | reg = <0x70000014 0x10 /* Tri-state registers */ | 247 | reg = <0x70000014 0x10 /* Tri-state registers */ |
@@ -545,6 +551,15 @@ | |||
545 | #size-cells = <0>; | 551 | #size-cells = <0>; |
546 | }; | 552 | }; |
547 | 553 | ||
554 | fuse@7000f800 { | ||
555 | compatible = "nvidia,tegra20-efuse"; | ||
556 | reg = <0x7000F800 0x400>; | ||
557 | clocks = <&tegra_car TEGRA20_CLK_FUSE>; | ||
558 | clock-names = "fuse"; | ||
559 | resets = <&tegra_car 39>; | ||
560 | reset-names = "fuse"; | ||
561 | }; | ||
562 | |||
548 | pcie-controller@80003000 { | 563 | pcie-controller@80003000 { |
549 | compatible = "nvidia,tegra20-pcie"; | 564 | compatible = "nvidia,tegra20-pcie"; |
550 | device_type = "pci"; | 565 | device_type = "pci"; |
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 54805ce5efe0..6b35c29278d7 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi | |||
@@ -335,6 +335,12 @@ | |||
335 | interrupt-controller; | 335 | interrupt-controller; |
336 | }; | 336 | }; |
337 | 337 | ||
338 | apbmisc@70000800 { | ||
339 | compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc"; | ||
340 | reg = <0x70000800 0x64 /* Chip revision */ | ||
341 | 0x70000008 0x04>; /* Strapping options */ | ||
342 | }; | ||
343 | |||
338 | pinmux: pinmux@70000868 { | 344 | pinmux: pinmux@70000868 { |
339 | compatible = "nvidia,tegra30-pinmux"; | 345 | compatible = "nvidia,tegra30-pinmux"; |
340 | reg = <0x70000868 0xd4 /* Pad control registers */ | 346 | reg = <0x70000868 0xd4 /* Pad control registers */ |
@@ -631,6 +637,15 @@ | |||
631 | nvidia,ahb = <&ahb>; | 637 | nvidia,ahb = <&ahb>; |
632 | }; | 638 | }; |
633 | 639 | ||
640 | fuse@7000f800 { | ||
641 | compatible = "nvidia,tegra30-efuse"; | ||
642 | reg = <0x7000f800 0x400>; | ||
643 | clocks = <&tegra_car TEGRA30_CLK_FUSE>; | ||
644 | clock-names = "fuse"; | ||
645 | resets = <&tegra_car 39>; | ||
646 | reset-names = "fuse"; | ||
647 | }; | ||
648 | |||
634 | ahub@70080000 { | 649 | ahub@70080000 { |
635 | compatible = "nvidia,tegra30-ahub"; | 650 | compatible = "nvidia,tegra30-ahub"; |
636 | reg = <0x70080000 0x200 | 651 | reg = <0x70080000 0x200 |
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig deleted file mode 100644 index ad6b61b0bd11..000000000000 --- a/arch/arm/configs/s5p64x0_defconfig +++ /dev/null | |||
@@ -1,68 +0,0 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
3 | CONFIG_BLK_DEV_INITRD=y | ||
4 | CONFIG_KALLSYMS_ALL=y | ||
5 | CONFIG_MODULES=y | ||
6 | CONFIG_MODULE_UNLOAD=y | ||
7 | # CONFIG_BLK_DEV_BSG is not set | ||
8 | CONFIG_ARCH_S5P64X0=y | ||
9 | CONFIG_S3C_BOOT_ERROR_RESET=y | ||
10 | CONFIG_S3C_LOWLEVEL_UART_PORT=1 | ||
11 | CONFIG_MACH_SMDK6440=y | ||
12 | CONFIG_MACH_SMDK6450=y | ||
13 | CONFIG_NO_HZ=y | ||
14 | CONFIG_HIGH_RES_TIMERS=y | ||
15 | CONFIG_CPU_32v6K=y | ||
16 | CONFIG_AEABI=y | ||
17 | CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc" | ||
18 | CONFIG_FPE_NWFPE=y | ||
19 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
20 | # CONFIG_PREVENT_FIRMWARE_BUILD is not set | ||
21 | CONFIG_BLK_DEV_RAM=y | ||
22 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
23 | # CONFIG_MISC_DEVICES is not set | ||
24 | CONFIG_SCSI=y | ||
25 | CONFIG_BLK_DEV_SD=y | ||
26 | CONFIG_CHR_DEV_SG=y | ||
27 | CONFIG_INPUT_EVDEV=y | ||
28 | CONFIG_INPUT_TOUCHSCREEN=y | ||
29 | CONFIG_SERIAL_8250=y | ||
30 | CONFIG_SERIAL_8250_NR_UARTS=3 | ||
31 | CONFIG_SERIAL_SAMSUNG=y | ||
32 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | ||
33 | CONFIG_HW_RANDOM=y | ||
34 | # CONFIG_HWMON is not set | ||
35 | CONFIG_DISPLAY_SUPPORT=y | ||
36 | # CONFIG_VGA_CONSOLE is not set | ||
37 | # CONFIG_HID_SUPPORT is not set | ||
38 | # CONFIG_USB_SUPPORT is not set | ||
39 | CONFIG_EXT2_FS=y | ||
40 | CONFIG_EXT3_FS=y | ||
41 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
42 | CONFIG_EXT3_FS_SECURITY=y | ||
43 | CONFIG_INOTIFY=y | ||
44 | CONFIG_MSDOS_FS=y | ||
45 | CONFIG_VFAT_FS=y | ||
46 | CONFIG_TMPFS=y | ||
47 | CONFIG_TMPFS_POSIX_ACL=y | ||
48 | CONFIG_CRAMFS=y | ||
49 | CONFIG_ROMFS_FS=y | ||
50 | CONFIG_NLS_CODEPAGE_437=y | ||
51 | CONFIG_NLS_ASCII=y | ||
52 | CONFIG_NLS_ISO8859_1=y | ||
53 | CONFIG_MAGIC_SYSRQ=y | ||
54 | CONFIG_DEBUG_KERNEL=y | ||
55 | CONFIG_DEBUG_RT_MUTEXES=y | ||
56 | CONFIG_DEBUG_SPINLOCK=y | ||
57 | CONFIG_DEBUG_MUTEXES=y | ||
58 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
59 | CONFIG_DEBUG_INFO=y | ||
60 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
61 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
62 | CONFIG_DEBUG_USER=y | ||
63 | CONFIG_DEBUG_ERRORS=y | ||
64 | CONFIG_DEBUG_LL=y | ||
65 | CONFIG_DEBUG_S3C_UART=1 | ||
66 | CONFIG_CRYPTO=y | ||
67 | # CONFIG_CRYPTO_ANSI_CPRNG is not set | ||
68 | CONFIG_CRC_CCITT=y | ||
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig deleted file mode 100644 index 41bafc94dd85..000000000000 --- a/arch/arm/configs/s5pc100_defconfig +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | CONFIG_EXPERIMENTAL=y | ||
2 | CONFIG_SYSFS_DEPRECATED_V2=y | ||
3 | CONFIG_BLK_DEV_INITRD=y | ||
4 | CONFIG_KALLSYMS_ALL=y | ||
5 | CONFIG_MODULES=y | ||
6 | CONFIG_MODULE_UNLOAD=y | ||
7 | # CONFIG_BLK_DEV_BSG is not set | ||
8 | CONFIG_ARCH_S5PC100=y | ||
9 | CONFIG_MACH_SMDKC100=y | ||
10 | CONFIG_AEABI=y | ||
11 | CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M" | ||
12 | CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" | ||
13 | CONFIG_BLK_DEV_LOOP=y | ||
14 | CONFIG_BLK_DEV_RAM=y | ||
15 | CONFIG_BLK_DEV_RAM_SIZE=8192 | ||
16 | CONFIG_EEPROM_AT24=y | ||
17 | CONFIG_SERIAL_8250=y | ||
18 | CONFIG_SERIAL_SAMSUNG=y | ||
19 | CONFIG_SERIAL_SAMSUNG_CONSOLE=y | ||
20 | CONFIG_HW_RANDOM=y | ||
21 | CONFIG_I2C=y | ||
22 | CONFIG_I2C_CHARDEV=y | ||
23 | # CONFIG_VGA_CONSOLE is not set | ||
24 | CONFIG_MMC=y | ||
25 | CONFIG_MMC_DEBUG=y | ||
26 | CONFIG_MMC_UNSAFE_RESUME=y | ||
27 | CONFIG_SDIO_UART=y | ||
28 | CONFIG_MMC_SDHCI=y | ||
29 | CONFIG_EXT2_FS=y | ||
30 | CONFIG_EXT3_FS=y | ||
31 | CONFIG_EXT3_FS_POSIX_ACL=y | ||
32 | CONFIG_EXT3_FS_SECURITY=y | ||
33 | CONFIG_INOTIFY=y | ||
34 | CONFIG_TMPFS=y | ||
35 | CONFIG_TMPFS_POSIX_ACL=y | ||
36 | CONFIG_CRAMFS=y | ||
37 | CONFIG_ROMFS_FS=y | ||
38 | CONFIG_MAGIC_SYSRQ=y | ||
39 | CONFIG_DEBUG_KERNEL=y | ||
40 | CONFIG_DEBUG_RT_MUTEXES=y | ||
41 | CONFIG_DEBUG_SPINLOCK=y | ||
42 | CONFIG_DEBUG_MUTEXES=y | ||
43 | CONFIG_DEBUG_SPINLOCK_SLEEP=y | ||
44 | CONFIG_DEBUG_INFO=y | ||
45 | # CONFIG_RCU_CPU_STALL_DETECTOR is not set | ||
46 | CONFIG_SYSCTL_SYSCALL_CHECK=y | ||
47 | CONFIG_DEBUG_USER=y | ||
48 | CONFIG_DEBUG_ERRORS=y | ||
49 | CONFIG_DEBUG_LL=y | ||
diff --git a/arch/arm/include/asm/gpio.h b/arch/arm/include/asm/gpio.h index 477e0206e016..504dcddebfcc 100644 --- a/arch/arm/include/asm/gpio.h +++ b/arch/arm/include/asm/gpio.h | |||
@@ -5,12 +5,6 @@ | |||
5 | #define ARCH_NR_GPIOS CONFIG_ARCH_NR_GPIO | 5 | #define ARCH_NR_GPIOS CONFIG_ARCH_NR_GPIO |
6 | #endif | 6 | #endif |
7 | 7 | ||
8 | /* not all ARM platforms necessarily support this API ... */ | ||
9 | #ifdef CONFIG_NEED_MACH_GPIO_H | ||
10 | #include <mach/gpio.h> | ||
11 | #endif | ||
12 | |||
13 | #ifndef __ARM_GPIOLIB_COMPLEX | ||
14 | /* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */ | 8 | /* Note: this may rely upon the value of ARCH_NR_GPIOS set in mach/gpio.h */ |
15 | #include <asm-generic/gpio.h> | 9 | #include <asm-generic/gpio.h> |
16 | 10 | ||
@@ -18,7 +12,6 @@ | |||
18 | #define gpio_get_value __gpio_get_value | 12 | #define gpio_get_value __gpio_get_value |
19 | #define gpio_set_value __gpio_set_value | 13 | #define gpio_set_value __gpio_set_value |
20 | #define gpio_cansleep __gpio_cansleep | 14 | #define gpio_cansleep __gpio_cansleep |
21 | #endif | ||
22 | 15 | ||
23 | /* | 16 | /* |
24 | * Provide a default gpio_to_irq() which should satisfy every case. | 17 | * Provide a default gpio_to_irq() which should satisfy every case. |
diff --git a/arch/arm/include/debug/clps711x.S b/arch/arm/include/debug/clps711x.S new file mode 100644 index 000000000000..abe225436686 --- /dev/null +++ b/arch/arm/include/debug/clps711x.S | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | */ | ||
9 | |||
10 | #ifndef CONFIG_DEBUG_CLPS711X_UART2 | ||
11 | #define CLPS711X_UART_PADDR (0x80000000 + 0x0000) | ||
12 | #define CLPS711X_UART_VADDR (0xfeff0000 + 0x0000) | ||
13 | #else | ||
14 | #define CLPS711X_UART_PADDR (0x80000000 + 0x1000) | ||
15 | #define CLPS711X_UART_VADDR (0xfeff0000 + 0x1000) | ||
16 | #endif | ||
17 | |||
18 | #define SYSFLG (0x0140) | ||
19 | #define SYSFLG_UBUSY (1 << 11) | ||
20 | #define UARTDR (0x0480) | ||
21 | |||
22 | .macro addruart, rp, rv, tmp | ||
23 | ldr \rv, =CLPS711X_UART_VADDR | ||
24 | ldr \rp, =CLPS711X_UART_PADDR | ||
25 | .endm | ||
26 | |||
27 | .macro waituart,rd,rx | ||
28 | .endm | ||
29 | |||
30 | .macro senduart,rd,rx | ||
31 | str \rd, [\rx, #UARTDR] | ||
32 | .endm | ||
33 | |||
34 | .macro busyuart,rd,rx | ||
35 | 1001: ldr \rd, [\rx, #SYSFLG] | ||
36 | tst \rd, #SYSFLG_UBUSY | ||
37 | bne 1001b | ||
38 | .endm | ||
diff --git a/arch/arm/mach-clps711x/board-autcpu12.c b/arch/arm/mach-clps711x/board-autcpu12.c index d62ca16d5394..45abf6bd5f68 100644 --- a/arch/arm/mach-clps711x/board-autcpu12.c +++ b/arch/arm/mach-clps711x/board-autcpu12.c | |||
@@ -266,7 +266,6 @@ MACHINE_START(AUTCPU12, "autronix autcpu12") | |||
266 | /* Maintainer: Thomas Gleixner */ | 266 | /* Maintainer: Thomas Gleixner */ |
267 | .atag_offset = 0x20000, | 267 | .atag_offset = 0x20000, |
268 | .map_io = clps711x_map_io, | 268 | .map_io = clps711x_map_io, |
269 | .init_early = clps711x_init_early, | ||
270 | .init_irq = clps711x_init_irq, | 269 | .init_irq = clps711x_init_irq, |
271 | .init_time = clps711x_timer_init, | 270 | .init_time = clps711x_timer_init, |
272 | .init_machine = autcpu12_init, | 271 | .init_machine = autcpu12_init, |
diff --git a/arch/arm/mach-clps711x/board-cdb89712.c b/arch/arm/mach-clps711x/board-cdb89712.c index e261a47f2aff..1ec378c334e5 100644 --- a/arch/arm/mach-clps711x/board-cdb89712.c +++ b/arch/arm/mach-clps711x/board-cdb89712.c | |||
@@ -140,7 +140,6 @@ MACHINE_START(CDB89712, "Cirrus-CDB89712") | |||
140 | /* Maintainer: Ray Lehtiniemi */ | 140 | /* Maintainer: Ray Lehtiniemi */ |
141 | .atag_offset = 0x100, | 141 | .atag_offset = 0x100, |
142 | .map_io = clps711x_map_io, | 142 | .map_io = clps711x_map_io, |
143 | .init_early = clps711x_init_early, | ||
144 | .init_irq = clps711x_init_irq, | 143 | .init_irq = clps711x_init_irq, |
145 | .init_time = clps711x_timer_init, | 144 | .init_time = clps711x_timer_init, |
146 | .init_machine = cdb89712_init, | 145 | .init_machine = cdb89712_init, |
diff --git a/arch/arm/mach-clps711x/board-clep7312.c b/arch/arm/mach-clps711x/board-clep7312.c index 94a7add88a3f..f9ca22b646bf 100644 --- a/arch/arm/mach-clps711x/board-clep7312.c +++ b/arch/arm/mach-clps711x/board-clep7312.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | 26 | ||
27 | #include "common.h" | 27 | #include "common.h" |
28 | #include "devices.h" | ||
28 | 29 | ||
29 | static void __init | 30 | static void __init |
30 | fixup_clep7312(struct tag *tags, char **cmdline) | 31 | fixup_clep7312(struct tag *tags, char **cmdline) |
@@ -37,8 +38,8 @@ MACHINE_START(CLEP7212, "Cirrus Logic 7212/7312") | |||
37 | .atag_offset = 0x0100, | 38 | .atag_offset = 0x0100, |
38 | .fixup = fixup_clep7312, | 39 | .fixup = fixup_clep7312, |
39 | .map_io = clps711x_map_io, | 40 | .map_io = clps711x_map_io, |
40 | .init_early = clps711x_init_early, | ||
41 | .init_irq = clps711x_init_irq, | 41 | .init_irq = clps711x_init_irq, |
42 | .init_time = clps711x_timer_init, | 42 | .init_time = clps711x_timer_init, |
43 | .init_machine = clps711x_devices_init, | ||
43 | .restart = clps711x_restart, | 44 | .restart = clps711x_restart, |
44 | MACHINE_END | 45 | MACHINE_END |
diff --git a/arch/arm/mach-clps711x/board-edb7211.c b/arch/arm/mach-clps711x/board-edb7211.c index 6144fb5cdc36..fdf54d40909a 100644 --- a/arch/arm/mach-clps711x/board-edb7211.c +++ b/arch/arm/mach-clps711x/board-edb7211.c | |||
@@ -148,11 +148,6 @@ fixup_edb7211(struct tag *tags, char **cmdline) | |||
148 | memblock_add(0xc1000000, SZ_8M); | 148 | memblock_add(0xc1000000, SZ_8M); |
149 | } | 149 | } |
150 | 150 | ||
151 | static void __init edb7211_init(void) | ||
152 | { | ||
153 | clps711x_devices_init(); | ||
154 | } | ||
155 | |||
156 | static void __init edb7211_init_late(void) | 151 | static void __init edb7211_init_late(void) |
157 | { | 152 | { |
158 | gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios)); | 153 | gpio_request_array(edb7211_gpios, ARRAY_SIZE(edb7211_gpios)); |
@@ -178,10 +173,9 @@ MACHINE_START(EDB7211, "CL-EDB7211 (EP7211 eval board)") | |||
178 | .fixup = fixup_edb7211, | 173 | .fixup = fixup_edb7211, |
179 | .reserve = edb7211_reserve, | 174 | .reserve = edb7211_reserve, |
180 | .map_io = clps711x_map_io, | 175 | .map_io = clps711x_map_io, |
181 | .init_early = clps711x_init_early, | ||
182 | .init_irq = clps711x_init_irq, | 176 | .init_irq = clps711x_init_irq, |
183 | .init_time = clps711x_timer_init, | 177 | .init_time = clps711x_timer_init, |
184 | .init_machine = edb7211_init, | 178 | .init_machine = clps711x_devices_init, |
185 | .init_late = edb7211_init_late, | 179 | .init_late = edb7211_init_late, |
186 | .restart = clps711x_restart, | 180 | .restart = clps711x_restart, |
187 | MACHINE_END | 181 | MACHINE_END |
diff --git a/arch/arm/mach-clps711x/board-p720t.c b/arch/arm/mach-clps711x/board-p720t.c index 96bcc76c4437..e68dd629bda2 100644 --- a/arch/arm/mach-clps711x/board-p720t.c +++ b/arch/arm/mach-clps711x/board-p720t.c | |||
@@ -365,7 +365,6 @@ MACHINE_START(P720T, "ARM-Prospector720T") | |||
365 | .atag_offset = 0x100, | 365 | .atag_offset = 0x100, |
366 | .fixup = fixup_p720t, | 366 | .fixup = fixup_p720t, |
367 | .map_io = clps711x_map_io, | 367 | .map_io = clps711x_map_io, |
368 | .init_early = clps711x_init_early, | ||
369 | .init_irq = clps711x_init_irq, | 368 | .init_irq = clps711x_init_irq, |
370 | .init_time = clps711x_timer_init, | 369 | .init_time = clps711x_timer_init, |
371 | .init_machine = p720t_init, | 370 | .init_machine = p720t_init, |
diff --git a/arch/arm/mach-clps711x/common.c b/arch/arm/mach-clps711x/common.c index aee81fa46ccf..2a6323b15782 100644 --- a/arch/arm/mach-clps711x/common.c +++ b/arch/arm/mach-clps711x/common.c | |||
@@ -193,15 +193,3 @@ void clps711x_restart(enum reboot_mode mode, const char *cmd) | |||
193 | { | 193 | { |
194 | soft_restart(0); | 194 | soft_restart(0); |
195 | } | 195 | } |
196 | |||
197 | static void clps711x_idle(void) | ||
198 | { | ||
199 | clps_writel(1, HALT); | ||
200 | asm("mov r0, r0"); | ||
201 | asm("mov r0, r0"); | ||
202 | } | ||
203 | |||
204 | void __init clps711x_init_early(void) | ||
205 | { | ||
206 | arm_pm_idle = clps711x_idle; | ||
207 | } | ||
diff --git a/arch/arm/mach-clps711x/common.h b/arch/arm/mach-clps711x/common.h index 7489139d5d63..f88189963898 100644 --- a/arch/arm/mach-clps711x/common.h +++ b/arch/arm/mach-clps711x/common.h | |||
@@ -13,7 +13,6 @@ extern void clps711x_map_io(void); | |||
13 | extern void clps711x_init_irq(void); | 13 | extern void clps711x_init_irq(void); |
14 | extern void clps711x_timer_init(void); | 14 | extern void clps711x_timer_init(void); |
15 | extern void clps711x_restart(enum reboot_mode mode, const char *cmd); | 15 | extern void clps711x_restart(enum reboot_mode mode, const char *cmd); |
16 | extern void clps711x_init_early(void); | ||
17 | 16 | ||
18 | /* drivers/irqchip/irq-clps711x.c */ | 17 | /* drivers/irqchip/irq-clps711x.c */ |
19 | void clps711x_intc_init(phys_addr_t, resource_size_t); | 18 | void clps711x_intc_init(phys_addr_t, resource_size_t); |
diff --git a/arch/arm/mach-clps711x/devices.c b/arch/arm/mach-clps711x/devices.c index 2001488a5ef2..0c689d3a6710 100644 --- a/arch/arm/mach-clps711x/devices.c +++ b/arch/arm/mach-clps711x/devices.c | |||
@@ -14,6 +14,15 @@ | |||
14 | 14 | ||
15 | #include <mach/hardware.h> | 15 | #include <mach/hardware.h> |
16 | 16 | ||
17 | static const struct resource clps711x_cpuidle_res __initconst = | ||
18 | DEFINE_RES_MEM(CLPS711X_PHYS_BASE + HALT, SZ_128); | ||
19 | |||
20 | static void __init clps711x_add_cpuidle(void) | ||
21 | { | ||
22 | platform_device_register_simple("clps711x-cpuidle", PLATFORM_DEVID_NONE, | ||
23 | &clps711x_cpuidle_res, 1); | ||
24 | } | ||
25 | |||
17 | static const phys_addr_t clps711x_gpios[][2] __initconst = { | 26 | static const phys_addr_t clps711x_gpios[][2] __initconst = { |
18 | { PADR, PADDR }, | 27 | { PADR, PADDR }, |
19 | { PBDR, PBDDR }, | 28 | { PBDR, PBDDR }, |
@@ -83,6 +92,7 @@ static void __init clps711x_add_uart(void) | |||
83 | 92 | ||
84 | void __init clps711x_devices_init(void) | 93 | void __init clps711x_devices_init(void) |
85 | { | 94 | { |
95 | clps711x_add_cpuidle(); | ||
86 | clps711x_add_gpio(); | 96 | clps711x_add_gpio(); |
87 | clps711x_add_syscon(); | 97 | clps711x_add_syscon(); |
88 | clps711x_add_uart(); | 98 | clps711x_add_uart(); |
diff --git a/arch/arm/mach-clps711x/include/mach/debug-macro.S b/arch/arm/mach-clps711x/include/mach/debug-macro.S deleted file mode 100644 index cb3684f8dae0..000000000000 --- a/arch/arm/mach-clps711x/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* arch/arm/mach-clps711x/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Debugging macro include header | ||
4 | * | ||
5 | * Copyright (C) 1994-1999 Russell King | ||
6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | * | ||
12 | */ | ||
13 | |||
14 | #include <mach/hardware.h> | ||
15 | |||
16 | .macro addruart, rp, rv, tmp | ||
17 | #ifndef CONFIG_DEBUG_CLPS711X_UART2 | ||
18 | mov \rp, #0x0000 @ UART1 | ||
19 | #else | ||
20 | mov \rp, #0x1000 @ UART2 | ||
21 | #endif | ||
22 | orr \rv, \rp, #CLPS711X_VIRT_BASE | ||
23 | orr \rp, \rp, #CLPS711X_PHYS_BASE | ||
24 | .endm | ||
25 | |||
26 | .macro senduart,rd,rx | ||
27 | str \rd, [\rx, #0x0480] @ UARTDR | ||
28 | .endm | ||
29 | |||
30 | .macro waituart,rd,rx | ||
31 | .endm | ||
32 | |||
33 | .macro busyuart,rd,rx | ||
34 | 1001: ldr \rd, [\rx, #0x0140] @ SYSFLGx | ||
35 | tst \rd, #1 << 11 @ UBUSYx | ||
36 | bne 1001b | ||
37 | .endm | ||
38 | |||
diff --git a/arch/arm/mach-clps711x/include/mach/hardware.h b/arch/arm/mach-clps711x/include/mach/hardware.h index 5d6afda1c0e8..833129c9f798 100644 --- a/arch/arm/mach-clps711x/include/mach/hardware.h +++ b/arch/arm/mach-clps711x/include/mach/hardware.h | |||
@@ -24,10 +24,7 @@ | |||
24 | 24 | ||
25 | #include <mach/clps711x.h> | 25 | #include <mach/clps711x.h> |
26 | 26 | ||
27 | #define IO_ADDRESS(x) (0xdc000000 + (((x) & 0x03ffffff) | \ | 27 | #define CLPS711X_VIRT_BASE IOMEM(0xfeff0000) |
28 | (((x) >> 2) & 0x3c000000))) | ||
29 | |||
30 | #define CLPS711X_VIRT_BASE IOMEM(IO_ADDRESS(CLPS711X_PHYS_BASE)) | ||
31 | 28 | ||
32 | #ifndef __ASSEMBLY__ | 29 | #ifndef __ASSEMBLY__ |
33 | #define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off)) | 30 | #define clps_readb(off) readb(CLPS711X_VIRT_BASE + (off)) |
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 1ee91763fa7c..f8daa9cc5617 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h | |||
@@ -111,25 +111,14 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) | |||
111 | #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ | 111 | #define soc_is_exynos5() (soc_is_exynos5250() || soc_is_exynos5410() || \ |
112 | soc_is_exynos5420() || soc_is_exynos5800()) | 112 | soc_is_exynos5420() || soc_is_exynos5800()) |
113 | 113 | ||
114 | void mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1); | ||
115 | |||
116 | struct map_desc; | ||
117 | extern void __iomem *sysram_ns_base_addr; | 114 | extern void __iomem *sysram_ns_base_addr; |
118 | extern void __iomem *sysram_base_addr; | 115 | extern void __iomem *sysram_base_addr; |
119 | void exynos_init_io(void); | 116 | extern void __iomem *pmu_base_addr; |
120 | void exynos_restart(enum reboot_mode mode, const char *cmd); | ||
121 | void exynos_sysram_init(void); | 117 | void exynos_sysram_init(void); |
122 | void exynos_cpuidle_init(void); | ||
123 | void exynos_cpufreq_init(void); | ||
124 | void exynos_init_late(void); | ||
125 | 118 | ||
126 | void exynos_firmware_init(void); | 119 | void exynos_firmware_init(void); |
127 | 120 | ||
128 | #ifdef CONFIG_PINCTRL_EXYNOS | ||
129 | extern u32 exynos_get_eint_wake_mask(void); | 121 | extern u32 exynos_get_eint_wake_mask(void); |
130 | #else | ||
131 | static inline u32 exynos_get_eint_wake_mask(void) { return 0xffffffff; } | ||
132 | #endif | ||
133 | 122 | ||
134 | #ifdef CONFIG_PM_SLEEP | 123 | #ifdef CONFIG_PM_SLEEP |
135 | extern void __init exynos_pm_init(void); | 124 | extern void __init exynos_pm_init(void); |
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 66c9b9614f3c..3164ef2e6b6c 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <linux/of_platform.h> | 19 | #include <linux/of_platform.h> |
20 | #include <linux/platform_device.h> | 20 | #include <linux/platform_device.h> |
21 | #include <linux/pm_domain.h> | 21 | #include <linux/pm_domain.h> |
22 | #include <linux/irqchip.h> | ||
22 | 23 | ||
23 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
24 | #include <asm/hardware/cache-l2x0.h> | 25 | #include <asm/hardware/cache-l2x0.h> |
@@ -29,6 +30,9 @@ | |||
29 | #include "common.h" | 30 | #include "common.h" |
30 | #include "mfc.h" | 31 | #include "mfc.h" |
31 | #include "regs-pmu.h" | 32 | #include "regs-pmu.h" |
33 | #include "regs-sys.h" | ||
34 | |||
35 | void __iomem *pmu_base_addr; | ||
32 | 36 | ||
33 | static struct map_desc exynos4_iodesc[] __initdata = { | 37 | static struct map_desc exynos4_iodesc[] __initdata = { |
34 | { | 38 | { |
@@ -143,7 +147,7 @@ static struct map_desc exynos5_iodesc[] __initdata = { | |||
143 | }, | 147 | }, |
144 | }; | 148 | }; |
145 | 149 | ||
146 | void exynos_restart(enum reboot_mode mode, const char *cmd) | 150 | static void exynos_restart(enum reboot_mode mode, const char *cmd) |
147 | { | 151 | { |
148 | struct device_node *np; | 152 | struct device_node *np; |
149 | u32 val = 0x1; | 153 | u32 val = 0x1; |
@@ -204,7 +208,7 @@ void __init exynos_sysram_init(void) | |||
204 | } | 208 | } |
205 | } | 209 | } |
206 | 210 | ||
207 | void __init exynos_init_late(void) | 211 | static void __init exynos_init_late(void) |
208 | { | 212 | { |
209 | if (of_machine_is_compatible("samsung,exynos5440")) | 213 | if (of_machine_is_compatible("samsung,exynos5440")) |
210 | /* to be supported later */ | 214 | /* to be supported later */ |
@@ -251,7 +255,7 @@ static void __init exynos_map_io(void) | |||
251 | iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); | 255 | iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc)); |
252 | } | 256 | } |
253 | 257 | ||
254 | void __init exynos_init_io(void) | 258 | static void __init exynos_init_io(void) |
255 | { | 259 | { |
256 | debug_ll_io_init(); | 260 | debug_ll_io_init(); |
257 | 261 | ||
@@ -263,6 +267,39 @@ void __init exynos_init_io(void) | |||
263 | exynos_map_io(); | 267 | exynos_map_io(); |
264 | } | 268 | } |
265 | 269 | ||
270 | static const struct of_device_id exynos_dt_pmu_match[] = { | ||
271 | { .compatible = "samsung,exynos3250-pmu" }, | ||
272 | { .compatible = "samsung,exynos4210-pmu" }, | ||
273 | { .compatible = "samsung,exynos4212-pmu" }, | ||
274 | { .compatible = "samsung,exynos4412-pmu" }, | ||
275 | { .compatible = "samsung,exynos5250-pmu" }, | ||
276 | { .compatible = "samsung,exynos5420-pmu" }, | ||
277 | { /*sentinel*/ }, | ||
278 | }; | ||
279 | |||
280 | static void exynos_map_pmu(void) | ||
281 | { | ||
282 | struct device_node *np; | ||
283 | |||
284 | np = of_find_matching_node(NULL, exynos_dt_pmu_match); | ||
285 | if (np) | ||
286 | pmu_base_addr = of_iomap(np, 0); | ||
287 | |||
288 | if (!pmu_base_addr) | ||
289 | panic("failed to find exynos pmu register\n"); | ||
290 | } | ||
291 | |||
292 | static void __init exynos_init_irq(void) | ||
293 | { | ||
294 | irqchip_init(); | ||
295 | /* | ||
296 | * Since platsmp.c needs pmu base address by the time | ||
297 | * DT is not unflatten so we can't use DT APIs before | ||
298 | * init_irq | ||
299 | */ | ||
300 | exynos_map_pmu(); | ||
301 | } | ||
302 | |||
266 | static void __init exynos_dt_machine_init(void) | 303 | static void __init exynos_dt_machine_init(void) |
267 | { | 304 | { |
268 | struct device_node *i2c_np; | 305 | struct device_node *i2c_np; |
@@ -352,6 +389,7 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)") | |||
352 | .smp = smp_ops(exynos_smp_ops), | 389 | .smp = smp_ops(exynos_smp_ops), |
353 | .map_io = exynos_init_io, | 390 | .map_io = exynos_init_io, |
354 | .init_early = exynos_firmware_init, | 391 | .init_early = exynos_firmware_init, |
392 | .init_irq = exynos_init_irq, | ||
355 | .init_machine = exynos_dt_machine_init, | 393 | .init_machine = exynos_dt_machine_init, |
356 | .init_late = exynos_init_late, | 394 | .init_late = exynos_init_late, |
357 | .dt_compat = exynos_dt_compat, | 395 | .dt_compat = exynos_dt_compat, |
diff --git a/arch/arm/mach-exynos/headsmp.S b/arch/arm/mach-exynos/headsmp.S index cdd9d91e9933..b54f9701e421 100644 --- a/arch/arm/mach-exynos/headsmp.S +++ b/arch/arm/mach-exynos/headsmp.S | |||
@@ -1,5 +1,4 @@ | |||
1 | /* | 1 | /* |
2 | * linux/arch/arm/mach-exynos4/headsmp.S | ||
3 | * | 2 | * |
4 | * Cloned from linux/arch/arm/mach-realview/headsmp.S | 3 | * Cloned from linux/arch/arm/mach-realview/headsmp.S |
5 | * | 4 | * |
diff --git a/arch/arm/mach-exynos/hotplug.c b/arch/arm/mach-exynos/hotplug.c index 920a4baa53cd..4d86961a7957 100644 --- a/arch/arm/mach-exynos/hotplug.c +++ b/arch/arm/mach-exynos/hotplug.c | |||
@@ -1,5 +1,4 @@ | |||
1 | /* linux arch/arm/mach-exynos4/hotplug.c | 1 | /* |
2 | * | ||
3 | * Cloned from linux/arch/arm/mach-realview/hotplug.c | 2 | * Cloned from linux/arch/arm/mach-realview/hotplug.c |
4 | * | 3 | * |
5 | * Copyright (C) 2002 ARM Ltd. | 4 | * Copyright (C) 2002 ARM Ltd. |
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h index 548269a60634..963002fb15c3 100644 --- a/arch/arm/mach-exynos/include/mach/map.h +++ b/arch/arm/mach-exynos/include/mach/map.h | |||
@@ -1,5 +1,4 @@ | |||
1 | /* linux/arch/arm/mach-exynos/include/mach/map.h | 1 | /* |
2 | * | ||
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | 2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com/ | 3 | * http://www.samsung.com/ |
5 | * | 4 | * |
diff --git a/arch/arm/mach-exynos/include/mach/memory.h b/arch/arm/mach-exynos/include/mach/memory.h index 2a4cdb7cb326..e19df1f18c0d 100644 --- a/arch/arm/mach-exynos/include/mach/memory.h +++ b/arch/arm/mach-exynos/include/mach/memory.h | |||
@@ -1,5 +1,4 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/include/mach/memory.h | 1 | /* |
2 | * | ||
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | 2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | 3 | * http://www.samsung.com |
5 | * | 4 | * |
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c index 70d1e65a51d8..e5a8d764f24c 100644 --- a/arch/arm/mach-exynos/platsmp.c +++ b/arch/arm/mach-exynos/platsmp.c | |||
@@ -1,5 +1,4 @@ | |||
1 | /* linux/arch/arm/mach-exynos4/platsmp.c | 1 | /* |
2 | * | ||
3 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | 2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com | 3 | * http://www.samsung.com |
5 | * | 4 | * |
@@ -32,6 +31,72 @@ | |||
32 | 31 | ||
33 | extern void exynos4_secondary_startup(void); | 32 | extern void exynos4_secondary_startup(void); |
34 | 33 | ||
34 | /** | ||
35 | * exynos_core_power_down : power down the specified cpu | ||
36 | * @cpu : the cpu to power down | ||
37 | * | ||
38 | * Power down the specified cpu. The sequence must be finished by a | ||
39 | * call to cpu_do_idle() | ||
40 | * | ||
41 | */ | ||
42 | void exynos_cpu_power_down(int cpu) | ||
43 | { | ||
44 | __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); | ||
45 | } | ||
46 | |||
47 | /** | ||
48 | * exynos_cpu_power_up : power up the specified cpu | ||
49 | * @cpu : the cpu to power up | ||
50 | * | ||
51 | * Power up the specified cpu | ||
52 | */ | ||
53 | void exynos_cpu_power_up(int cpu) | ||
54 | { | ||
55 | __raw_writel(S5P_CORE_LOCAL_PWR_EN, | ||
56 | EXYNOS_ARM_CORE_CONFIGURATION(cpu)); | ||
57 | } | ||
58 | |||
59 | /** | ||
60 | * exynos_cpu_power_state : returns the power state of the cpu | ||
61 | * @cpu : the cpu to retrieve the power state from | ||
62 | * | ||
63 | */ | ||
64 | int exynos_cpu_power_state(int cpu) | ||
65 | { | ||
66 | return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & | ||
67 | S5P_CORE_LOCAL_PWR_EN); | ||
68 | } | ||
69 | |||
70 | /** | ||
71 | * exynos_cluster_power_down : power down the specified cluster | ||
72 | * @cluster : the cluster to power down | ||
73 | */ | ||
74 | void exynos_cluster_power_down(int cluster) | ||
75 | { | ||
76 | __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); | ||
77 | } | ||
78 | |||
79 | /** | ||
80 | * exynos_cluster_power_up : power up the specified cluster | ||
81 | * @cluster : the cluster to power up | ||
82 | */ | ||
83 | void exynos_cluster_power_up(int cluster) | ||
84 | { | ||
85 | __raw_writel(S5P_CORE_LOCAL_PWR_EN, | ||
86 | EXYNOS_COMMON_CONFIGURATION(cluster)); | ||
87 | } | ||
88 | |||
89 | /** | ||
90 | * exynos_cluster_power_state : returns the power state of the cluster | ||
91 | * @cluster : the cluster to retrieve the power state from | ||
92 | * | ||
93 | */ | ||
94 | int exynos_cluster_power_state(int cluster) | ||
95 | { | ||
96 | return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) & | ||
97 | S5P_CORE_LOCAL_PWR_EN); | ||
98 | } | ||
99 | |||
35 | static inline void __iomem *cpu_boot_reg_base(void) | 100 | static inline void __iomem *cpu_boot_reg_base(void) |
36 | { | 101 | { |
37 | if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) | 102 | if (soc_is_exynos4210() && samsung_rev() == EXYNOS4210_REV_1_1) |
diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 67d383de614f..6ab68a068e93 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c | |||
@@ -35,6 +35,7 @@ | |||
35 | 35 | ||
36 | #include "common.h" | 36 | #include "common.h" |
37 | #include "regs-pmu.h" | 37 | #include "regs-pmu.h" |
38 | #include "regs-sys.h" | ||
38 | 39 | ||
39 | /** | 40 | /** |
40 | * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping | 41 | * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping |
@@ -100,72 +101,6 @@ static int exynos_irq_set_wake(struct irq_data *data, unsigned int state) | |||
100 | return -ENOENT; | 101 | return -ENOENT; |
101 | } | 102 | } |
102 | 103 | ||
103 | /** | ||
104 | * exynos_core_power_down : power down the specified cpu | ||
105 | * @cpu : the cpu to power down | ||
106 | * | ||
107 | * Power down the specified cpu. The sequence must be finished by a | ||
108 | * call to cpu_do_idle() | ||
109 | * | ||
110 | */ | ||
111 | void exynos_cpu_power_down(int cpu) | ||
112 | { | ||
113 | __raw_writel(0, EXYNOS_ARM_CORE_CONFIGURATION(cpu)); | ||
114 | } | ||
115 | |||
116 | /** | ||
117 | * exynos_cpu_power_up : power up the specified cpu | ||
118 | * @cpu : the cpu to power up | ||
119 | * | ||
120 | * Power up the specified cpu | ||
121 | */ | ||
122 | void exynos_cpu_power_up(int cpu) | ||
123 | { | ||
124 | __raw_writel(S5P_CORE_LOCAL_PWR_EN, | ||
125 | EXYNOS_ARM_CORE_CONFIGURATION(cpu)); | ||
126 | } | ||
127 | |||
128 | /** | ||
129 | * exynos_cpu_power_state : returns the power state of the cpu | ||
130 | * @cpu : the cpu to retrieve the power state from | ||
131 | * | ||
132 | */ | ||
133 | int exynos_cpu_power_state(int cpu) | ||
134 | { | ||
135 | return (__raw_readl(EXYNOS_ARM_CORE_STATUS(cpu)) & | ||
136 | S5P_CORE_LOCAL_PWR_EN); | ||
137 | } | ||
138 | |||
139 | /** | ||
140 | * exynos_cluster_power_down : power down the specified cluster | ||
141 | * @cluster : the cluster to power down | ||
142 | */ | ||
143 | void exynos_cluster_power_down(int cluster) | ||
144 | { | ||
145 | __raw_writel(0, EXYNOS_COMMON_CONFIGURATION(cluster)); | ||
146 | } | ||
147 | |||
148 | /** | ||
149 | * exynos_cluster_power_up : power up the specified cluster | ||
150 | * @cluster : the cluster to power up | ||
151 | */ | ||
152 | void exynos_cluster_power_up(int cluster) | ||
153 | { | ||
154 | __raw_writel(S5P_CORE_LOCAL_PWR_EN, | ||
155 | EXYNOS_COMMON_CONFIGURATION(cluster)); | ||
156 | } | ||
157 | |||
158 | /** | ||
159 | * exynos_cluster_power_state : returns the power state of the cluster | ||
160 | * @cluster : the cluster to retrieve the power state from | ||
161 | * | ||
162 | */ | ||
163 | int exynos_cluster_power_state(int cluster) | ||
164 | { | ||
165 | return (__raw_readl(EXYNOS_COMMON_STATUS(cluster)) & | ||
166 | S5P_CORE_LOCAL_PWR_EN); | ||
167 | } | ||
168 | |||
169 | #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ | 104 | #define EXYNOS_BOOT_VECTOR_ADDR (samsung_rev() == EXYNOS4210_REV_1_1 ? \ |
170 | S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ | 105 | S5P_INFORM7 : (samsung_rev() == EXYNOS4210_REV_1_0 ? \ |
171 | (sysram_base_addr + 0x24) : S5P_INFORM0)) | 106 | (sysram_base_addr + 0x24) : S5P_INFORM0)) |
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c index 797cb134bfff..fd76e1b5a471 100644 --- a/arch/arm/mach-exynos/pm_domains.c +++ b/arch/arm/mach-exynos/pm_domains.c | |||
@@ -23,8 +23,7 @@ | |||
23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
24 | #include <linux/sched.h> | 24 | #include <linux/sched.h> |
25 | 25 | ||
26 | #include "regs-pmu.h" | 26 | #define INT_LOCAL_PWR_EN 0x7 |
27 | |||
28 | #define MAX_CLK_PER_DOMAIN 4 | 27 | #define MAX_CLK_PER_DOMAIN 4 |
29 | 28 | ||
30 | /* | 29 | /* |
@@ -63,13 +62,13 @@ static int exynos_pd_power(struct generic_pm_domain *domain, bool power_on) | |||
63 | } | 62 | } |
64 | } | 63 | } |
65 | 64 | ||
66 | pwr = power_on ? S5P_INT_LOCAL_PWR_EN : 0; | 65 | pwr = power_on ? INT_LOCAL_PWR_EN : 0; |
67 | __raw_writel(pwr, base); | 66 | __raw_writel(pwr, base); |
68 | 67 | ||
69 | /* Wait max 1ms */ | 68 | /* Wait max 1ms */ |
70 | timeout = 10; | 69 | timeout = 10; |
71 | 70 | ||
72 | while ((__raw_readl(base + 0x4) & S5P_INT_LOCAL_PWR_EN) != pwr) { | 71 | while ((__raw_readl(base + 0x4) & INT_LOCAL_PWR_EN) != pwr) { |
73 | if (!timeout) { | 72 | if (!timeout) { |
74 | op = (power_on) ? "enable" : "disable"; | 73 | op = (power_on) ? "enable" : "disable"; |
75 | pr_err("Power domain %s %s failed\n", domain->name, op); | 74 | pr_err("Power domain %s %s failed\n", domain->name, op); |
@@ -231,7 +230,7 @@ static __init int exynos4_pm_init_power_domain(void) | |||
231 | no_clk: | 230 | no_clk: |
232 | platform_set_drvdata(pdev, pd); | 231 | platform_set_drvdata(pdev, pd); |
233 | 232 | ||
234 | on = __raw_readl(pd->base + 0x4) & S5P_INT_LOCAL_PWR_EN; | 233 | on = __raw_readl(pd->base + 0x4) & INT_LOCAL_PWR_EN; |
235 | 234 | ||
236 | pm_genpd_init(&pd->pd, NULL, !on); | 235 | pm_genpd_init(&pd->pd, NULL, !on); |
237 | } | 236 | } |
diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c index fb0deda3b3a4..dcfcb44c3c55 100644 --- a/arch/arm/mach-exynos/pmu.c +++ b/arch/arm/mach-exynos/pmu.c | |||
@@ -11,7 +11,6 @@ | |||
11 | 11 | ||
12 | #include <linux/io.h> | 12 | #include <linux/io.h> |
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/bug.h> | ||
15 | 14 | ||
16 | #include "common.h" | 15 | #include "common.h" |
17 | #include "regs-pmu.h" | 16 | #include "regs-pmu.h" |
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h index 1d13b08708f0..1993e6bd5388 100644 --- a/arch/arm/mach-exynos/regs-pmu.h +++ b/arch/arm/mach-exynos/regs-pmu.h | |||
@@ -15,7 +15,6 @@ | |||
15 | #include <mach/map.h> | 15 | #include <mach/map.h> |
16 | 16 | ||
17 | #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) | 17 | #define S5P_PMUREG(x) (S5P_VA_PMU + (x)) |
18 | #define S5P_SYSREG(x) (S3C_VA_SYS + (x)) | ||
19 | 18 | ||
20 | #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) | 19 | #define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200) |
21 | 20 | ||
@@ -127,7 +126,6 @@ | |||
127 | #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) | 126 | #define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8) |
128 | 127 | ||
129 | #define S5P_CORE_LOCAL_PWR_EN 0x3 | 128 | #define S5P_CORE_LOCAL_PWR_EN 0x3 |
130 | #define S5P_INT_LOCAL_PWR_EN 0x7 | ||
131 | 129 | ||
132 | /* Only for EXYNOS4210 */ | 130 | /* Only for EXYNOS4210 */ |
133 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) | 131 | #define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154) |
@@ -188,8 +186,6 @@ | |||
188 | 186 | ||
189 | /* For EXYNOS5 */ | 187 | /* For EXYNOS5 */ |
190 | 188 | ||
191 | #define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234) | ||
192 | |||
193 | #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) | 189 | #define EXYNOS5_AUTO_WDTRESET_DISABLE S5P_PMUREG(0x0408) |
194 | #define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) | 190 | #define EXYNOS5_MASK_WDTRESET_REQUEST S5P_PMUREG(0x040C) |
195 | 191 | ||
diff --git a/arch/arm/mach-exynos/regs-sys.h b/arch/arm/mach-exynos/regs-sys.h new file mode 100644 index 000000000000..84332b0dd7a6 --- /dev/null +++ b/arch/arm/mach-exynos/regs-sys.h | |||
@@ -0,0 +1,22 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * EXYNOS - system register definition | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ASM_ARCH_REGS_SYS_H | ||
13 | #define __ASM_ARCH_REGS_SYS_H __FILE__ | ||
14 | |||
15 | #include <mach/map.h> | ||
16 | |||
17 | #define S5P_SYSREG(x) (S3C_VA_SYS + (x)) | ||
18 | |||
19 | /* For EXYNOS5 */ | ||
20 | #define EXYNOS5_SYS_I2C_CFG S5P_SYSREG(0x0234) | ||
21 | |||
22 | #endif /* __ASM_ARCH_REGS_SYS_H */ | ||
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig index 64f8e2564a37..c455e974bbfe 100644 --- a/arch/arm/mach-integrator/Kconfig +++ b/arch/arm/mach-integrator/Kconfig | |||
@@ -17,7 +17,6 @@ config ARCH_INTEGRATOR_CP | |||
17 | bool "Support Integrator/CP platform" | 17 | bool "Support Integrator/CP platform" |
18 | select ARCH_CINTEGRATOR | 18 | select ARCH_CINTEGRATOR |
19 | select ARM_TIMER_SP804 | 19 | select ARM_TIMER_SP804 |
20 | select PLAT_VERSATILE_CLCD | ||
21 | select SERIAL_AMBA_PL011 if TTY | 20 | select SERIAL_AMBA_PL011 if TTY |
22 | select SERIAL_AMBA_PL011_CONSOLE if TTY | 21 | select SERIAL_AMBA_PL011_CONSOLE if TTY |
23 | select SOC_BUS | 22 | select SOC_BUS |
diff --git a/arch/arm/mach-integrator/include/mach/memory.h b/arch/arm/mach-integrator/include/mach/memory.h deleted file mode 100644 index 7268cb50ded0..000000000000 --- a/arch/arm/mach-integrator/include/mach/memory.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-integrator/include/mach/memory.h | ||
3 | * | ||
4 | * Copyright (C) 1999 ARM Limited | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License as published by | ||
8 | * the Free Software Foundation; either version 2 of the License, or | ||
9 | * (at your option) any later version. | ||
10 | * | ||
11 | * This program is distributed in the hope that it will be useful, | ||
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
14 | * GNU General Public License for more details. | ||
15 | * | ||
16 | * You should have received a copy of the GNU General Public License | ||
17 | * along with this program; if not, write to the Free Software | ||
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
19 | */ | ||
20 | #ifndef __ASM_ARCH_MEMORY_H | ||
21 | #define __ASM_ARCH_MEMORY_H | ||
22 | |||
23 | #define BUS_OFFSET UL(0x80000000) | ||
24 | #define __virt_to_bus(x) ((x) - PAGE_OFFSET + BUS_OFFSET) | ||
25 | #define __bus_to_virt(x) ((x) - BUS_OFFSET + PAGE_OFFSET) | ||
26 | #define __pfn_to_bus(x) (__pfn_to_phys(x) + (BUS_OFFSET - PHYS_OFFSET)) | ||
27 | #define __bus_to_pfn(x) __phys_to_pfn((x) - (BUS_OFFSET - PHYS_OFFSET)) | ||
28 | |||
29 | #endif | ||
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c index 0e57f8f820a5..e39097068cf9 100644 --- a/arch/arm/mach-integrator/integrator_cp.c +++ b/arch/arm/mach-integrator/integrator_cp.c | |||
@@ -18,6 +18,7 @@ | |||
18 | #include <linux/amba/bus.h> | 18 | #include <linux/amba/bus.h> |
19 | #include <linux/amba/kmi.h> | 19 | #include <linux/amba/kmi.h> |
20 | #include <linux/amba/clcd.h> | 20 | #include <linux/amba/clcd.h> |
21 | #include <linux/platform_data/video-clcd-versatile.h> | ||
21 | #include <linux/amba/mmci.h> | 22 | #include <linux/amba/mmci.h> |
22 | #include <linux/io.h> | 23 | #include <linux/io.h> |
23 | #include <linux/irqchip/versatile-fpga.h> | 24 | #include <linux/irqchip/versatile-fpga.h> |
@@ -36,8 +37,6 @@ | |||
36 | #include <asm/mach/map.h> | 37 | #include <asm/mach/map.h> |
37 | #include <asm/mach/time.h> | 38 | #include <asm/mach/time.h> |
38 | 39 | ||
39 | #include <plat/clcd.h> | ||
40 | |||
41 | #include "hardware.h" | 40 | #include "hardware.h" |
42 | #include "cm.h" | 41 | #include "cm.h" |
43 | #include "common.h" | 42 | #include "common.h" |
diff --git a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h index fbd7ee8e4897..8c78f2b16452 100644 --- a/arch/arm/mach-mmp/include/mach/mfp-pxa910.h +++ b/arch/arm/mach-mmp/include/mach/mfp-pxa910.h | |||
@@ -23,7 +23,6 @@ | |||
23 | #define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0) | 23 | #define SM_nCS0_nCS0 MFP_CFG(SM_nCS0, AF0) |
24 | #define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0) | 24 | #define SM_ADV_SM_ADV MFP_CFG(SM_ADV, AF0) |
25 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | 25 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) |
26 | #define SM_SCLK_SM_SCLK MFP_CFG(SM_SCLK, AF0) | ||
27 | #define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1) | 26 | #define SM_BE0_SM_BE0 MFP_CFG(SM_BE0, AF1) |
28 | #define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1) | 27 | #define SM_BE1_SM_BE1 MFP_CFG(SM_BE1, AF1) |
29 | 28 | ||
diff --git a/arch/arm/mach-omap1/ocpi.c b/arch/arm/mach-omap1/ocpi.c index 238170cab5b7..44a3d19eb481 100644 --- a/arch/arm/mach-omap1/ocpi.c +++ b/arch/arm/mach-omap1/ocpi.c | |||
@@ -55,7 +55,6 @@ static struct clk *ocpi_ck; | |||
55 | 55 | ||
56 | /* | 56 | /* |
57 | * Enables device access to OMAP buses via the OCPI bridge | 57 | * Enables device access to OMAP buses via the OCPI bridge |
58 | * FIXME: Add locking | ||
59 | */ | 58 | */ |
60 | int ocpi_enable(void) | 59 | int ocpi_enable(void) |
61 | { | 60 | { |
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c index 67fd26a18441..b2ff6cd7ca9f 100644 --- a/arch/arm/mach-omap2/clkt_dpll.c +++ b/arch/arm/mach-omap2/clkt_dpll.c | |||
@@ -21,10 +21,7 @@ | |||
21 | 21 | ||
22 | #include <asm/div64.h> | 22 | #include <asm/div64.h> |
23 | 23 | ||
24 | #include "soc.h" | ||
25 | #include "clock.h" | 24 | #include "clock.h" |
26 | #include "cm-regbits-24xx.h" | ||
27 | #include "cm-regbits-34xx.h" | ||
28 | 25 | ||
29 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ | 26 | /* DPLL rate rounding: minimum DPLL multiplier, divider values */ |
30 | #define DPLL_MIN_MULTIPLIER 2 | 27 | #define DPLL_MIN_MULTIPLIER 2 |
@@ -44,20 +41,12 @@ | |||
44 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ | 41 | #define DPLL_ROUNDING_VAL ((DPLL_SCALE_BASE / 2) * \ |
45 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) | 42 | (DPLL_SCALE_FACTOR / DPLL_SCALE_BASE)) |
46 | 43 | ||
47 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ | ||
48 | #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 | ||
49 | #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 | ||
50 | #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 | ||
51 | #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 | ||
52 | |||
53 | /* | 44 | /* |
54 | * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. | 45 | * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. |
55 | * From device data manual section 4.3 "DPLL and DLL Specifications". | 46 | * From device data manual section 4.3 "DPLL and DLL Specifications". |
56 | */ | 47 | */ |
57 | #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 | 48 | #define OMAP3PLUS_DPLL_FINT_JTYPE_MIN 500000 |
58 | #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 | 49 | #define OMAP3PLUS_DPLL_FINT_JTYPE_MAX 2500000 |
59 | #define OMAP3PLUS_DPLL_FINT_MIN 32000 | ||
60 | #define OMAP3PLUS_DPLL_FINT_MAX 52000000 | ||
61 | 50 | ||
62 | /* _dpll_test_fint() return codes */ | 51 | /* _dpll_test_fint() return codes */ |
63 | #define DPLL_FINT_UNDERFLOW -1 | 52 | #define DPLL_FINT_UNDERFLOW -1 |
@@ -87,33 +76,31 @@ static int _dpll_test_fint(struct clk_hw_omap *clk, unsigned int n) | |||
87 | /* DPLL divider must result in a valid jitter correction val */ | 76 | /* DPLL divider must result in a valid jitter correction val */ |
88 | fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; | 77 | fint = __clk_get_rate(__clk_get_parent(clk->hw.clk)) / n; |
89 | 78 | ||
90 | if (cpu_is_omap24xx()) { | 79 | if (dd->flags & DPLL_J_TYPE) { |
91 | /* Should not be called for OMAP2, so warn if it is called */ | ||
92 | WARN(1, "No fint limits available for OMAP2!\n"); | ||
93 | return DPLL_FINT_INVALID; | ||
94 | } else if (cpu_is_omap3430()) { | ||
95 | fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; | ||
96 | fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; | ||
97 | } else if (dd->flags & DPLL_J_TYPE) { | ||
98 | fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; | 80 | fint_min = OMAP3PLUS_DPLL_FINT_JTYPE_MIN; |
99 | fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; | 81 | fint_max = OMAP3PLUS_DPLL_FINT_JTYPE_MAX; |
100 | } else { | 82 | } else { |
101 | fint_min = OMAP3PLUS_DPLL_FINT_MIN; | 83 | fint_min = ti_clk_features.fint_min; |
102 | fint_max = OMAP3PLUS_DPLL_FINT_MAX; | 84 | fint_max = ti_clk_features.fint_max; |
103 | } | 85 | } |
104 | 86 | ||
105 | if (fint < fint_min) { | 87 | if (!fint_min || !fint_max) { |
88 | WARN(1, "No fint limits available!\n"); | ||
89 | return DPLL_FINT_INVALID; | ||
90 | } | ||
91 | |||
92 | if (fint < ti_clk_features.fint_min) { | ||
106 | pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", | 93 | pr_debug("rejecting n=%d due to Fint failure, lowering max_divider\n", |
107 | n); | 94 | n); |
108 | dd->max_divider = n; | 95 | dd->max_divider = n; |
109 | ret = DPLL_FINT_UNDERFLOW; | 96 | ret = DPLL_FINT_UNDERFLOW; |
110 | } else if (fint > fint_max) { | 97 | } else if (fint > ti_clk_features.fint_max) { |
111 | pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", | 98 | pr_debug("rejecting n=%d due to Fint failure, boosting min_divider\n", |
112 | n); | 99 | n); |
113 | dd->min_divider = n; | 100 | dd->min_divider = n; |
114 | ret = DPLL_FINT_INVALID; | 101 | ret = DPLL_FINT_INVALID; |
115 | } else if (cpu_is_omap3430() && fint > OMAP3430_DPLL_FINT_BAND1_MAX && | 102 | } else if (fint > ti_clk_features.fint_band1_max && |
116 | fint < OMAP3430_DPLL_FINT_BAND2_MIN) { | 103 | fint < ti_clk_features.fint_band2_min) { |
117 | pr_debug("rejecting n=%d due to Fint failure\n", n); | 104 | pr_debug("rejecting n=%d due to Fint failure\n", n); |
118 | ret = DPLL_FINT_INVALID; | 105 | ret = DPLL_FINT_INVALID; |
119 | } | 106 | } |
@@ -185,6 +172,34 @@ static int _dpll_test_mult(int *m, int n, unsigned long *new_rate, | |||
185 | return r; | 172 | return r; |
186 | } | 173 | } |
187 | 174 | ||
175 | /** | ||
176 | * _omap2_dpll_is_in_bypass - check if DPLL is in bypass mode or not | ||
177 | * @v: bitfield value of the DPLL enable | ||
178 | * | ||
179 | * Checks given DPLL enable bitfield to see whether the DPLL is in bypass | ||
180 | * mode or not. Returns 1 if the DPLL is in bypass, 0 otherwise. | ||
181 | */ | ||
182 | static int _omap2_dpll_is_in_bypass(u32 v) | ||
183 | { | ||
184 | u8 mask, val; | ||
185 | |||
186 | mask = ti_clk_features.dpll_bypass_vals; | ||
187 | |||
188 | /* | ||
189 | * Each set bit in the mask corresponds to a bypass value equal | ||
190 | * to the bitshift. Go through each set-bit in the mask and | ||
191 | * compare against the given register value. | ||
192 | */ | ||
193 | while (mask) { | ||
194 | val = __ffs(mask); | ||
195 | mask ^= (1 << val); | ||
196 | if (v == val) | ||
197 | return 1; | ||
198 | } | ||
199 | |||
200 | return 0; | ||
201 | } | ||
202 | |||
188 | /* Public functions */ | 203 | /* Public functions */ |
189 | u8 omap2_init_dpll_parent(struct clk_hw *hw) | 204 | u8 omap2_init_dpll_parent(struct clk_hw *hw) |
190 | { | 205 | { |
@@ -201,20 +216,9 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) | |||
201 | v >>= __ffs(dd->enable_mask); | 216 | v >>= __ffs(dd->enable_mask); |
202 | 217 | ||
203 | /* Reparent the struct clk in case the dpll is in bypass */ | 218 | /* Reparent the struct clk in case the dpll is in bypass */ |
204 | if (cpu_is_omap24xx()) { | 219 | if (_omap2_dpll_is_in_bypass(v)) |
205 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | 220 | return 1; |
206 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | 221 | |
207 | return 1; | ||
208 | } else if (cpu_is_omap34xx()) { | ||
209 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
210 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
211 | return 1; | ||
212 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { | ||
213 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
214 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
215 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
216 | return 1; | ||
217 | } | ||
218 | return 0; | 222 | return 0; |
219 | } | 223 | } |
220 | 224 | ||
@@ -247,20 +251,8 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) | |||
247 | v &= dd->enable_mask; | 251 | v &= dd->enable_mask; |
248 | v >>= __ffs(dd->enable_mask); | 252 | v >>= __ffs(dd->enable_mask); |
249 | 253 | ||
250 | if (cpu_is_omap24xx()) { | 254 | if (_omap2_dpll_is_in_bypass(v)) |
251 | if (v == OMAP2XXX_EN_DPLL_LPBYPASS || | 255 | return __clk_get_rate(dd->clk_bypass); |
252 | v == OMAP2XXX_EN_DPLL_FRBYPASS) | ||
253 | return __clk_get_rate(dd->clk_bypass); | ||
254 | } else if (cpu_is_omap34xx()) { | ||
255 | if (v == OMAP3XXX_EN_DPLL_LPBYPASS || | ||
256 | v == OMAP3XXX_EN_DPLL_FRBYPASS) | ||
257 | return __clk_get_rate(dd->clk_bypass); | ||
258 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx()) { | ||
259 | if (v == OMAP4XXX_EN_DPLL_LPBYPASS || | ||
260 | v == OMAP4XXX_EN_DPLL_FRBYPASS || | ||
261 | v == OMAP4XXX_EN_DPLL_MNBYPASS) | ||
262 | return __clk_get_rate(dd->clk_bypass); | ||
263 | } | ||
264 | 256 | ||
265 | v = omap2_clk_readl(clk, dd->mult_div1_reg); | 257 | v = omap2_clk_readl(clk, dd->mult_div1_reg); |
266 | dpll_mult = v & dd->mult_mask; | 258 | dpll_mult = v & dd->mult_mask; |
diff --git a/arch/arm/mach-omap2/clkt_iclk.c b/arch/arm/mach-omap2/clkt_iclk.c index 333f0a666171..55eb579aeae1 100644 --- a/arch/arm/mach-omap2/clkt_iclk.c +++ b/arch/arm/mach-omap2/clkt_iclk.c | |||
@@ -14,11 +14,11 @@ | |||
14 | #include <linux/clk-provider.h> | 14 | #include <linux/clk-provider.h> |
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | 16 | ||
17 | |||
18 | #include "clock.h" | 17 | #include "clock.h" |
19 | #include "clock2xxx.h" | 18 | |
20 | #include "cm2xxx_3xxx.h" | 19 | /* Register offsets */ |
21 | #include "cm-regbits-24xx.h" | 20 | #define CM_AUTOIDLE 0x30 |
21 | #define CM_ICLKEN 0x10 | ||
22 | 22 | ||
23 | /* Private functions */ | 23 | /* Private functions */ |
24 | 24 | ||
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c index 591581a66532..5a0cac93d9ec 100644 --- a/arch/arm/mach-omap2/clock.c +++ b/arch/arm/mach-omap2/clock.c | |||
@@ -47,6 +47,24 @@ | |||
47 | u16 cpu_mask; | 47 | u16 cpu_mask; |
48 | 48 | ||
49 | /* | 49 | /* |
50 | * Clock features setup. Used instead of CPU type checks. | ||
51 | */ | ||
52 | struct ti_clk_features ti_clk_features; | ||
53 | |||
54 | /* DPLL valid Fint frequency band limits - from 34xx TRM Section 4.7.6.2 */ | ||
55 | #define OMAP3430_DPLL_FINT_BAND1_MIN 750000 | ||
56 | #define OMAP3430_DPLL_FINT_BAND1_MAX 2100000 | ||
57 | #define OMAP3430_DPLL_FINT_BAND2_MIN 7500000 | ||
58 | #define OMAP3430_DPLL_FINT_BAND2_MAX 21000000 | ||
59 | |||
60 | /* | ||
61 | * DPLL valid Fint frequency range for OMAP36xx and OMAP4xxx. | ||
62 | * From device data manual section 4.3 "DPLL and DLL Specifications". | ||
63 | */ | ||
64 | #define OMAP3PLUS_DPLL_FINT_MIN 32000 | ||
65 | #define OMAP3PLUS_DPLL_FINT_MAX 52000000 | ||
66 | |||
67 | /* | ||
50 | * clkdm_control: if true, then when a clock is enabled in the | 68 | * clkdm_control: if true, then when a clock is enabled in the |
51 | * hardware, its clockdomain will first be enabled; and when a clock | 69 | * hardware, its clockdomain will first be enabled; and when a clock |
52 | * is disabled in the hardware, its clockdomain will be disabled | 70 | * is disabled in the hardware, its clockdomain will be disabled |
@@ -287,13 +305,7 @@ void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk, | |||
287 | * 34xx reverses this, just to keep us on our toes | 305 | * 34xx reverses this, just to keep us on our toes |
288 | * AM35xx uses both, depending on the module. | 306 | * AM35xx uses both, depending on the module. |
289 | */ | 307 | */ |
290 | if (cpu_is_omap24xx()) | 308 | *idlest_val = ti_clk_features.cm_idlest_val; |
291 | *idlest_val = OMAP24XX_CM_IDLEST_VAL; | ||
292 | else if (cpu_is_omap34xx()) | ||
293 | *idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
294 | else | ||
295 | BUG(); | ||
296 | |||
297 | } | 309 | } |
298 | 310 | ||
299 | /** | 311 | /** |
@@ -731,3 +743,53 @@ void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name, | |||
731 | (clk_get_rate(core_ck) / 1000000), | 743 | (clk_get_rate(core_ck) / 1000000), |
732 | (clk_get_rate(mpu_ck) / 1000000)); | 744 | (clk_get_rate(mpu_ck) / 1000000)); |
733 | } | 745 | } |
746 | |||
747 | /** | ||
748 | * ti_clk_init_features - init clock features struct for the SoC | ||
749 | * | ||
750 | * Initializes the clock features struct based on the SoC type. | ||
751 | */ | ||
752 | void __init ti_clk_init_features(void) | ||
753 | { | ||
754 | /* Fint setup for DPLLs */ | ||
755 | if (cpu_is_omap3430()) { | ||
756 | ti_clk_features.fint_min = OMAP3430_DPLL_FINT_BAND1_MIN; | ||
757 | ti_clk_features.fint_max = OMAP3430_DPLL_FINT_BAND2_MAX; | ||
758 | ti_clk_features.fint_band1_max = OMAP3430_DPLL_FINT_BAND1_MAX; | ||
759 | ti_clk_features.fint_band2_min = OMAP3430_DPLL_FINT_BAND2_MIN; | ||
760 | } else { | ||
761 | ti_clk_features.fint_min = OMAP3PLUS_DPLL_FINT_MIN; | ||
762 | ti_clk_features.fint_max = OMAP3PLUS_DPLL_FINT_MAX; | ||
763 | } | ||
764 | |||
765 | /* Bypass value setup for DPLLs */ | ||
766 | if (cpu_is_omap24xx()) { | ||
767 | ti_clk_features.dpll_bypass_vals |= | ||
768 | (1 << OMAP2XXX_EN_DPLL_LPBYPASS) | | ||
769 | (1 << OMAP2XXX_EN_DPLL_FRBYPASS); | ||
770 | } else if (cpu_is_omap34xx()) { | ||
771 | ti_clk_features.dpll_bypass_vals |= | ||
772 | (1 << OMAP3XXX_EN_DPLL_LPBYPASS) | | ||
773 | (1 << OMAP3XXX_EN_DPLL_FRBYPASS); | ||
774 | } else if (soc_is_am33xx() || cpu_is_omap44xx() || soc_is_am43xx() || | ||
775 | soc_is_omap54xx() || soc_is_dra7xx()) { | ||
776 | ti_clk_features.dpll_bypass_vals |= | ||
777 | (1 << OMAP4XXX_EN_DPLL_LPBYPASS) | | ||
778 | (1 << OMAP4XXX_EN_DPLL_FRBYPASS) | | ||
779 | (1 << OMAP4XXX_EN_DPLL_MNBYPASS); | ||
780 | } | ||
781 | |||
782 | /* Jitter correction only available on OMAP343X */ | ||
783 | if (cpu_is_omap343x()) | ||
784 | ti_clk_features.flags |= TI_CLK_DPLL_HAS_FREQSEL; | ||
785 | |||
786 | /* Idlest value for interface clocks. | ||
787 | * 24xx uses 0 to indicate not ready, and 1 to indicate ready. | ||
788 | * 34xx reverses this, just to keep us on our toes | ||
789 | * AM35xx uses both, depending on the module. | ||
790 | */ | ||
791 | if (cpu_is_omap24xx()) | ||
792 | ti_clk_features.cm_idlest_val = OMAP24XX_CM_IDLEST_VAL; | ||
793 | else if (cpu_is_omap34xx()) | ||
794 | ti_clk_features.cm_idlest_val = OMAP34XX_CM_IDLEST_VAL; | ||
795 | } | ||
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h index 12f54d428d7c..0f100dc4e97f 100644 --- a/arch/arm/mach-omap2/clock.h +++ b/arch/arm/mach-omap2/clock.h | |||
@@ -101,31 +101,6 @@ struct clockdomain; | |||
101 | }; \ | 101 | }; \ |
102 | DEFINE_STRUCT_CLK(_name, _parent_names, _ops); | 102 | DEFINE_STRUCT_CLK(_name, _parent_names, _ops); |
103 | 103 | ||
104 | #define DEFINE_CLK_OMAP_HSDIVIDER(_name, _parent_name, \ | ||
105 | _parent_ptr, _flags, \ | ||
106 | _clksel_reg, _clksel_mask) \ | ||
107 | static const struct clksel _name##_div[] = { \ | ||
108 | { \ | ||
109 | .parent = _parent_ptr, \ | ||
110 | .rates = div31_1to31_rates \ | ||
111 | }, \ | ||
112 | { .parent = NULL }, \ | ||
113 | }; \ | ||
114 | static struct clk _name; \ | ||
115 | static const char *_name##_parent_names[] = { \ | ||
116 | _parent_name, \ | ||
117 | }; \ | ||
118 | static struct clk_hw_omap _name##_hw = { \ | ||
119 | .hw = { \ | ||
120 | .clk = &_name, \ | ||
121 | }, \ | ||
122 | .clksel = _name##_div, \ | ||
123 | .clksel_reg = _clksel_reg, \ | ||
124 | .clksel_mask = _clksel_mask, \ | ||
125 | .ops = &clkhwops_omap4_dpllmx, \ | ||
126 | }; \ | ||
127 | DEFINE_STRUCT_CLK(_name, _name##_parent_names, omap_hsdivider_ops); | ||
128 | |||
129 | /* struct clksel_rate.flags possibilities */ | 104 | /* struct clksel_rate.flags possibilities */ |
130 | #define RATE_IN_242X (1 << 0) | 105 | #define RATE_IN_242X (1 << 0) |
131 | #define RATE_IN_243X (1 << 1) | 106 | #define RATE_IN_243X (1 << 1) |
@@ -248,6 +223,23 @@ void omap2_clk_writel(u32 val, struct clk_hw_omap *clk, void __iomem *reg); | |||
248 | 223 | ||
249 | extern u16 cpu_mask; | 224 | extern u16 cpu_mask; |
250 | 225 | ||
226 | /* | ||
227 | * Clock features setup. Used instead of CPU type checks. | ||
228 | */ | ||
229 | struct ti_clk_features { | ||
230 | u32 flags; | ||
231 | long fint_min; | ||
232 | long fint_max; | ||
233 | long fint_band1_max; | ||
234 | long fint_band2_min; | ||
235 | u8 dpll_bypass_vals; | ||
236 | u8 cm_idlest_val; | ||
237 | }; | ||
238 | |||
239 | #define TI_CLK_DPLL_HAS_FREQSEL (1 << 0) | ||
240 | |||
241 | extern struct ti_clk_features ti_clk_features; | ||
242 | |||
251 | extern const struct clkops clkops_omap2_dflt_wait; | 243 | extern const struct clkops clkops_omap2_dflt_wait; |
252 | extern const struct clkops clkops_dummy; | 244 | extern const struct clkops clkops_dummy; |
253 | extern const struct clkops clkops_omap2_dflt; | 245 | extern const struct clkops clkops_omap2_dflt; |
@@ -286,4 +278,6 @@ extern int omap2_clkops_enable_clkdm(struct clk_hw *hw); | |||
286 | extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); | 278 | extern void omap2_clkops_disable_clkdm(struct clk_hw *hw); |
287 | 279 | ||
288 | extern void omap_clocks_register(struct omap_clk *oclks, int cnt); | 280 | extern void omap_clocks_register(struct omap_clk *oclks, int cnt); |
281 | |||
282 | void __init ti_clk_init_features(void); | ||
289 | #endif | 283 | #endif |
diff --git a/arch/arm/mach-omap2/control.c b/arch/arm/mach-omap2/control.c index 751f3549bf6f..f4796c002070 100644 --- a/arch/arm/mach-omap2/control.c +++ b/arch/arm/mach-omap2/control.c | |||
@@ -44,8 +44,7 @@ struct omap3_scratchpad { | |||
44 | }; | 44 | }; |
45 | 45 | ||
46 | struct omap3_scratchpad_prcm_block { | 46 | struct omap3_scratchpad_prcm_block { |
47 | u32 prm_clksrc_ctrl; | 47 | u32 prm_contents[2]; |
48 | u32 prm_clksel; | ||
49 | u32 cm_contents[11]; | 48 | u32 cm_contents[11]; |
50 | u32 prcm_block_size; | 49 | u32 prcm_block_size; |
51 | }; | 50 | }; |
@@ -282,13 +281,9 @@ void omap3_clear_scratchpad_contents(void) | |||
282 | void __iomem *v_addr; | 281 | void __iomem *v_addr; |
283 | u32 offset = 0; | 282 | u32 offset = 0; |
284 | v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); | 283 | v_addr = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD_ROM); |
285 | if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & | 284 | if (omap3xxx_prm_clear_global_cold_reset()) { |
286 | OMAP3430_GLOBAL_COLD_RST_MASK) { | ||
287 | for ( ; offset <= max_offset; offset += 0x4) | 285 | for ( ; offset <= max_offset; offset += 0x4) |
288 | writel_relaxed(0x0, (v_addr + offset)); | 286 | writel_relaxed(0x0, (v_addr + offset)); |
289 | omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, | ||
290 | OMAP3430_GR_MOD, | ||
291 | OMAP3_PRM_RSTST_OFFSET); | ||
292 | } | 287 | } |
293 | } | 288 | } |
294 | 289 | ||
@@ -331,13 +326,7 @@ void omap3_save_scratchpad_contents(void) | |||
331 | scratchpad_contents.sdrc_block_offset = 0x64; | 326 | scratchpad_contents.sdrc_block_offset = 0x64; |
332 | 327 | ||
333 | /* Populate the PRCM block contents */ | 328 | /* Populate the PRCM block contents */ |
334 | prcm_block_contents.prm_clksrc_ctrl = | 329 | omap3_prm_save_scratchpad_contents(prcm_block_contents.prm_contents); |
335 | omap2_prm_read_mod_reg(OMAP3430_GR_MOD, | ||
336 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | ||
337 | prcm_block_contents.prm_clksel = | ||
338 | omap2_prm_read_mod_reg(OMAP3430_CCR_MOD, | ||
339 | OMAP3_PRM_CLKSEL_OFFSET); | ||
340 | |||
341 | omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); | 330 | omap3_cm_save_scratchpad_contents(prcm_block_contents.cm_contents); |
342 | 331 | ||
343 | prcm_block_contents.prcm_block_size = 0x0; | 332 | prcm_block_contents.prcm_block_size = 0x0; |
@@ -575,9 +564,50 @@ int omap3_ctrl_save_padconf(void) | |||
575 | * Sets the bootmode for IVA2 to idle. This is needed by the PM code to | 564 | * Sets the bootmode for IVA2 to idle. This is needed by the PM code to |
576 | * force disable IVA2 so that it does not prevent any low-power states. | 565 | * force disable IVA2 so that it does not prevent any low-power states. |
577 | */ | 566 | */ |
578 | void omap3_ctrl_set_iva_bootmode_idle(void) | 567 | static void __init omap3_ctrl_set_iva_bootmode_idle(void) |
579 | { | 568 | { |
580 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, | 569 | omap_ctrl_writel(OMAP3_IVA2_BOOTMOD_IDLE, |
581 | OMAP343X_CONTROL_IVA2_BOOTMOD); | 570 | OMAP343X_CONTROL_IVA2_BOOTMOD); |
582 | } | 571 | } |
572 | |||
573 | /** | ||
574 | * omap3_ctrl_setup_d2d_padconf - setup stacked modem pads for idle | ||
575 | * | ||
576 | * Sets up the pads controlling the stacked modem in such way that the | ||
577 | * device can enter idle. | ||
578 | */ | ||
579 | static void __init omap3_ctrl_setup_d2d_padconf(void) | ||
580 | { | ||
581 | u16 mask, padconf; | ||
582 | |||
583 | /* | ||
584 | * In a stand alone OMAP3430 where there is not a stacked | ||
585 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | ||
586 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | ||
587 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. | ||
588 | */ | ||
589 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | ||
590 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | ||
591 | padconf |= mask; | ||
592 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | ||
593 | |||
594 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | ||
595 | padconf |= mask; | ||
596 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | ||
597 | } | ||
598 | |||
599 | /** | ||
600 | * omap3_ctrl_init - does static initializations for control module | ||
601 | * | ||
602 | * Initializes system control module. This sets up the sysconfig autoidle, | ||
603 | * and sets up modem and iva2 so that they can be idled properly. | ||
604 | */ | ||
605 | void __init omap3_ctrl_init(void) | ||
606 | { | ||
607 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); | ||
608 | |||
609 | omap3_ctrl_set_iva_bootmode_idle(); | ||
610 | |||
611 | omap3_ctrl_setup_d2d_padconf(); | ||
612 | } | ||
583 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ | 613 | #endif /* CONFIG_ARCH_OMAP3 && CONFIG_PM */ |
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h index da054801b114..a3c013345c45 100644 --- a/arch/arm/mach-omap2/control.h +++ b/arch/arm/mach-omap2/control.h | |||
@@ -16,11 +16,6 @@ | |||
16 | #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H | 16 | #ifndef __ARCH_ARM_MACH_OMAP2_CONTROL_H |
17 | #define __ARCH_ARM_MACH_OMAP2_CONTROL_H | 17 | #define __ARCH_ARM_MACH_OMAP2_CONTROL_H |
18 | 18 | ||
19 | #include "ctrl_module_core_44xx.h" | ||
20 | #include "ctrl_module_wkup_44xx.h" | ||
21 | #include "ctrl_module_pad_core_44xx.h" | ||
22 | #include "ctrl_module_pad_wkup_44xx.h" | ||
23 | |||
24 | #include "am33xx.h" | 19 | #include "am33xx.h" |
25 | 20 | ||
26 | #ifndef __ASSEMBLY__ | 21 | #ifndef __ASSEMBLY__ |
@@ -254,6 +249,39 @@ | |||
254 | /* TI81XX CONTROL_DEVCONF register offsets */ | 249 | /* TI81XX CONTROL_DEVCONF register offsets */ |
255 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) | 250 | #define TI81XX_CONTROL_DEVICE_ID (TI81XX_CONTROL_DEVCONF + 0x000) |
256 | 251 | ||
252 | /* OMAP4 CONTROL MODULE */ | ||
253 | #define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 | ||
254 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 | ||
255 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 | ||
256 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 | ||
257 | #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 | ||
258 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 | ||
259 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 | ||
260 | |||
261 | /* OMAP4 CONTROL_DSIPHY */ | ||
262 | #define OMAP4_DSI2_LANEENABLE_SHIFT 29 | ||
263 | #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) | ||
264 | #define OMAP4_DSI1_LANEENABLE_SHIFT 24 | ||
265 | #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) | ||
266 | #define OMAP4_DSI1_PIPD_SHIFT 19 | ||
267 | #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) | ||
268 | #define OMAP4_DSI2_PIPD_SHIFT 14 | ||
269 | #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) | ||
270 | |||
271 | /* OMAP4 CONTROL_CAMERA_RX */ | ||
272 | #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 | ||
273 | #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) | ||
274 | #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 | ||
275 | #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) | ||
276 | #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 | ||
277 | #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) | ||
278 | #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 | ||
279 | #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) | ||
280 | #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 | ||
281 | #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) | ||
282 | #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 | ||
283 | #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) | ||
284 | |||
257 | /* OMAP54XX CONTROL STATUS register */ | 285 | /* OMAP54XX CONTROL STATUS register */ |
258 | #define OMAP5XXX_CONTROL_STATUS 0x134 | 286 | #define OMAP5XXX_CONTROL_STATUS 0x134 |
259 | #define OMAP5_DEVICETYPE_MASK (0x7 << 6) | 287 | #define OMAP5_DEVICETYPE_MASK (0x7 << 6) |
@@ -427,7 +455,7 @@ extern void omap_ctrl_write_dsp_boot_addr(u32 bootaddr); | |||
427 | extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); | 455 | extern void omap_ctrl_write_dsp_boot_mode(u8 bootmode); |
428 | extern void omap3630_ctrl_disable_rta(void); | 456 | extern void omap3630_ctrl_disable_rta(void); |
429 | extern int omap3_ctrl_save_padconf(void); | 457 | extern int omap3_ctrl_save_padconf(void); |
430 | extern void omap3_ctrl_set_iva_bootmode_idle(void); | 458 | void omap3_ctrl_init(void); |
431 | extern void omap2_set_globals_control(void __iomem *ctrl, | 459 | extern void omap2_set_globals_control(void __iomem *ctrl, |
432 | void __iomem *ctrl_pad); | 460 | void __iomem *ctrl_pad); |
433 | #else | 461 | #else |
diff --git a/arch/arm/mach-omap2/ctrl_module_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_core_44xx.h deleted file mode 100644 index 01970824e0e5..000000000000 --- a/arch/arm/mach-omap2/ctrl_module_core_44xx.h +++ /dev/null | |||
@@ -1,392 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP44xx CTRL_MODULE_CORE registers and bitfields | ||
3 | * | ||
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
5 | * | ||
6 | * Benoit Cousson (b-cousson@ti.com) | ||
7 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
8 | * | ||
9 | * This file is automatically generated from the OMAP hardware databases. | ||
10 | * We respectfully ask that any modifications to this file be coordinated | ||
11 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
12 | * authors above to ensure that the autogeneration scripts are kept | ||
13 | * up-to-date with the file contents. | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License version 2 as | ||
17 | * published by the Free Software Foundation. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H | ||
21 | #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_CORE_44XX_H | ||
22 | |||
23 | |||
24 | /* Base address */ | ||
25 | #define OMAP4_CTRL_MODULE_CORE 0x4a002000 | ||
26 | |||
27 | /* Registers offset */ | ||
28 | #define OMAP4_CTRL_MODULE_CORE_IP_REVISION 0x0000 | ||
29 | #define OMAP4_CTRL_MODULE_CORE_IP_HWINFO 0x0004 | ||
30 | #define OMAP4_CTRL_MODULE_CORE_IP_SYSCONFIG 0x0010 | ||
31 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_0 0x0200 | ||
32 | #define OMAP4_CTRL_MODULE_CORE_ID_CODE 0x0204 | ||
33 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_1 0x0208 | ||
34 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_2 0x020c | ||
35 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_DIE_ID_3 0x0210 | ||
36 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_0 0x0214 | ||
37 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_PROD_ID_1 0x0218 | ||
38 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_USB_CONF 0x021c | ||
39 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_VDD_WKUP 0x0228 | ||
40 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_BGAP 0x0260 | ||
41 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_0 0x0264 | ||
42 | #define OMAP4_CTRL_MODULE_CORE_STD_FUSE_OPP_DPLL_1 0x0268 | ||
43 | #define OMAP4_CTRL_MODULE_CORE_STATUS 0x02c4 | ||
44 | #define OMAP4_CTRL_MODULE_CORE_DEV_CONF 0x0300 | ||
45 | #define OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR 0x0304 | ||
46 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_IVA_VOLTAGE_CTRL 0x0314 | ||
47 | #define OMAP4_CTRL_MODULE_CORE_LDOVBB_MPU_VOLTAGE_CTRL 0x0318 | ||
48 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_IVA_VOLTAGE_CTRL 0x0320 | ||
49 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_MPU_VOLTAGE_CTRL 0x0324 | ||
50 | #define OMAP4_CTRL_MODULE_CORE_LDOSRAM_CORE_VOLTAGE_CTRL 0x0328 | ||
51 | #define OMAP4_CTRL_MODULE_CORE_TEMP_SENSOR 0x032c | ||
52 | #define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_0 0x0330 | ||
53 | #define OMAP4_CTRL_MODULE_CORE_DPLL_NWELL_TRIM_1 0x0334 | ||
54 | #define OMAP4_CTRL_MODULE_CORE_USBOTGHS_CONTROL 0x033c | ||
55 | #define OMAP4_CTRL_MODULE_CORE_DSS_CONTROL 0x0340 | ||
56 | #define OMAP4_CTRL_MODULE_CORE_HWOBS_CONTROL 0x0350 | ||
57 | #define OMAP4_CTRL_MODULE_CORE_DEBOBS_FINAL_MUX_SEL 0x0400 | ||
58 | #define OMAP4_CTRL_MODULE_CORE_DEBOBS_MMR_MPU 0x0408 | ||
59 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL0 0x042c | ||
60 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL1 0x0430 | ||
61 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL2 0x0434 | ||
62 | #define OMAP4_CTRL_MODULE_CORE_CONF_SDMA_REQ_SEL3 0x0438 | ||
63 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL0 0x0440 | ||
64 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL1 0x0444 | ||
65 | #define OMAP4_CTRL_MODULE_CORE_CONF_CLK_SEL2 0x0448 | ||
66 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_FREQLOCK_SEL 0x044c | ||
67 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_TINITZ_SEL 0x0450 | ||
68 | #define OMAP4_CTRL_MODULE_CORE_CONF_DPLL_PHASELOCK_SEL 0x0454 | ||
69 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_0 0x0480 | ||
70 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_1 0x0484 | ||
71 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_2 0x0488 | ||
72 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_3 0x048c | ||
73 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_4 0x0490 | ||
74 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_5 0x0494 | ||
75 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_6 0x0498 | ||
76 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_7 0x049c | ||
77 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_8 0x04a0 | ||
78 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_9 0x04a4 | ||
79 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_10 0x04a8 | ||
80 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_11 0x04ac | ||
81 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_12 0x04b0 | ||
82 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_13 0x04b4 | ||
83 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_14 0x04b8 | ||
84 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_15 0x04bc | ||
85 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_16 0x04c0 | ||
86 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_17 0x04c4 | ||
87 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_18 0x04c8 | ||
88 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_19 0x04cc | ||
89 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_20 0x04d0 | ||
90 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_21 0x04d4 | ||
91 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_22 0x04d8 | ||
92 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_23 0x04dc | ||
93 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_24 0x04e0 | ||
94 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_25 0x04e4 | ||
95 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_26 0x04e8 | ||
96 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_27 0x04ec | ||
97 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_28 0x04f0 | ||
98 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_29 0x04f4 | ||
99 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_30 0x04f8 | ||
100 | #define OMAP4_CTRL_MODULE_CORE_CONF_DEBUG_SEL_TST_31 0x04fc | ||
101 | |||
102 | /* Registers shifts and masks */ | ||
103 | |||
104 | /* IP_REVISION */ | ||
105 | #define OMAP4_IP_REV_SCHEME_SHIFT 30 | ||
106 | #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) | ||
107 | #define OMAP4_IP_REV_FUNC_SHIFT 16 | ||
108 | #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) | ||
109 | #define OMAP4_IP_REV_RTL_SHIFT 11 | ||
110 | #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) | ||
111 | #define OMAP4_IP_REV_MAJOR_SHIFT 8 | ||
112 | #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) | ||
113 | #define OMAP4_IP_REV_CUSTOM_SHIFT 6 | ||
114 | #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) | ||
115 | #define OMAP4_IP_REV_MINOR_SHIFT 0 | ||
116 | #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) | ||
117 | |||
118 | /* IP_HWINFO */ | ||
119 | #define OMAP4_IP_HWINFO_SHIFT 0 | ||
120 | #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) | ||
121 | |||
122 | /* IP_SYSCONFIG */ | ||
123 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 | ||
124 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) | ||
125 | |||
126 | /* STD_FUSE_DIE_ID_0 */ | ||
127 | #define OMAP4_STD_FUSE_DIE_ID_0_SHIFT 0 | ||
128 | #define OMAP4_STD_FUSE_DIE_ID_0_MASK (0xffffffff << 0) | ||
129 | |||
130 | /* ID_CODE */ | ||
131 | #define OMAP4_STD_FUSE_IDCODE_SHIFT 0 | ||
132 | #define OMAP4_STD_FUSE_IDCODE_MASK (0xffffffff << 0) | ||
133 | |||
134 | /* STD_FUSE_DIE_ID_1 */ | ||
135 | #define OMAP4_STD_FUSE_DIE_ID_1_SHIFT 0 | ||
136 | #define OMAP4_STD_FUSE_DIE_ID_1_MASK (0xffffffff << 0) | ||
137 | |||
138 | /* STD_FUSE_DIE_ID_2 */ | ||
139 | #define OMAP4_STD_FUSE_DIE_ID_2_SHIFT 0 | ||
140 | #define OMAP4_STD_FUSE_DIE_ID_2_MASK (0xffffffff << 0) | ||
141 | |||
142 | /* STD_FUSE_DIE_ID_3 */ | ||
143 | #define OMAP4_STD_FUSE_DIE_ID_3_SHIFT 0 | ||
144 | #define OMAP4_STD_FUSE_DIE_ID_3_MASK (0xffffffff << 0) | ||
145 | |||
146 | /* STD_FUSE_PROD_ID_0 */ | ||
147 | #define OMAP4_STD_FUSE_PROD_ID_0_SHIFT 0 | ||
148 | #define OMAP4_STD_FUSE_PROD_ID_0_MASK (0xffffffff << 0) | ||
149 | |||
150 | /* STD_FUSE_PROD_ID_1 */ | ||
151 | #define OMAP4_STD_FUSE_PROD_ID_1_SHIFT 0 | ||
152 | #define OMAP4_STD_FUSE_PROD_ID_1_MASK (0xffffffff << 0) | ||
153 | |||
154 | /* STD_FUSE_USB_CONF */ | ||
155 | #define OMAP4_USB_PROD_ID_SHIFT 16 | ||
156 | #define OMAP4_USB_PROD_ID_MASK (0xffff << 16) | ||
157 | #define OMAP4_USB_VENDOR_ID_SHIFT 0 | ||
158 | #define OMAP4_USB_VENDOR_ID_MASK (0xffff << 0) | ||
159 | |||
160 | /* STD_FUSE_OPP_VDD_WKUP */ | ||
161 | #define OMAP4_STD_FUSE_OPP_VDD_WKUP_SHIFT 0 | ||
162 | #define OMAP4_STD_FUSE_OPP_VDD_WKUP_MASK (0xffffffff << 0) | ||
163 | |||
164 | /* STD_FUSE_OPP_BGAP */ | ||
165 | #define OMAP4_STD_FUSE_OPP_BGAP_SHIFT 0 | ||
166 | #define OMAP4_STD_FUSE_OPP_BGAP_MASK (0xffffffff << 0) | ||
167 | |||
168 | /* STD_FUSE_OPP_DPLL_0 */ | ||
169 | #define OMAP4_STD_FUSE_OPP_DPLL_0_SHIFT 0 | ||
170 | #define OMAP4_STD_FUSE_OPP_DPLL_0_MASK (0xffffffff << 0) | ||
171 | |||
172 | /* STD_FUSE_OPP_DPLL_1 */ | ||
173 | #define OMAP4_STD_FUSE_OPP_DPLL_1_SHIFT 0 | ||
174 | #define OMAP4_STD_FUSE_OPP_DPLL_1_MASK (0xffffffff << 0) | ||
175 | |||
176 | /* STATUS */ | ||
177 | #define OMAP4_ATTILA_CONF_SHIFT 11 | ||
178 | #define OMAP4_ATTILA_CONF_MASK (0x3 << 11) | ||
179 | #define OMAP4_DEVICE_TYPE_SHIFT 8 | ||
180 | #define OMAP4_DEVICE_TYPE_MASK (0x7 << 8) | ||
181 | #define OMAP4_SYS_BOOT_SHIFT 0 | ||
182 | #define OMAP4_SYS_BOOT_MASK (0xff << 0) | ||
183 | |||
184 | /* DEV_CONF */ | ||
185 | #define OMAP4_DEV_CONF_SHIFT 1 | ||
186 | #define OMAP4_DEV_CONF_MASK (0x7fffffff << 1) | ||
187 | #define OMAP4_USBPHY_PD_SHIFT 0 | ||
188 | #define OMAP4_USBPHY_PD_MASK (1 << 0) | ||
189 | |||
190 | /* LDOVBB_IVA_VOLTAGE_CTRL */ | ||
191 | #define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_SHIFT 26 | ||
192 | #define OMAP4_LDOVBBIVA_RBB_MUX_CTRL_MASK (1 << 26) | ||
193 | #define OMAP4_LDOVBBIVA_RBB_VSET_IN_SHIFT 21 | ||
194 | #define OMAP4_LDOVBBIVA_RBB_VSET_IN_MASK (0x1f << 21) | ||
195 | #define OMAP4_LDOVBBIVA_RBB_VSET_OUT_SHIFT 16 | ||
196 | #define OMAP4_LDOVBBIVA_RBB_VSET_OUT_MASK (0x1f << 16) | ||
197 | #define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_SHIFT 10 | ||
198 | #define OMAP4_LDOVBBIVA_FBB_MUX_CTRL_MASK (1 << 10) | ||
199 | #define OMAP4_LDOVBBIVA_FBB_VSET_IN_SHIFT 5 | ||
200 | #define OMAP4_LDOVBBIVA_FBB_VSET_IN_MASK (0x1f << 5) | ||
201 | #define OMAP4_LDOVBBIVA_FBB_VSET_OUT_SHIFT 0 | ||
202 | #define OMAP4_LDOVBBIVA_FBB_VSET_OUT_MASK (0x1f << 0) | ||
203 | |||
204 | /* LDOVBB_MPU_VOLTAGE_CTRL */ | ||
205 | #define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_SHIFT 26 | ||
206 | #define OMAP4_LDOVBBMPU_RBB_MUX_CTRL_MASK (1 << 26) | ||
207 | #define OMAP4_LDOVBBMPU_RBB_VSET_IN_SHIFT 21 | ||
208 | #define OMAP4_LDOVBBMPU_RBB_VSET_IN_MASK (0x1f << 21) | ||
209 | #define OMAP4_LDOVBBMPU_RBB_VSET_OUT_SHIFT 16 | ||
210 | #define OMAP4_LDOVBBMPU_RBB_VSET_OUT_MASK (0x1f << 16) | ||
211 | #define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_SHIFT 10 | ||
212 | #define OMAP4_LDOVBBMPU_FBB_MUX_CTRL_MASK (1 << 10) | ||
213 | #define OMAP4_LDOVBBMPU_FBB_VSET_IN_SHIFT 5 | ||
214 | #define OMAP4_LDOVBBMPU_FBB_VSET_IN_MASK (0x1f << 5) | ||
215 | #define OMAP4_LDOVBBMPU_FBB_VSET_OUT_SHIFT 0 | ||
216 | #define OMAP4_LDOVBBMPU_FBB_VSET_OUT_MASK (0x1f << 0) | ||
217 | |||
218 | /* LDOSRAM_IVA_VOLTAGE_CTRL */ | ||
219 | #define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_SHIFT 26 | ||
220 | #define OMAP4_LDOSRAMIVA_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
221 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_SHIFT 21 | ||
222 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
223 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_SHIFT 16 | ||
224 | #define OMAP4_LDOSRAMIVA_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
225 | #define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_SHIFT 10 | ||
226 | #define OMAP4_LDOSRAMIVA_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
227 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_SHIFT 5 | ||
228 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
229 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_SHIFT 0 | ||
230 | #define OMAP4_LDOSRAMIVA_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
231 | |||
232 | /* LDOSRAM_MPU_VOLTAGE_CTRL */ | ||
233 | #define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_SHIFT 26 | ||
234 | #define OMAP4_LDOSRAMMPU_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
235 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_SHIFT 21 | ||
236 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
237 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_SHIFT 16 | ||
238 | #define OMAP4_LDOSRAMMPU_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
239 | #define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_SHIFT 10 | ||
240 | #define OMAP4_LDOSRAMMPU_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
241 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_SHIFT 5 | ||
242 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
243 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_SHIFT 0 | ||
244 | #define OMAP4_LDOSRAMMPU_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
245 | |||
246 | /* LDOSRAM_CORE_VOLTAGE_CTRL */ | ||
247 | #define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_SHIFT 26 | ||
248 | #define OMAP4_LDOSRAMCORE_RETMODE_MUX_CTRL_MASK (1 << 26) | ||
249 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_SHIFT 21 | ||
250 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_IN_MASK (0x1f << 21) | ||
251 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_SHIFT 16 | ||
252 | #define OMAP4_LDOSRAMCORE_RETMODE_VSET_OUT_MASK (0x1f << 16) | ||
253 | #define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_SHIFT 10 | ||
254 | #define OMAP4_LDOSRAMCORE_ACTMODE_MUX_CTRL_MASK (1 << 10) | ||
255 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_SHIFT 5 | ||
256 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_IN_MASK (0x1f << 5) | ||
257 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_SHIFT 0 | ||
258 | #define OMAP4_LDOSRAMCORE_ACTMODE_VSET_OUT_MASK (0x1f << 0) | ||
259 | |||
260 | /* TEMP_SENSOR */ | ||
261 | #define OMAP4_BGAP_TEMPSOFF_SHIFT 12 | ||
262 | #define OMAP4_BGAP_TEMPSOFF_MASK (1 << 12) | ||
263 | #define OMAP4_BGAP_TSHUT_SHIFT 11 | ||
264 | #define OMAP4_BGAP_TSHUT_MASK (1 << 11) | ||
265 | #define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_SHIFT 10 | ||
266 | #define OMAP4_BGAP_TEMP_SENSOR_CONTCONV_MASK (1 << 10) | ||
267 | #define OMAP4_BGAP_TEMP_SENSOR_SOC_SHIFT 9 | ||
268 | #define OMAP4_BGAP_TEMP_SENSOR_SOC_MASK (1 << 9) | ||
269 | #define OMAP4_BGAP_TEMP_SENSOR_EOCZ_SHIFT 8 | ||
270 | #define OMAP4_BGAP_TEMP_SENSOR_EOCZ_MASK (1 << 8) | ||
271 | #define OMAP4_BGAP_TEMP_SENSOR_DTEMP_SHIFT 0 | ||
272 | #define OMAP4_BGAP_TEMP_SENSOR_DTEMP_MASK (0xff << 0) | ||
273 | |||
274 | /* DPLL_NWELL_TRIM_0 */ | ||
275 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_SHIFT 29 | ||
276 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) | ||
277 | #define OMAP4_DPLL_ABE_NWELL_TRIM_SHIFT 24 | ||
278 | #define OMAP4_DPLL_ABE_NWELL_TRIM_MASK (0x1f << 24) | ||
279 | #define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_SHIFT 23 | ||
280 | #define OMAP4_DPLL_PER_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) | ||
281 | #define OMAP4_DPLL_PER_NWELL_TRIM_SHIFT 18 | ||
282 | #define OMAP4_DPLL_PER_NWELL_TRIM_MASK (0x1f << 18) | ||
283 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_SHIFT 17 | ||
284 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) | ||
285 | #define OMAP4_DPLL_CORE_NWELL_TRIM_SHIFT 12 | ||
286 | #define OMAP4_DPLL_CORE_NWELL_TRIM_MASK (0x1f << 12) | ||
287 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_SHIFT 11 | ||
288 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) | ||
289 | #define OMAP4_DPLL_IVA_NWELL_TRIM_SHIFT 6 | ||
290 | #define OMAP4_DPLL_IVA_NWELL_TRIM_MASK (0x1f << 6) | ||
291 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_SHIFT 5 | ||
292 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) | ||
293 | #define OMAP4_DPLL_MPU_NWELL_TRIM_SHIFT 0 | ||
294 | #define OMAP4_DPLL_MPU_NWELL_TRIM_MASK (0x1f << 0) | ||
295 | |||
296 | /* DPLL_NWELL_TRIM_1 */ | ||
297 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_SHIFT 29 | ||
298 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MUX_CTRL_MASK (1 << 29) | ||
299 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_SHIFT 24 | ||
300 | #define OMAP4_DPLL_UNIPRO_NWELL_TRIM_MASK (0x1f << 24) | ||
301 | #define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_SHIFT 23 | ||
302 | #define OMAP4_DPLL_USB_NWELL_TRIM_MUX_CTRL_MASK (1 << 23) | ||
303 | #define OMAP4_DPLL_USB_NWELL_TRIM_SHIFT 18 | ||
304 | #define OMAP4_DPLL_USB_NWELL_TRIM_MASK (0x1f << 18) | ||
305 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_SHIFT 17 | ||
306 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MUX_CTRL_MASK (1 << 17) | ||
307 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_SHIFT 12 | ||
308 | #define OMAP4_DPLL_HDMI_NWELL_TRIM_MASK (0x1f << 12) | ||
309 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_SHIFT 11 | ||
310 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MUX_CTRL_MASK (1 << 11) | ||
311 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_SHIFT 6 | ||
312 | #define OMAP4_DPLL_DSI2_NWELL_TRIM_MASK (0x1f << 6) | ||
313 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_SHIFT 5 | ||
314 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MUX_CTRL_MASK (1 << 5) | ||
315 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_SHIFT 0 | ||
316 | #define OMAP4_DPLL_DSI1_NWELL_TRIM_MASK (0x1f << 0) | ||
317 | |||
318 | /* USBOTGHS_CONTROL */ | ||
319 | #define OMAP4_DISCHRGVBUS_SHIFT 8 | ||
320 | #define OMAP4_DISCHRGVBUS_MASK (1 << 8) | ||
321 | #define OMAP4_CHRGVBUS_SHIFT 7 | ||
322 | #define OMAP4_CHRGVBUS_MASK (1 << 7) | ||
323 | #define OMAP4_DRVVBUS_SHIFT 6 | ||
324 | #define OMAP4_DRVVBUS_MASK (1 << 6) | ||
325 | #define OMAP4_IDPULLUP_SHIFT 5 | ||
326 | #define OMAP4_IDPULLUP_MASK (1 << 5) | ||
327 | #define OMAP4_IDDIG_SHIFT 4 | ||
328 | #define OMAP4_IDDIG_MASK (1 << 4) | ||
329 | #define OMAP4_SESSEND_SHIFT 3 | ||
330 | #define OMAP4_SESSEND_MASK (1 << 3) | ||
331 | #define OMAP4_VBUSVALID_SHIFT 2 | ||
332 | #define OMAP4_VBUSVALID_MASK (1 << 2) | ||
333 | #define OMAP4_BVALID_SHIFT 1 | ||
334 | #define OMAP4_BVALID_MASK (1 << 1) | ||
335 | #define OMAP4_AVALID_SHIFT 0 | ||
336 | #define OMAP4_AVALID_MASK (1 << 0) | ||
337 | |||
338 | /* DSS_CONTROL */ | ||
339 | #define OMAP4_DSS_MUX6_SELECT_SHIFT 0 | ||
340 | #define OMAP4_DSS_MUX6_SELECT_MASK (1 << 0) | ||
341 | |||
342 | /* HWOBS_CONTROL */ | ||
343 | #define OMAP4_HWOBS_CLKDIV_SEL_SHIFT 3 | ||
344 | #define OMAP4_HWOBS_CLKDIV_SEL_MASK (0x1f << 3) | ||
345 | #define OMAP4_HWOBS_ALL_ZERO_MODE_SHIFT 2 | ||
346 | #define OMAP4_HWOBS_ALL_ZERO_MODE_MASK (1 << 2) | ||
347 | #define OMAP4_HWOBS_ALL_ONE_MODE_SHIFT 1 | ||
348 | #define OMAP4_HWOBS_ALL_ONE_MODE_MASK (1 << 1) | ||
349 | #define OMAP4_HWOBS_MACRO_ENABLE_SHIFT 0 | ||
350 | #define OMAP4_HWOBS_MACRO_ENABLE_MASK (1 << 0) | ||
351 | |||
352 | /* DEBOBS_FINAL_MUX_SEL */ | ||
353 | #define OMAP4_SELECT_SHIFT 0 | ||
354 | #define OMAP4_SELECT_MASK (0xffffffff << 0) | ||
355 | |||
356 | /* DEBOBS_MMR_MPU */ | ||
357 | #define OMAP4_SELECT_DEBOBS_MMR_MPU_SHIFT 0 | ||
358 | #define OMAP4_SELECT_DEBOBS_MMR_MPU_MASK (0xf << 0) | ||
359 | |||
360 | /* CONF_SDMA_REQ_SEL0 */ | ||
361 | #define OMAP4_MULT_SHIFT 0 | ||
362 | #define OMAP4_MULT_MASK (0x7f << 0) | ||
363 | |||
364 | /* CONF_CLK_SEL0 */ | ||
365 | #define OMAP4_MULT_CONF_CLK_SEL0_SHIFT 0 | ||
366 | #define OMAP4_MULT_CONF_CLK_SEL0_MASK (0x7 << 0) | ||
367 | |||
368 | /* CONF_CLK_SEL1 */ | ||
369 | #define OMAP4_MULT_CONF_CLK_SEL1_SHIFT 0 | ||
370 | #define OMAP4_MULT_CONF_CLK_SEL1_MASK (0x7 << 0) | ||
371 | |||
372 | /* CONF_CLK_SEL2 */ | ||
373 | #define OMAP4_MULT_CONF_CLK_SEL2_SHIFT 0 | ||
374 | #define OMAP4_MULT_CONF_CLK_SEL2_MASK (0x7 << 0) | ||
375 | |||
376 | /* CONF_DPLL_FREQLOCK_SEL */ | ||
377 | #define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_SHIFT 0 | ||
378 | #define OMAP4_MULT_CONF_DPLL_FREQLOCK_SEL_MASK (0x7 << 0) | ||
379 | |||
380 | /* CONF_DPLL_TINITZ_SEL */ | ||
381 | #define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_SHIFT 0 | ||
382 | #define OMAP4_MULT_CONF_DPLL_TINITZ_SEL_MASK (0x7 << 0) | ||
383 | |||
384 | /* CONF_DPLL_PHASELOCK_SEL */ | ||
385 | #define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_SHIFT 0 | ||
386 | #define OMAP4_MULT_CONF_DPLL_PHASELOCK_SEL_MASK (0x7 << 0) | ||
387 | |||
388 | /* CONF_DEBUG_SEL_TST_0 */ | ||
389 | #define OMAP4_MODE_SHIFT 0 | ||
390 | #define OMAP4_MODE_MASK (0xf << 0) | ||
391 | |||
392 | #endif | ||
diff --git a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h deleted file mode 100644 index c88420de1151..000000000000 --- a/arch/arm/mach-omap2/ctrl_module_pad_core_44xx.h +++ /dev/null | |||
@@ -1,1409 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP44xx CTRL_MODULE_PAD_CORE registers and bitfields | ||
3 | * | ||
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
5 | * | ||
6 | * Benoit Cousson (b-cousson@ti.com) | ||
7 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
8 | * | ||
9 | * This file is automatically generated from the OMAP hardware databases. | ||
10 | * We respectfully ask that any modifications to this file be coordinated | ||
11 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
12 | * authors above to ensure that the autogeneration scripts are kept | ||
13 | * up-to-date with the file contents. | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License version 2 as | ||
17 | * published by the Free Software Foundation. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H | ||
21 | #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_CORE_44XX_H | ||
22 | |||
23 | |||
24 | /* Base address */ | ||
25 | #define OMAP4_CTRL_MODULE_PAD_CORE 0x4a100000 | ||
26 | |||
27 | /* Registers offset */ | ||
28 | #define OMAP4_CTRL_MODULE_PAD_CORE_IP_REVISION 0x0000 | ||
29 | #define OMAP4_CTRL_MODULE_PAD_CORE_IP_HWINFO 0x0004 | ||
30 | #define OMAP4_CTRL_MODULE_PAD_CORE_IP_SYSCONFIG 0x0010 | ||
31 | #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_0 0x01d8 | ||
32 | #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_1 0x01dc | ||
33 | #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_2 0x01e0 | ||
34 | #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_3 0x01e4 | ||
35 | #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_4 0x01e8 | ||
36 | #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_5 0x01ec | ||
37 | #define OMAP4_CTRL_MODULE_PAD_CORE_PADCONF_WAKEUPEVENT_6 0x01f0 | ||
38 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_GLOBAL 0x05a0 | ||
39 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PADCONF_MODE 0x05a4 | ||
40 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_0 0x05a8 | ||
41 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART1IO_PADCONF_1 0x05ac | ||
42 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_0 0x05b0 | ||
43 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART2IO_PADCONF_1 0x05b4 | ||
44 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_0 0x05b8 | ||
45 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_1 0x05bc | ||
46 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SMART3IO_PADCONF_2 0x05c0 | ||
47 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USBB_HSIC 0x05c4 | ||
48 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_SLIMBUS 0x05c8 | ||
49 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_PBIASLITE 0x0600 | ||
50 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_0 0x0604 | ||
51 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_CAMERA_RX 0x0608 | ||
52 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_AVDAC 0x060c | ||
53 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDMI_TX_PHY 0x0610 | ||
54 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC2 0x0614 | ||
55 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_DSIPHY 0x0618 | ||
56 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MCBSPLP 0x061c | ||
57 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB2PHYCORE 0x0620 | ||
58 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_I2C_1 0x0624 | ||
59 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_MMC1 0x0628 | ||
60 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HSI 0x062c | ||
61 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_USB 0x0630 | ||
62 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_HDQ 0x0634 | ||
63 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_0 0x0638 | ||
64 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_1 0x063c | ||
65 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_2 0x0640 | ||
66 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO1_3 0x0644 | ||
67 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_0 0x0648 | ||
68 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_1 0x064c | ||
69 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_2 0x0650 | ||
70 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_LPDDR2IO2_3 0x0654 | ||
71 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_BUS_HOLD 0x0658 | ||
72 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_C2C 0x065c | ||
73 | #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_RW 0x0660 | ||
74 | #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R 0x0664 | ||
75 | #define OMAP4_CTRL_MODULE_PAD_CORE_CORE_CONTROL_SPARE_R_C0 0x0668 | ||
76 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_1 0x0700 | ||
77 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_2 0x0704 | ||
78 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_3 0x0708 | ||
79 | #define OMAP4_CTRL_MODULE_PAD_CORE_CONTROL_EFUSE_4 0x070c | ||
80 | |||
81 | /* Registers shifts and masks */ | ||
82 | |||
83 | /* IP_REVISION */ | ||
84 | #define OMAP4_IP_REV_SCHEME_SHIFT 30 | ||
85 | #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) | ||
86 | #define OMAP4_IP_REV_FUNC_SHIFT 16 | ||
87 | #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) | ||
88 | #define OMAP4_IP_REV_RTL_SHIFT 11 | ||
89 | #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) | ||
90 | #define OMAP4_IP_REV_MAJOR_SHIFT 8 | ||
91 | #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) | ||
92 | #define OMAP4_IP_REV_CUSTOM_SHIFT 6 | ||
93 | #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) | ||
94 | #define OMAP4_IP_REV_MINOR_SHIFT 0 | ||
95 | #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) | ||
96 | |||
97 | /* IP_HWINFO */ | ||
98 | #define OMAP4_IP_HWINFO_SHIFT 0 | ||
99 | #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) | ||
100 | |||
101 | /* IP_SYSCONFIG */ | ||
102 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 | ||
103 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) | ||
104 | |||
105 | /* PADCONF_WAKEUPEVENT_0 */ | ||
106 | #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_SHIFT 31 | ||
107 | #define OMAP4_GPMC_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 31) | ||
108 | #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_SHIFT 30 | ||
109 | #define OMAP4_GPMC_NWP_DUPLICATEWAKEUPEVENT_MASK (1 << 30) | ||
110 | #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_SHIFT 29 | ||
111 | #define OMAP4_GPMC_NCS3_DUPLICATEWAKEUPEVENT_MASK (1 << 29) | ||
112 | #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_SHIFT 28 | ||
113 | #define OMAP4_GPMC_NCS2_DUPLICATEWAKEUPEVENT_MASK (1 << 28) | ||
114 | #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_SHIFT 27 | ||
115 | #define OMAP4_GPMC_NCS1_DUPLICATEWAKEUPEVENT_MASK (1 << 27) | ||
116 | #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_SHIFT 26 | ||
117 | #define OMAP4_GPMC_NCS0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) | ||
118 | #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_SHIFT 25 | ||
119 | #define OMAP4_GPMC_A25_DUPLICATEWAKEUPEVENT_MASK (1 << 25) | ||
120 | #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_SHIFT 24 | ||
121 | #define OMAP4_GPMC_A24_DUPLICATEWAKEUPEVENT_MASK (1 << 24) | ||
122 | #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_SHIFT 23 | ||
123 | #define OMAP4_GPMC_A23_DUPLICATEWAKEUPEVENT_MASK (1 << 23) | ||
124 | #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_SHIFT 22 | ||
125 | #define OMAP4_GPMC_A22_DUPLICATEWAKEUPEVENT_MASK (1 << 22) | ||
126 | #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_SHIFT 21 | ||
127 | #define OMAP4_GPMC_A21_DUPLICATEWAKEUPEVENT_MASK (1 << 21) | ||
128 | #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_SHIFT 20 | ||
129 | #define OMAP4_GPMC_A20_DUPLICATEWAKEUPEVENT_MASK (1 << 20) | ||
130 | #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_SHIFT 19 | ||
131 | #define OMAP4_GPMC_A19_DUPLICATEWAKEUPEVENT_MASK (1 << 19) | ||
132 | #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_SHIFT 18 | ||
133 | #define OMAP4_GPMC_A18_DUPLICATEWAKEUPEVENT_MASK (1 << 18) | ||
134 | #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_SHIFT 17 | ||
135 | #define OMAP4_GPMC_A17_DUPLICATEWAKEUPEVENT_MASK (1 << 17) | ||
136 | #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_SHIFT 16 | ||
137 | #define OMAP4_GPMC_A16_DUPLICATEWAKEUPEVENT_MASK (1 << 16) | ||
138 | #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_SHIFT 15 | ||
139 | #define OMAP4_GPMC_AD15_DUPLICATEWAKEUPEVENT_MASK (1 << 15) | ||
140 | #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_SHIFT 14 | ||
141 | #define OMAP4_GPMC_AD14_DUPLICATEWAKEUPEVENT_MASK (1 << 14) | ||
142 | #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_SHIFT 13 | ||
143 | #define OMAP4_GPMC_AD13_DUPLICATEWAKEUPEVENT_MASK (1 << 13) | ||
144 | #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_SHIFT 12 | ||
145 | #define OMAP4_GPMC_AD12_DUPLICATEWAKEUPEVENT_MASK (1 << 12) | ||
146 | #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_SHIFT 11 | ||
147 | #define OMAP4_GPMC_AD11_DUPLICATEWAKEUPEVENT_MASK (1 << 11) | ||
148 | #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_SHIFT 10 | ||
149 | #define OMAP4_GPMC_AD10_DUPLICATEWAKEUPEVENT_MASK (1 << 10) | ||
150 | #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_SHIFT 9 | ||
151 | #define OMAP4_GPMC_AD9_DUPLICATEWAKEUPEVENT_MASK (1 << 9) | ||
152 | #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_SHIFT 8 | ||
153 | #define OMAP4_GPMC_AD8_DUPLICATEWAKEUPEVENT_MASK (1 << 8) | ||
154 | #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
155 | #define OMAP4_GPMC_AD7_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
156 | #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
157 | #define OMAP4_GPMC_AD6_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
158 | #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
159 | #define OMAP4_GPMC_AD5_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
160 | #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
161 | #define OMAP4_GPMC_AD4_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
162 | #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
163 | #define OMAP4_GPMC_AD3_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
164 | #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
165 | #define OMAP4_GPMC_AD2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
166 | #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
167 | #define OMAP4_GPMC_AD1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
168 | #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
169 | #define OMAP4_GPMC_AD0_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
170 | |||
171 | /* PADCONF_WAKEUPEVENT_1 */ | ||
172 | #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 31 | ||
173 | #define OMAP4_CAM_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 31) | ||
174 | #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_SHIFT 30 | ||
175 | #define OMAP4_CAM_SHUTTER_DUPLICATEWAKEUPEVENT_MASK (1 << 30) | ||
176 | #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_SHIFT 29 | ||
177 | #define OMAP4_CSI22_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) | ||
178 | #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_SHIFT 28 | ||
179 | #define OMAP4_CSI22_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 28) | ||
180 | #define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_SHIFT 27 | ||
181 | #define OMAP4_CSI22_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 27) | ||
182 | #define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_SHIFT 26 | ||
183 | #define OMAP4_CSI22_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 26) | ||
184 | #define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_SHIFT 25 | ||
185 | #define OMAP4_CSI21_DY4_DUPLICATEWAKEUPEVENT_MASK (1 << 25) | ||
186 | #define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_SHIFT 24 | ||
187 | #define OMAP4_CSI21_DX4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) | ||
188 | #define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_SHIFT 23 | ||
189 | #define OMAP4_CSI21_DY3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) | ||
190 | #define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_SHIFT 22 | ||
191 | #define OMAP4_CSI21_DX3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) | ||
192 | #define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_SHIFT 21 | ||
193 | #define OMAP4_CSI21_DY2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) | ||
194 | #define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_SHIFT 20 | ||
195 | #define OMAP4_CSI21_DX2_DUPLICATEWAKEUPEVENT_MASK (1 << 20) | ||
196 | #define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_SHIFT 19 | ||
197 | #define OMAP4_CSI21_DY1_DUPLICATEWAKEUPEVENT_MASK (1 << 19) | ||
198 | #define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_SHIFT 18 | ||
199 | #define OMAP4_CSI21_DX1_DUPLICATEWAKEUPEVENT_MASK (1 << 18) | ||
200 | #define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_SHIFT 17 | ||
201 | #define OMAP4_CSI21_DY0_DUPLICATEWAKEUPEVENT_MASK (1 << 17) | ||
202 | #define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_SHIFT 16 | ||
203 | #define OMAP4_CSI21_DX0_DUPLICATEWAKEUPEVENT_MASK (1 << 16) | ||
204 | #define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_SHIFT 15 | ||
205 | #define OMAP4_HDMI_DDC_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 15) | ||
206 | #define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_SHIFT 14 | ||
207 | #define OMAP4_HDMI_DDC_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 14) | ||
208 | #define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_SHIFT 13 | ||
209 | #define OMAP4_HDMI_CEC_DUPLICATEWAKEUPEVENT_MASK (1 << 13) | ||
210 | #define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_SHIFT 12 | ||
211 | #define OMAP4_HDMI_HPD_DUPLICATEWAKEUPEVENT_MASK (1 << 12) | ||
212 | #define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_SHIFT 11 | ||
213 | #define OMAP4_C2C_DATA15_DUPLICATEWAKEUPEVENT_MASK (1 << 11) | ||
214 | #define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_SHIFT 10 | ||
215 | #define OMAP4_C2C_DATA14_DUPLICATEWAKEUPEVENT_MASK (1 << 10) | ||
216 | #define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_SHIFT 9 | ||
217 | #define OMAP4_C2C_DATA13_DUPLICATEWAKEUPEVENT_MASK (1 << 9) | ||
218 | #define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_SHIFT 8 | ||
219 | #define OMAP4_C2C_DATA12_DUPLICATEWAKEUPEVENT_MASK (1 << 8) | ||
220 | #define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
221 | #define OMAP4_C2C_DATA11_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
222 | #define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
223 | #define OMAP4_GPMC_WAIT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
224 | #define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
225 | #define OMAP4_GPMC_WAIT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
226 | #define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
227 | #define OMAP4_GPMC_NBE1_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
228 | #define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
229 | #define OMAP4_GPMC_NBE0_CLE_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
230 | #define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
231 | #define OMAP4_GPMC_NWE_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
232 | #define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
233 | #define OMAP4_GPMC_NOE_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
234 | #define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
235 | #define OMAP4_GPMC_NADV_ALE_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
236 | |||
237 | /* PADCONF_WAKEUPEVENT_2 */ | ||
238 | #define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 31 | ||
239 | #define OMAP4_ABE_MCBSP1_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 31) | ||
240 | #define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_SHIFT 30 | ||
241 | #define OMAP4_ABE_MCBSP2_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 30) | ||
242 | #define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_SHIFT 29 | ||
243 | #define OMAP4_ABE_MCBSP2_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 29) | ||
244 | #define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_SHIFT 28 | ||
245 | #define OMAP4_ABE_MCBSP2_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 28) | ||
246 | #define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_SHIFT 27 | ||
247 | #define OMAP4_ABE_MCBSP2_CLKX_DUPLICATEWAKEUPEVENT_MASK (1 << 27) | ||
248 | #define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 26 | ||
249 | #define OMAP4_SDMMC1_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 26) | ||
250 | #define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 25 | ||
251 | #define OMAP4_SDMMC1_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 25) | ||
252 | #define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 24 | ||
253 | #define OMAP4_SDMMC1_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 24) | ||
254 | #define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 23 | ||
255 | #define OMAP4_SDMMC1_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 23) | ||
256 | #define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 22 | ||
257 | #define OMAP4_SDMMC1_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 22) | ||
258 | #define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 21 | ||
259 | #define OMAP4_SDMMC1_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 21) | ||
260 | #define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 20 | ||
261 | #define OMAP4_SDMMC1_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 20) | ||
262 | #define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 19 | ||
263 | #define OMAP4_SDMMC1_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 19) | ||
264 | #define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_SHIFT 18 | ||
265 | #define OMAP4_SDMMC1_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 18) | ||
266 | #define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 17 | ||
267 | #define OMAP4_SDMMC1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 17) | ||
268 | #define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_SHIFT 16 | ||
269 | #define OMAP4_USBC1_ICUSB_DM_DUPLICATEWAKEUPEVENT_MASK (1 << 16) | ||
270 | #define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_SHIFT 15 | ||
271 | #define OMAP4_USBC1_ICUSB_DP_DUPLICATEWAKEUPEVENT_MASK (1 << 15) | ||
272 | #define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 14 | ||
273 | #define OMAP4_USBB1_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 14) | ||
274 | #define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 13 | ||
275 | #define OMAP4_USBB1_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 13) | ||
276 | #define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 12 | ||
277 | #define OMAP4_USBB1_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 12) | ||
278 | #define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 11 | ||
279 | #define OMAP4_USBB1_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 11) | ||
280 | #define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 10 | ||
281 | #define OMAP4_USBB1_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 10) | ||
282 | #define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 9 | ||
283 | #define OMAP4_USBB1_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 9) | ||
284 | #define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 8 | ||
285 | #define OMAP4_USBB1_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 8) | ||
286 | #define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
287 | #define OMAP4_USBB1_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
288 | #define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
289 | #define OMAP4_USBB1_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
290 | #define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
291 | #define OMAP4_USBB1_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
292 | #define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
293 | #define OMAP4_USBB1_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
294 | #define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
295 | #define OMAP4_USBB1_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
296 | #define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
297 | #define OMAP4_USBB1_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
298 | #define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
299 | #define OMAP4_USBB1_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
300 | #define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
301 | #define OMAP4_CAM_GLOBALRESET_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
302 | |||
303 | /* PADCONF_WAKEUPEVENT_3 */ | ||
304 | #define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_SHIFT 31 | ||
305 | #define OMAP4_MCSPI1_CS3_DUPLICATEWAKEUPEVENT_MASK (1 << 31) | ||
306 | #define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_SHIFT 30 | ||
307 | #define OMAP4_MCSPI1_CS2_DUPLICATEWAKEUPEVENT_MASK (1 << 30) | ||
308 | #define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_SHIFT 29 | ||
309 | #define OMAP4_MCSPI1_CS1_DUPLICATEWAKEUPEVENT_MASK (1 << 29) | ||
310 | #define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_SHIFT 28 | ||
311 | #define OMAP4_MCSPI1_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 28) | ||
312 | #define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 27 | ||
313 | #define OMAP4_MCSPI1_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 27) | ||
314 | #define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 26 | ||
315 | #define OMAP4_MCSPI1_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 26) | ||
316 | #define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_SHIFT 25 | ||
317 | #define OMAP4_MCSPI1_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 25) | ||
318 | #define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_SHIFT 24 | ||
319 | #define OMAP4_I2C4_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 24) | ||
320 | #define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_SHIFT 23 | ||
321 | #define OMAP4_I2C4_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 23) | ||
322 | #define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_SHIFT 22 | ||
323 | #define OMAP4_I2C3_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 22) | ||
324 | #define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_SHIFT 21 | ||
325 | #define OMAP4_I2C3_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 21) | ||
326 | #define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_SHIFT 20 | ||
327 | #define OMAP4_I2C2_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 20) | ||
328 | #define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_SHIFT 19 | ||
329 | #define OMAP4_I2C2_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 19) | ||
330 | #define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_SHIFT 18 | ||
331 | #define OMAP4_I2C1_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 18) | ||
332 | #define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_SHIFT 17 | ||
333 | #define OMAP4_I2C1_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 17) | ||
334 | #define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_SHIFT 16 | ||
335 | #define OMAP4_HDQ_SIO_DUPLICATEWAKEUPEVENT_MASK (1 << 16) | ||
336 | #define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 | ||
337 | #define OMAP4_UART2_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) | ||
338 | #define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 | ||
339 | #define OMAP4_UART2_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) | ||
340 | #define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_SHIFT 13 | ||
341 | #define OMAP4_UART2_RTS_DUPLICATEWAKEUPEVENT_MASK (1 << 13) | ||
342 | #define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_SHIFT 12 | ||
343 | #define OMAP4_UART2_CTS_DUPLICATEWAKEUPEVENT_MASK (1 << 12) | ||
344 | #define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_SHIFT 11 | ||
345 | #define OMAP4_ABE_DMIC_DIN3_DUPLICATEWAKEUPEVENT_MASK (1 << 11) | ||
346 | #define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_SHIFT 10 | ||
347 | #define OMAP4_ABE_DMIC_DIN2_DUPLICATEWAKEUPEVENT_MASK (1 << 10) | ||
348 | #define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_SHIFT 9 | ||
349 | #define OMAP4_ABE_DMIC_DIN1_DUPLICATEWAKEUPEVENT_MASK (1 << 9) | ||
350 | #define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_SHIFT 8 | ||
351 | #define OMAP4_ABE_DMIC_CLK1_DUPLICATEWAKEUPEVENT_MASK (1 << 8) | ||
352 | #define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
353 | #define OMAP4_ABE_CLKS_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
354 | #define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
355 | #define OMAP4_ABE_PDM_LB_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
356 | #define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
357 | #define OMAP4_ABE_PDM_FRAME_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
358 | #define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
359 | #define OMAP4_ABE_PDM_DL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
360 | #define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
361 | #define OMAP4_ABE_PDM_UL_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
362 | #define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
363 | #define OMAP4_ABE_MCBSP1_FSX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
364 | #define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
365 | #define OMAP4_ABE_MCBSP1_DX_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
366 | #define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
367 | #define OMAP4_ABE_MCBSP1_DR_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
368 | |||
369 | /* PADCONF_WAKEUPEVENT_4 */ | ||
370 | #define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_SHIFT 31 | ||
371 | #define OMAP4_UNIPRO_TY0_DUPLICATEWAKEUPEVENT_MASK (1 << 31) | ||
372 | #define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_SHIFT 30 | ||
373 | #define OMAP4_UNIPRO_TX0_DUPLICATEWAKEUPEVENT_MASK (1 << 30) | ||
374 | #define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_SHIFT 29 | ||
375 | #define OMAP4_USBB2_HSIC_STROBE_DUPLICATEWAKEUPEVENT_MASK (1 << 29) | ||
376 | #define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_SHIFT 28 | ||
377 | #define OMAP4_USBB2_HSIC_DATA_DUPLICATEWAKEUPEVENT_MASK (1 << 28) | ||
378 | #define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_SHIFT 27 | ||
379 | #define OMAP4_USBB2_ULPITLL_DAT7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) | ||
380 | #define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_SHIFT 26 | ||
381 | #define OMAP4_USBB2_ULPITLL_DAT6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) | ||
382 | #define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_SHIFT 25 | ||
383 | #define OMAP4_USBB2_ULPITLL_DAT5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) | ||
384 | #define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_SHIFT 24 | ||
385 | #define OMAP4_USBB2_ULPITLL_DAT4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) | ||
386 | #define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 23 | ||
387 | #define OMAP4_USBB2_ULPITLL_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) | ||
388 | #define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 22 | ||
389 | #define OMAP4_USBB2_ULPITLL_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) | ||
390 | #define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 21 | ||
391 | #define OMAP4_USBB2_ULPITLL_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) | ||
392 | #define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 20 | ||
393 | #define OMAP4_USBB2_ULPITLL_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) | ||
394 | #define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_SHIFT 19 | ||
395 | #define OMAP4_USBB2_ULPITLL_NXT_DUPLICATEWAKEUPEVENT_MASK (1 << 19) | ||
396 | #define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_SHIFT 18 | ||
397 | #define OMAP4_USBB2_ULPITLL_DIR_DUPLICATEWAKEUPEVENT_MASK (1 << 18) | ||
398 | #define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_SHIFT 17 | ||
399 | #define OMAP4_USBB2_ULPITLL_STP_DUPLICATEWAKEUPEVENT_MASK (1 << 17) | ||
400 | #define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_SHIFT 16 | ||
401 | #define OMAP4_USBB2_ULPITLL_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 16) | ||
402 | #define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_SHIFT 15 | ||
403 | #define OMAP4_UART4_TX_DUPLICATEWAKEUPEVENT_MASK (1 << 15) | ||
404 | #define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_SHIFT 14 | ||
405 | #define OMAP4_UART4_RX_DUPLICATEWAKEUPEVENT_MASK (1 << 14) | ||
406 | #define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_SHIFT 13 | ||
407 | #define OMAP4_MCSPI4_CS0_DUPLICATEWAKEUPEVENT_MASK (1 << 13) | ||
408 | #define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_SHIFT 12 | ||
409 | #define OMAP4_MCSPI4_SOMI_DUPLICATEWAKEUPEVENT_MASK (1 << 12) | ||
410 | #define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_SHIFT 11 | ||
411 | #define OMAP4_MCSPI4_SIMO_DUPLICATEWAKEUPEVENT_MASK (1 << 11) | ||
412 | #define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_SHIFT 10 | ||
413 | #define OMAP4_MCSPI4_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 10) | ||
414 | #define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_SHIFT 9 | ||
415 | #define OMAP4_SDMMC5_DAT3_DUPLICATEWAKEUPEVENT_MASK (1 << 9) | ||
416 | #define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_SHIFT 8 | ||
417 | #define OMAP4_SDMMC5_DAT2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) | ||
418 | #define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
419 | #define OMAP4_SDMMC5_DAT1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
420 | #define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
421 | #define OMAP4_SDMMC5_DAT0_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
422 | #define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
423 | #define OMAP4_SDMMC5_CMD_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
424 | #define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
425 | #define OMAP4_SDMMC5_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
426 | #define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
427 | #define OMAP4_UART3_TX_IRTX_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
428 | #define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
429 | #define OMAP4_UART3_RX_IRRX_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
430 | #define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
431 | #define OMAP4_UART3_RTS_SD_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
432 | #define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
433 | #define OMAP4_UART3_CTS_RCTX_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
434 | |||
435 | /* PADCONF_WAKEUPEVENT_5 */ | ||
436 | #define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_SHIFT 31 | ||
437 | #define OMAP4_DPM_EMU11_DUPLICATEWAKEUPEVENT_MASK (1 << 31) | ||
438 | #define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_SHIFT 30 | ||
439 | #define OMAP4_DPM_EMU10_DUPLICATEWAKEUPEVENT_MASK (1 << 30) | ||
440 | #define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_SHIFT 29 | ||
441 | #define OMAP4_DPM_EMU9_DUPLICATEWAKEUPEVENT_MASK (1 << 29) | ||
442 | #define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_SHIFT 28 | ||
443 | #define OMAP4_DPM_EMU8_DUPLICATEWAKEUPEVENT_MASK (1 << 28) | ||
444 | #define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_SHIFT 27 | ||
445 | #define OMAP4_DPM_EMU7_DUPLICATEWAKEUPEVENT_MASK (1 << 27) | ||
446 | #define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_SHIFT 26 | ||
447 | #define OMAP4_DPM_EMU6_DUPLICATEWAKEUPEVENT_MASK (1 << 26) | ||
448 | #define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_SHIFT 25 | ||
449 | #define OMAP4_DPM_EMU5_DUPLICATEWAKEUPEVENT_MASK (1 << 25) | ||
450 | #define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_SHIFT 24 | ||
451 | #define OMAP4_DPM_EMU4_DUPLICATEWAKEUPEVENT_MASK (1 << 24) | ||
452 | #define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_SHIFT 23 | ||
453 | #define OMAP4_DPM_EMU3_DUPLICATEWAKEUPEVENT_MASK (1 << 23) | ||
454 | #define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_SHIFT 22 | ||
455 | #define OMAP4_DPM_EMU2_DUPLICATEWAKEUPEVENT_MASK (1 << 22) | ||
456 | #define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_SHIFT 21 | ||
457 | #define OMAP4_DPM_EMU1_DUPLICATEWAKEUPEVENT_MASK (1 << 21) | ||
458 | #define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_SHIFT 20 | ||
459 | #define OMAP4_DPM_EMU0_DUPLICATEWAKEUPEVENT_MASK (1 << 20) | ||
460 | #define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_SHIFT 19 | ||
461 | #define OMAP4_SYS_BOOT5_DUPLICATEWAKEUPEVENT_MASK (1 << 19) | ||
462 | #define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_SHIFT 18 | ||
463 | #define OMAP4_SYS_BOOT4_DUPLICATEWAKEUPEVENT_MASK (1 << 18) | ||
464 | #define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_SHIFT 17 | ||
465 | #define OMAP4_SYS_BOOT3_DUPLICATEWAKEUPEVENT_MASK (1 << 17) | ||
466 | #define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_SHIFT 16 | ||
467 | #define OMAP4_SYS_BOOT2_DUPLICATEWAKEUPEVENT_MASK (1 << 16) | ||
468 | #define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_SHIFT 15 | ||
469 | #define OMAP4_SYS_BOOT1_DUPLICATEWAKEUPEVENT_MASK (1 << 15) | ||
470 | #define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_SHIFT 14 | ||
471 | #define OMAP4_SYS_BOOT0_DUPLICATEWAKEUPEVENT_MASK (1 << 14) | ||
472 | #define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_SHIFT 13 | ||
473 | #define OMAP4_SYS_NIRQ2_DUPLICATEWAKEUPEVENT_MASK (1 << 13) | ||
474 | #define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_SHIFT 12 | ||
475 | #define OMAP4_SYS_NIRQ1_DUPLICATEWAKEUPEVENT_MASK (1 << 12) | ||
476 | #define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_SHIFT 11 | ||
477 | #define OMAP4_FREF_CLK2_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 11) | ||
478 | #define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 | ||
479 | #define OMAP4_FREF_CLK1_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) | ||
480 | #define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_SHIFT 9 | ||
481 | #define OMAP4_UNIPRO_RY2_DUPLICATEWAKEUPEVENT_MASK (1 << 9) | ||
482 | #define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_SHIFT 8 | ||
483 | #define OMAP4_UNIPRO_RX2_DUPLICATEWAKEUPEVENT_MASK (1 << 8) | ||
484 | #define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
485 | #define OMAP4_UNIPRO_RY1_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
486 | #define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
487 | #define OMAP4_UNIPRO_RX1_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
488 | #define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
489 | #define OMAP4_UNIPRO_RY0_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
490 | #define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
491 | #define OMAP4_UNIPRO_RX0_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
492 | #define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
493 | #define OMAP4_UNIPRO_TY2_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
494 | #define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
495 | #define OMAP4_UNIPRO_TX2_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
496 | #define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
497 | #define OMAP4_UNIPRO_TY1_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
498 | #define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
499 | #define OMAP4_UNIPRO_TX1_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
500 | |||
501 | /* PADCONF_WAKEUPEVENT_6 */ | ||
502 | #define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
503 | #define OMAP4_DPM_EMU19_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
504 | #define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
505 | #define OMAP4_DPM_EMU18_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
506 | #define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
507 | #define OMAP4_DPM_EMU17_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
508 | #define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
509 | #define OMAP4_DPM_EMU16_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
510 | #define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
511 | #define OMAP4_DPM_EMU15_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
512 | #define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
513 | #define OMAP4_DPM_EMU14_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
514 | #define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
515 | #define OMAP4_DPM_EMU13_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
516 | #define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
517 | #define OMAP4_DPM_EMU12_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
518 | |||
519 | /* CONTROL_PADCONF_GLOBAL */ | ||
520 | #define OMAP4_FORCE_OFFMODE_EN_SHIFT 31 | ||
521 | #define OMAP4_FORCE_OFFMODE_EN_MASK (1 << 31) | ||
522 | |||
523 | /* CONTROL_PADCONF_MODE */ | ||
524 | #define OMAP4_VDDS_DV_BANK0_SHIFT 31 | ||
525 | #define OMAP4_VDDS_DV_BANK0_MASK (1 << 31) | ||
526 | #define OMAP4_VDDS_DV_BANK1_SHIFT 30 | ||
527 | #define OMAP4_VDDS_DV_BANK1_MASK (1 << 30) | ||
528 | #define OMAP4_VDDS_DV_BANK3_SHIFT 29 | ||
529 | #define OMAP4_VDDS_DV_BANK3_MASK (1 << 29) | ||
530 | #define OMAP4_VDDS_DV_BANK4_SHIFT 28 | ||
531 | #define OMAP4_VDDS_DV_BANK4_MASK (1 << 28) | ||
532 | #define OMAP4_VDDS_DV_BANK5_SHIFT 27 | ||
533 | #define OMAP4_VDDS_DV_BANK5_MASK (1 << 27) | ||
534 | #define OMAP4_VDDS_DV_BANK6_SHIFT 26 | ||
535 | #define OMAP4_VDDS_DV_BANK6_MASK (1 << 26) | ||
536 | #define OMAP4_VDDS_DV_C2C_SHIFT 25 | ||
537 | #define OMAP4_VDDS_DV_C2C_MASK (1 << 25) | ||
538 | #define OMAP4_VDDS_DV_CAM_SHIFT 24 | ||
539 | #define OMAP4_VDDS_DV_CAM_MASK (1 << 24) | ||
540 | #define OMAP4_VDDS_DV_GPMC_SHIFT 23 | ||
541 | #define OMAP4_VDDS_DV_GPMC_MASK (1 << 23) | ||
542 | #define OMAP4_VDDS_DV_SDMMC2_SHIFT 22 | ||
543 | #define OMAP4_VDDS_DV_SDMMC2_MASK (1 << 22) | ||
544 | |||
545 | /* CONTROL_SMART1IO_PADCONF_0 */ | ||
546 | #define OMAP4_ABE_DR0_SC_SHIFT 30 | ||
547 | #define OMAP4_ABE_DR0_SC_MASK (0x3 << 30) | ||
548 | #define OMAP4_CAM_DR0_SC_SHIFT 28 | ||
549 | #define OMAP4_CAM_DR0_SC_MASK (0x3 << 28) | ||
550 | #define OMAP4_FREF_DR2_SC_SHIFT 26 | ||
551 | #define OMAP4_FREF_DR2_SC_MASK (0x3 << 26) | ||
552 | #define OMAP4_FREF_DR3_SC_SHIFT 24 | ||
553 | #define OMAP4_FREF_DR3_SC_MASK (0x3 << 24) | ||
554 | #define OMAP4_GPIO_DR8_SC_SHIFT 22 | ||
555 | #define OMAP4_GPIO_DR8_SC_MASK (0x3 << 22) | ||
556 | #define OMAP4_GPIO_DR9_SC_SHIFT 20 | ||
557 | #define OMAP4_GPIO_DR9_SC_MASK (0x3 << 20) | ||
558 | #define OMAP4_GPMC_DR2_SC_SHIFT 18 | ||
559 | #define OMAP4_GPMC_DR2_SC_MASK (0x3 << 18) | ||
560 | #define OMAP4_GPMC_DR3_SC_SHIFT 16 | ||
561 | #define OMAP4_GPMC_DR3_SC_MASK (0x3 << 16) | ||
562 | #define OMAP4_GPMC_DR6_SC_SHIFT 14 | ||
563 | #define OMAP4_GPMC_DR6_SC_MASK (0x3 << 14) | ||
564 | #define OMAP4_HDMI_DR0_SC_SHIFT 12 | ||
565 | #define OMAP4_HDMI_DR0_SC_MASK (0x3 << 12) | ||
566 | #define OMAP4_MCSPI1_DR0_SC_SHIFT 10 | ||
567 | #define OMAP4_MCSPI1_DR0_SC_MASK (0x3 << 10) | ||
568 | #define OMAP4_UART1_DR0_SC_SHIFT 8 | ||
569 | #define OMAP4_UART1_DR0_SC_MASK (0x3 << 8) | ||
570 | #define OMAP4_UART3_DR0_SC_SHIFT 6 | ||
571 | #define OMAP4_UART3_DR0_SC_MASK (0x3 << 6) | ||
572 | #define OMAP4_UART3_DR1_SC_SHIFT 4 | ||
573 | #define OMAP4_UART3_DR1_SC_MASK (0x3 << 4) | ||
574 | #define OMAP4_UNIPRO_DR0_SC_SHIFT 2 | ||
575 | #define OMAP4_UNIPRO_DR0_SC_MASK (0x3 << 2) | ||
576 | #define OMAP4_UNIPRO_DR1_SC_SHIFT 0 | ||
577 | #define OMAP4_UNIPRO_DR1_SC_MASK (0x3 << 0) | ||
578 | |||
579 | /* CONTROL_SMART1IO_PADCONF_1 */ | ||
580 | #define OMAP4_ABE_DR0_LB_SHIFT 30 | ||
581 | #define OMAP4_ABE_DR0_LB_MASK (0x3 << 30) | ||
582 | #define OMAP4_CAM_DR0_LB_SHIFT 28 | ||
583 | #define OMAP4_CAM_DR0_LB_MASK (0x3 << 28) | ||
584 | #define OMAP4_FREF_DR2_LB_SHIFT 26 | ||
585 | #define OMAP4_FREF_DR2_LB_MASK (0x3 << 26) | ||
586 | #define OMAP4_FREF_DR3_LB_SHIFT 24 | ||
587 | #define OMAP4_FREF_DR3_LB_MASK (0x3 << 24) | ||
588 | #define OMAP4_GPIO_DR8_LB_SHIFT 22 | ||
589 | #define OMAP4_GPIO_DR8_LB_MASK (0x3 << 22) | ||
590 | #define OMAP4_GPIO_DR9_LB_SHIFT 20 | ||
591 | #define OMAP4_GPIO_DR9_LB_MASK (0x3 << 20) | ||
592 | #define OMAP4_GPMC_DR2_LB_SHIFT 18 | ||
593 | #define OMAP4_GPMC_DR2_LB_MASK (0x3 << 18) | ||
594 | #define OMAP4_GPMC_DR3_LB_SHIFT 16 | ||
595 | #define OMAP4_GPMC_DR3_LB_MASK (0x3 << 16) | ||
596 | #define OMAP4_GPMC_DR6_LB_SHIFT 14 | ||
597 | #define OMAP4_GPMC_DR6_LB_MASK (0x3 << 14) | ||
598 | #define OMAP4_HDMI_DR0_LB_SHIFT 12 | ||
599 | #define OMAP4_HDMI_DR0_LB_MASK (0x3 << 12) | ||
600 | #define OMAP4_MCSPI1_DR0_LB_SHIFT 10 | ||
601 | #define OMAP4_MCSPI1_DR0_LB_MASK (0x3 << 10) | ||
602 | #define OMAP4_UART1_DR0_LB_SHIFT 8 | ||
603 | #define OMAP4_UART1_DR0_LB_MASK (0x3 << 8) | ||
604 | #define OMAP4_UART3_DR0_LB_SHIFT 6 | ||
605 | #define OMAP4_UART3_DR0_LB_MASK (0x3 << 6) | ||
606 | #define OMAP4_UART3_DR1_LB_SHIFT 4 | ||
607 | #define OMAP4_UART3_DR1_LB_MASK (0x3 << 4) | ||
608 | #define OMAP4_UNIPRO_DR0_LB_SHIFT 2 | ||
609 | #define OMAP4_UNIPRO_DR0_LB_MASK (0x3 << 2) | ||
610 | #define OMAP4_UNIPRO_DR1_LB_SHIFT 0 | ||
611 | #define OMAP4_UNIPRO_DR1_LB_MASK (0x3 << 0) | ||
612 | |||
613 | /* CONTROL_SMART2IO_PADCONF_0 */ | ||
614 | #define OMAP4_C2C_DR0_LB_SHIFT 31 | ||
615 | #define OMAP4_C2C_DR0_LB_MASK (1 << 31) | ||
616 | #define OMAP4_DPM_DR1_LB_SHIFT 30 | ||
617 | #define OMAP4_DPM_DR1_LB_MASK (1 << 30) | ||
618 | #define OMAP4_DPM_DR2_LB_SHIFT 29 | ||
619 | #define OMAP4_DPM_DR2_LB_MASK (1 << 29) | ||
620 | #define OMAP4_DPM_DR3_LB_SHIFT 28 | ||
621 | #define OMAP4_DPM_DR3_LB_MASK (1 << 28) | ||
622 | #define OMAP4_GPIO_DR0_LB_SHIFT 27 | ||
623 | #define OMAP4_GPIO_DR0_LB_MASK (1 << 27) | ||
624 | #define OMAP4_GPIO_DR1_LB_SHIFT 26 | ||
625 | #define OMAP4_GPIO_DR1_LB_MASK (1 << 26) | ||
626 | #define OMAP4_GPIO_DR10_LB_SHIFT 25 | ||
627 | #define OMAP4_GPIO_DR10_LB_MASK (1 << 25) | ||
628 | #define OMAP4_GPIO_DR2_LB_SHIFT 24 | ||
629 | #define OMAP4_GPIO_DR2_LB_MASK (1 << 24) | ||
630 | #define OMAP4_GPMC_DR0_LB_SHIFT 23 | ||
631 | #define OMAP4_GPMC_DR0_LB_MASK (1 << 23) | ||
632 | #define OMAP4_GPMC_DR1_LB_SHIFT 22 | ||
633 | #define OMAP4_GPMC_DR1_LB_MASK (1 << 22) | ||
634 | #define OMAP4_GPMC_DR4_LB_SHIFT 21 | ||
635 | #define OMAP4_GPMC_DR4_LB_MASK (1 << 21) | ||
636 | #define OMAP4_GPMC_DR5_LB_SHIFT 20 | ||
637 | #define OMAP4_GPMC_DR5_LB_MASK (1 << 20) | ||
638 | #define OMAP4_GPMC_DR7_LB_SHIFT 19 | ||
639 | #define OMAP4_GPMC_DR7_LB_MASK (1 << 19) | ||
640 | #define OMAP4_HSI2_DR0_LB_SHIFT 18 | ||
641 | #define OMAP4_HSI2_DR0_LB_MASK (1 << 18) | ||
642 | #define OMAP4_HSI2_DR1_LB_SHIFT 17 | ||
643 | #define OMAP4_HSI2_DR1_LB_MASK (1 << 17) | ||
644 | #define OMAP4_HSI2_DR2_LB_SHIFT 16 | ||
645 | #define OMAP4_HSI2_DR2_LB_MASK (1 << 16) | ||
646 | #define OMAP4_KPD_DR0_LB_SHIFT 15 | ||
647 | #define OMAP4_KPD_DR0_LB_MASK (1 << 15) | ||
648 | #define OMAP4_KPD_DR1_LB_SHIFT 14 | ||
649 | #define OMAP4_KPD_DR1_LB_MASK (1 << 14) | ||
650 | #define OMAP4_PDM_DR0_LB_SHIFT 13 | ||
651 | #define OMAP4_PDM_DR0_LB_MASK (1 << 13) | ||
652 | #define OMAP4_SDMMC2_DR0_LB_SHIFT 12 | ||
653 | #define OMAP4_SDMMC2_DR0_LB_MASK (1 << 12) | ||
654 | #define OMAP4_SDMMC3_DR0_LB_SHIFT 11 | ||
655 | #define OMAP4_SDMMC3_DR0_LB_MASK (1 << 11) | ||
656 | #define OMAP4_SDMMC4_DR0_LB_SHIFT 10 | ||
657 | #define OMAP4_SDMMC4_DR0_LB_MASK (1 << 10) | ||
658 | #define OMAP4_SDMMC4_DR1_LB_SHIFT 9 | ||
659 | #define OMAP4_SDMMC4_DR1_LB_MASK (1 << 9) | ||
660 | #define OMAP4_SPI3_DR0_LB_SHIFT 8 | ||
661 | #define OMAP4_SPI3_DR0_LB_MASK (1 << 8) | ||
662 | #define OMAP4_SPI3_DR1_LB_SHIFT 7 | ||
663 | #define OMAP4_SPI3_DR1_LB_MASK (1 << 7) | ||
664 | #define OMAP4_UART3_DR2_LB_SHIFT 6 | ||
665 | #define OMAP4_UART3_DR2_LB_MASK (1 << 6) | ||
666 | #define OMAP4_UART3_DR3_LB_SHIFT 5 | ||
667 | #define OMAP4_UART3_DR3_LB_MASK (1 << 5) | ||
668 | #define OMAP4_UART3_DR4_LB_SHIFT 4 | ||
669 | #define OMAP4_UART3_DR4_LB_MASK (1 << 4) | ||
670 | #define OMAP4_UART3_DR5_LB_SHIFT 3 | ||
671 | #define OMAP4_UART3_DR5_LB_MASK (1 << 3) | ||
672 | #define OMAP4_USBA0_DR1_LB_SHIFT 2 | ||
673 | #define OMAP4_USBA0_DR1_LB_MASK (1 << 2) | ||
674 | #define OMAP4_USBA_DR2_LB_SHIFT 1 | ||
675 | #define OMAP4_USBA_DR2_LB_MASK (1 << 1) | ||
676 | |||
677 | /* CONTROL_SMART2IO_PADCONF_1 */ | ||
678 | #define OMAP4_USBB1_DR0_LB_SHIFT 31 | ||
679 | #define OMAP4_USBB1_DR0_LB_MASK (1 << 31) | ||
680 | #define OMAP4_USBB2_DR0_LB_SHIFT 30 | ||
681 | #define OMAP4_USBB2_DR0_LB_MASK (1 << 30) | ||
682 | #define OMAP4_USBA0_DR0_LB_SHIFT 29 | ||
683 | #define OMAP4_USBA0_DR0_LB_MASK (1 << 29) | ||
684 | |||
685 | /* CONTROL_SMART3IO_PADCONF_0 */ | ||
686 | #define OMAP4_DMIC_DR0_MB_SHIFT 30 | ||
687 | #define OMAP4_DMIC_DR0_MB_MASK (0x3 << 30) | ||
688 | #define OMAP4_GPIO_DR3_MB_SHIFT 28 | ||
689 | #define OMAP4_GPIO_DR3_MB_MASK (0x3 << 28) | ||
690 | #define OMAP4_GPIO_DR4_MB_SHIFT 26 | ||
691 | #define OMAP4_GPIO_DR4_MB_MASK (0x3 << 26) | ||
692 | #define OMAP4_GPIO_DR5_MB_SHIFT 24 | ||
693 | #define OMAP4_GPIO_DR5_MB_MASK (0x3 << 24) | ||
694 | #define OMAP4_GPIO_DR6_MB_SHIFT 22 | ||
695 | #define OMAP4_GPIO_DR6_MB_MASK (0x3 << 22) | ||
696 | #define OMAP4_HSI_DR1_MB_SHIFT 20 | ||
697 | #define OMAP4_HSI_DR1_MB_MASK (0x3 << 20) | ||
698 | #define OMAP4_HSI_DR2_MB_SHIFT 18 | ||
699 | #define OMAP4_HSI_DR2_MB_MASK (0x3 << 18) | ||
700 | #define OMAP4_HSI_DR3_MB_SHIFT 16 | ||
701 | #define OMAP4_HSI_DR3_MB_MASK (0x3 << 16) | ||
702 | #define OMAP4_MCBSP2_DR0_MB_SHIFT 14 | ||
703 | #define OMAP4_MCBSP2_DR0_MB_MASK (0x3 << 14) | ||
704 | #define OMAP4_MCSPI4_DR0_MB_SHIFT 12 | ||
705 | #define OMAP4_MCSPI4_DR0_MB_MASK (0x3 << 12) | ||
706 | #define OMAP4_MCSPI4_DR1_MB_SHIFT 10 | ||
707 | #define OMAP4_MCSPI4_DR1_MB_MASK (0x3 << 10) | ||
708 | #define OMAP4_SDMMC3_DR0_MB_SHIFT 8 | ||
709 | #define OMAP4_SDMMC3_DR0_MB_MASK (0x3 << 8) | ||
710 | #define OMAP4_SPI2_DR0_MB_SHIFT 0 | ||
711 | #define OMAP4_SPI2_DR0_MB_MASK (0x3 << 0) | ||
712 | |||
713 | /* CONTROL_SMART3IO_PADCONF_1 */ | ||
714 | #define OMAP4_SPI2_DR1_MB_SHIFT 30 | ||
715 | #define OMAP4_SPI2_DR1_MB_MASK (0x3 << 30) | ||
716 | #define OMAP4_SPI2_DR2_MB_SHIFT 28 | ||
717 | #define OMAP4_SPI2_DR2_MB_MASK (0x3 << 28) | ||
718 | #define OMAP4_UART2_DR0_MB_SHIFT 26 | ||
719 | #define OMAP4_UART2_DR0_MB_MASK (0x3 << 26) | ||
720 | #define OMAP4_UART2_DR1_MB_SHIFT 24 | ||
721 | #define OMAP4_UART2_DR1_MB_MASK (0x3 << 24) | ||
722 | #define OMAP4_UART4_DR0_MB_SHIFT 22 | ||
723 | #define OMAP4_UART4_DR0_MB_MASK (0x3 << 22) | ||
724 | #define OMAP4_HSI_DR0_MB_SHIFT 20 | ||
725 | #define OMAP4_HSI_DR0_MB_MASK (0x3 << 20) | ||
726 | |||
727 | /* CONTROL_SMART3IO_PADCONF_2 */ | ||
728 | #define OMAP4_DMIC_DR0_LB_SHIFT 31 | ||
729 | #define OMAP4_DMIC_DR0_LB_MASK (1 << 31) | ||
730 | #define OMAP4_GPIO_DR3_LB_SHIFT 30 | ||
731 | #define OMAP4_GPIO_DR3_LB_MASK (1 << 30) | ||
732 | #define OMAP4_GPIO_DR4_LB_SHIFT 29 | ||
733 | #define OMAP4_GPIO_DR4_LB_MASK (1 << 29) | ||
734 | #define OMAP4_GPIO_DR5_LB_SHIFT 28 | ||
735 | #define OMAP4_GPIO_DR5_LB_MASK (1 << 28) | ||
736 | #define OMAP4_GPIO_DR6_LB_SHIFT 27 | ||
737 | #define OMAP4_GPIO_DR6_LB_MASK (1 << 27) | ||
738 | #define OMAP4_HSI_DR1_LB_SHIFT 26 | ||
739 | #define OMAP4_HSI_DR1_LB_MASK (1 << 26) | ||
740 | #define OMAP4_HSI_DR2_LB_SHIFT 25 | ||
741 | #define OMAP4_HSI_DR2_LB_MASK (1 << 25) | ||
742 | #define OMAP4_HSI_DR3_LB_SHIFT 24 | ||
743 | #define OMAP4_HSI_DR3_LB_MASK (1 << 24) | ||
744 | #define OMAP4_MCBSP2_DR0_LB_SHIFT 23 | ||
745 | #define OMAP4_MCBSP2_DR0_LB_MASK (1 << 23) | ||
746 | #define OMAP4_MCSPI4_DR0_LB_SHIFT 22 | ||
747 | #define OMAP4_MCSPI4_DR0_LB_MASK (1 << 22) | ||
748 | #define OMAP4_MCSPI4_DR1_LB_SHIFT 21 | ||
749 | #define OMAP4_MCSPI4_DR1_LB_MASK (1 << 21) | ||
750 | #define OMAP4_SLIMBUS2_DR0_LB_SHIFT 18 | ||
751 | #define OMAP4_SLIMBUS2_DR0_LB_MASK (1 << 18) | ||
752 | #define OMAP4_SPI2_DR0_LB_SHIFT 16 | ||
753 | #define OMAP4_SPI2_DR0_LB_MASK (1 << 16) | ||
754 | #define OMAP4_SPI2_DR1_LB_SHIFT 15 | ||
755 | #define OMAP4_SPI2_DR1_LB_MASK (1 << 15) | ||
756 | #define OMAP4_SPI2_DR2_LB_SHIFT 14 | ||
757 | #define OMAP4_SPI2_DR2_LB_MASK (1 << 14) | ||
758 | #define OMAP4_UART2_DR0_LB_SHIFT 13 | ||
759 | #define OMAP4_UART2_DR0_LB_MASK (1 << 13) | ||
760 | #define OMAP4_UART2_DR1_LB_SHIFT 12 | ||
761 | #define OMAP4_UART2_DR1_LB_MASK (1 << 12) | ||
762 | #define OMAP4_UART4_DR0_LB_SHIFT 11 | ||
763 | #define OMAP4_UART4_DR0_LB_MASK (1 << 11) | ||
764 | #define OMAP4_HSI_DR0_LB_SHIFT 10 | ||
765 | #define OMAP4_HSI_DR0_LB_MASK (1 << 10) | ||
766 | |||
767 | /* CONTROL_USBB_HSIC */ | ||
768 | #define OMAP4_USBB2_DR1_SR_SHIFT 30 | ||
769 | #define OMAP4_USBB2_DR1_SR_MASK (0x3 << 30) | ||
770 | #define OMAP4_USBB2_DR1_I_SHIFT 27 | ||
771 | #define OMAP4_USBB2_DR1_I_MASK (0x7 << 27) | ||
772 | #define OMAP4_USBB1_DR1_SR_SHIFT 25 | ||
773 | #define OMAP4_USBB1_DR1_SR_MASK (0x3 << 25) | ||
774 | #define OMAP4_USBB1_DR1_I_SHIFT 22 | ||
775 | #define OMAP4_USBB1_DR1_I_MASK (0x7 << 22) | ||
776 | #define OMAP4_USBB1_HSIC_DATA_WD_SHIFT 20 | ||
777 | #define OMAP4_USBB1_HSIC_DATA_WD_MASK (0x3 << 20) | ||
778 | #define OMAP4_USBB1_HSIC_STROBE_WD_SHIFT 18 | ||
779 | #define OMAP4_USBB1_HSIC_STROBE_WD_MASK (0x3 << 18) | ||
780 | #define OMAP4_USBB2_HSIC_DATA_WD_SHIFT 16 | ||
781 | #define OMAP4_USBB2_HSIC_DATA_WD_MASK (0x3 << 16) | ||
782 | #define OMAP4_USBB2_HSIC_STROBE_WD_SHIFT 14 | ||
783 | #define OMAP4_USBB2_HSIC_STROBE_WD_MASK (0x3 << 14) | ||
784 | #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 13 | ||
785 | #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 13) | ||
786 | #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_SHIFT 11 | ||
787 | #define OMAP4_USBB1_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 11) | ||
788 | #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 10 | ||
789 | #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 10) | ||
790 | #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_SHIFT 8 | ||
791 | #define OMAP4_USBB1_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 8) | ||
792 | #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_SHIFT 7 | ||
793 | #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_ENABLE_MASK (1 << 7) | ||
794 | #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_SHIFT 5 | ||
795 | #define OMAP4_USBB2_HSIC_DATA_OFFMODE_WD_MASK (0x3 << 5) | ||
796 | #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_SHIFT 4 | ||
797 | #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_ENABLE_MASK (1 << 4) | ||
798 | #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_SHIFT 2 | ||
799 | #define OMAP4_USBB2_HSIC_STROBE_OFFMODE_WD_MASK (0x3 << 2) | ||
800 | |||
801 | /* CONTROL_SLIMBUS */ | ||
802 | #define OMAP4_SLIMBUS1_DR0_MB_SHIFT 30 | ||
803 | #define OMAP4_SLIMBUS1_DR0_MB_MASK (0x3 << 30) | ||
804 | #define OMAP4_SLIMBUS1_DR1_MB_SHIFT 28 | ||
805 | #define OMAP4_SLIMBUS1_DR1_MB_MASK (0x3 << 28) | ||
806 | #define OMAP4_SLIMBUS2_DR0_MB_SHIFT 26 | ||
807 | #define OMAP4_SLIMBUS2_DR0_MB_MASK (0x3 << 26) | ||
808 | #define OMAP4_SLIMBUS2_DR1_MB_SHIFT 24 | ||
809 | #define OMAP4_SLIMBUS2_DR1_MB_MASK (0x3 << 24) | ||
810 | #define OMAP4_SLIMBUS2_DR2_MB_SHIFT 22 | ||
811 | #define OMAP4_SLIMBUS2_DR2_MB_MASK (0x3 << 22) | ||
812 | #define OMAP4_SLIMBUS2_DR3_MB_SHIFT 20 | ||
813 | #define OMAP4_SLIMBUS2_DR3_MB_MASK (0x3 << 20) | ||
814 | #define OMAP4_SLIMBUS1_DR0_LB_SHIFT 19 | ||
815 | #define OMAP4_SLIMBUS1_DR0_LB_MASK (1 << 19) | ||
816 | #define OMAP4_SLIMBUS2_DR1_LB_SHIFT 18 | ||
817 | #define OMAP4_SLIMBUS2_DR1_LB_MASK (1 << 18) | ||
818 | |||
819 | /* CONTROL_PBIASLITE */ | ||
820 | #define OMAP4_USIM_PBIASLITE_HIZ_MODE_SHIFT 31 | ||
821 | #define OMAP4_USIM_PBIASLITE_HIZ_MODE_MASK (1 << 31) | ||
822 | #define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_SHIFT 30 | ||
823 | #define OMAP4_USIM_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 30) | ||
824 | #define OMAP4_USIM_PBIASLITE_VMODE_ERROR_SHIFT 29 | ||
825 | #define OMAP4_USIM_PBIASLITE_VMODE_ERROR_MASK (1 << 29) | ||
826 | #define OMAP4_USIM_PBIASLITE_PWRDNZ_SHIFT 28 | ||
827 | #define OMAP4_USIM_PBIASLITE_PWRDNZ_MASK (1 << 28) | ||
828 | #define OMAP4_USIM_PBIASLITE_VMODE_SHIFT 27 | ||
829 | #define OMAP4_USIM_PBIASLITE_VMODE_MASK (1 << 27) | ||
830 | #define OMAP4_MMC1_PWRDNZ_SHIFT 26 | ||
831 | #define OMAP4_MMC1_PWRDNZ_MASK (1 << 26) | ||
832 | #define OMAP4_MMC1_PBIASLITE_HIZ_MODE_SHIFT 25 | ||
833 | #define OMAP4_MMC1_PBIASLITE_HIZ_MODE_MASK (1 << 25) | ||
834 | #define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_SHIFT 24 | ||
835 | #define OMAP4_MMC1_PBIASLITE_SUPPLY_HI_OUT_MASK (1 << 24) | ||
836 | #define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_SHIFT 23 | ||
837 | #define OMAP4_MMC1_PBIASLITE_VMODE_ERROR_MASK (1 << 23) | ||
838 | #define OMAP4_MMC1_PBIASLITE_PWRDNZ_SHIFT 22 | ||
839 | #define OMAP4_MMC1_PBIASLITE_PWRDNZ_MASK (1 << 22) | ||
840 | #define OMAP4_MMC1_PBIASLITE_VMODE_SHIFT 21 | ||
841 | #define OMAP4_MMC1_PBIASLITE_VMODE_MASK (1 << 21) | ||
842 | #define OMAP4_USBC1_ICUSB_PWRDNZ_SHIFT 20 | ||
843 | #define OMAP4_USBC1_ICUSB_PWRDNZ_MASK (1 << 20) | ||
844 | |||
845 | /* CONTROL_I2C_0 */ | ||
846 | #define OMAP4_I2C4_SDA_GLFENB_SHIFT 31 | ||
847 | #define OMAP4_I2C4_SDA_GLFENB_MASK (1 << 31) | ||
848 | #define OMAP4_I2C4_SDA_LOAD_BITS_SHIFT 29 | ||
849 | #define OMAP4_I2C4_SDA_LOAD_BITS_MASK (0x3 << 29) | ||
850 | #define OMAP4_I2C4_SDA_PULLUPRESX_SHIFT 28 | ||
851 | #define OMAP4_I2C4_SDA_PULLUPRESX_MASK (1 << 28) | ||
852 | #define OMAP4_I2C3_SDA_GLFENB_SHIFT 27 | ||
853 | #define OMAP4_I2C3_SDA_GLFENB_MASK (1 << 27) | ||
854 | #define OMAP4_I2C3_SDA_LOAD_BITS_SHIFT 25 | ||
855 | #define OMAP4_I2C3_SDA_LOAD_BITS_MASK (0x3 << 25) | ||
856 | #define OMAP4_I2C3_SDA_PULLUPRESX_SHIFT 24 | ||
857 | #define OMAP4_I2C3_SDA_PULLUPRESX_MASK (1 << 24) | ||
858 | #define OMAP4_I2C2_SDA_GLFENB_SHIFT 23 | ||
859 | #define OMAP4_I2C2_SDA_GLFENB_MASK (1 << 23) | ||
860 | #define OMAP4_I2C2_SDA_LOAD_BITS_SHIFT 21 | ||
861 | #define OMAP4_I2C2_SDA_LOAD_BITS_MASK (0x3 << 21) | ||
862 | #define OMAP4_I2C2_SDA_PULLUPRESX_SHIFT 20 | ||
863 | #define OMAP4_I2C2_SDA_PULLUPRESX_MASK (1 << 20) | ||
864 | #define OMAP4_I2C1_SDA_GLFENB_SHIFT 19 | ||
865 | #define OMAP4_I2C1_SDA_GLFENB_MASK (1 << 19) | ||
866 | #define OMAP4_I2C1_SDA_LOAD_BITS_SHIFT 17 | ||
867 | #define OMAP4_I2C1_SDA_LOAD_BITS_MASK (0x3 << 17) | ||
868 | #define OMAP4_I2C1_SDA_PULLUPRESX_SHIFT 16 | ||
869 | #define OMAP4_I2C1_SDA_PULLUPRESX_MASK (1 << 16) | ||
870 | #define OMAP4_I2C4_SCL_GLFENB_SHIFT 15 | ||
871 | #define OMAP4_I2C4_SCL_GLFENB_MASK (1 << 15) | ||
872 | #define OMAP4_I2C4_SCL_LOAD_BITS_SHIFT 13 | ||
873 | #define OMAP4_I2C4_SCL_LOAD_BITS_MASK (0x3 << 13) | ||
874 | #define OMAP4_I2C4_SCL_PULLUPRESX_SHIFT 12 | ||
875 | #define OMAP4_I2C4_SCL_PULLUPRESX_MASK (1 << 12) | ||
876 | #define OMAP4_I2C3_SCL_GLFENB_SHIFT 11 | ||
877 | #define OMAP4_I2C3_SCL_GLFENB_MASK (1 << 11) | ||
878 | #define OMAP4_I2C3_SCL_LOAD_BITS_SHIFT 9 | ||
879 | #define OMAP4_I2C3_SCL_LOAD_BITS_MASK (0x3 << 9) | ||
880 | #define OMAP4_I2C3_SCL_PULLUPRESX_SHIFT 8 | ||
881 | #define OMAP4_I2C3_SCL_PULLUPRESX_MASK (1 << 8) | ||
882 | #define OMAP4_I2C2_SCL_GLFENB_SHIFT 7 | ||
883 | #define OMAP4_I2C2_SCL_GLFENB_MASK (1 << 7) | ||
884 | #define OMAP4_I2C2_SCL_LOAD_BITS_SHIFT 5 | ||
885 | #define OMAP4_I2C2_SCL_LOAD_BITS_MASK (0x3 << 5) | ||
886 | #define OMAP4_I2C2_SCL_PULLUPRESX_SHIFT 4 | ||
887 | #define OMAP4_I2C2_SCL_PULLUPRESX_MASK (1 << 4) | ||
888 | #define OMAP4_I2C1_SCL_GLFENB_SHIFT 3 | ||
889 | #define OMAP4_I2C1_SCL_GLFENB_MASK (1 << 3) | ||
890 | #define OMAP4_I2C1_SCL_LOAD_BITS_SHIFT 1 | ||
891 | #define OMAP4_I2C1_SCL_LOAD_BITS_MASK (0x3 << 1) | ||
892 | #define OMAP4_I2C1_SCL_PULLUPRESX_SHIFT 0 | ||
893 | #define OMAP4_I2C1_SCL_PULLUPRESX_MASK (1 << 0) | ||
894 | |||
895 | /* CONTROL_CAMERA_RX */ | ||
896 | #define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_SHIFT 31 | ||
897 | #define OMAP4_CAMERARX_UNIPRO_CTRLCLKEN_MASK (1 << 31) | ||
898 | #define OMAP4_CAMERARX_CSI22_LANEENABLE_SHIFT 29 | ||
899 | #define OMAP4_CAMERARX_CSI22_LANEENABLE_MASK (0x3 << 29) | ||
900 | #define OMAP4_CAMERARX_CSI21_LANEENABLE_SHIFT 24 | ||
901 | #define OMAP4_CAMERARX_CSI21_LANEENABLE_MASK (0x1f << 24) | ||
902 | #define OMAP4_CAMERARX_UNIPRO_CAMMODE_SHIFT 22 | ||
903 | #define OMAP4_CAMERARX_UNIPRO_CAMMODE_MASK (0x3 << 22) | ||
904 | #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_SHIFT 21 | ||
905 | #define OMAP4_CAMERARX_CSI22_CTRLCLKEN_MASK (1 << 21) | ||
906 | #define OMAP4_CAMERARX_CSI22_CAMMODE_SHIFT 19 | ||
907 | #define OMAP4_CAMERARX_CSI22_CAMMODE_MASK (0x3 << 19) | ||
908 | #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_SHIFT 18 | ||
909 | #define OMAP4_CAMERARX_CSI21_CTRLCLKEN_MASK (1 << 18) | ||
910 | #define OMAP4_CAMERARX_CSI21_CAMMODE_SHIFT 16 | ||
911 | #define OMAP4_CAMERARX_CSI21_CAMMODE_MASK (0x3 << 16) | ||
912 | |||
913 | /* CONTROL_AVDAC */ | ||
914 | #define OMAP4_AVDAC_ACEN_SHIFT 31 | ||
915 | #define OMAP4_AVDAC_ACEN_MASK (1 << 31) | ||
916 | #define OMAP4_AVDAC_TVOUTBYPASS_SHIFT 30 | ||
917 | #define OMAP4_AVDAC_TVOUTBYPASS_MASK (1 << 30) | ||
918 | #define OMAP4_AVDAC_INPUTINV_SHIFT 29 | ||
919 | #define OMAP4_AVDAC_INPUTINV_MASK (1 << 29) | ||
920 | #define OMAP4_AVDAC_CTL_SHIFT 13 | ||
921 | #define OMAP4_AVDAC_CTL_MASK (0xffff << 13) | ||
922 | #define OMAP4_AVDAC_CTL_WR_ACK_SHIFT 12 | ||
923 | #define OMAP4_AVDAC_CTL_WR_ACK_MASK (1 << 12) | ||
924 | |||
925 | /* CONTROL_HDMI_TX_PHY */ | ||
926 | #define OMAP4_HDMITXPHY_PADORDER_SHIFT 31 | ||
927 | #define OMAP4_HDMITXPHY_PADORDER_MASK (1 << 31) | ||
928 | #define OMAP4_HDMITXPHY_TXVALID_SHIFT 30 | ||
929 | #define OMAP4_HDMITXPHY_TXVALID_MASK (1 << 30) | ||
930 | #define OMAP4_HDMITXPHY_ENBYPASSCLK_SHIFT 29 | ||
931 | #define OMAP4_HDMITXPHY_ENBYPASSCLK_MASK (1 << 29) | ||
932 | #define OMAP4_HDMITXPHY_PD_PULLUPDET_SHIFT 28 | ||
933 | #define OMAP4_HDMITXPHY_PD_PULLUPDET_MASK (1 << 28) | ||
934 | |||
935 | /* CONTROL_MMC2 */ | ||
936 | #define OMAP4_MMC2_FEEDBACK_CLK_SEL_SHIFT 31 | ||
937 | #define OMAP4_MMC2_FEEDBACK_CLK_SEL_MASK (1 << 31) | ||
938 | |||
939 | /* CONTROL_DSIPHY */ | ||
940 | #define OMAP4_DSI2_LANEENABLE_SHIFT 29 | ||
941 | #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) | ||
942 | #define OMAP4_DSI1_LANEENABLE_SHIFT 24 | ||
943 | #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) | ||
944 | #define OMAP4_DSI1_PIPD_SHIFT 19 | ||
945 | #define OMAP4_DSI1_PIPD_MASK (0x1f << 19) | ||
946 | #define OMAP4_DSI2_PIPD_SHIFT 14 | ||
947 | #define OMAP4_DSI2_PIPD_MASK (0x1f << 14) | ||
948 | |||
949 | /* CONTROL_MCBSPLP */ | ||
950 | #define OMAP4_ALBCTRLRX_FSX_SHIFT 31 | ||
951 | #define OMAP4_ALBCTRLRX_FSX_MASK (1 << 31) | ||
952 | #define OMAP4_ALBCTRLRX_CLKX_SHIFT 30 | ||
953 | #define OMAP4_ALBCTRLRX_CLKX_MASK (1 << 30) | ||
954 | #define OMAP4_ABE_MCBSP1_DR_EN_SHIFT 29 | ||
955 | #define OMAP4_ABE_MCBSP1_DR_EN_MASK (1 << 29) | ||
956 | |||
957 | /* CONTROL_USB2PHYCORE */ | ||
958 | #define OMAP4_USB2PHY_AUTORESUME_EN_SHIFT 31 | ||
959 | #define OMAP4_USB2PHY_AUTORESUME_EN_MASK (1 << 31) | ||
960 | #define OMAP4_USB2PHY_DISCHGDET_SHIFT 30 | ||
961 | #define OMAP4_USB2PHY_DISCHGDET_MASK (1 << 30) | ||
962 | #define OMAP4_USB2PHY_GPIOMODE_SHIFT 29 | ||
963 | #define OMAP4_USB2PHY_GPIOMODE_MASK (1 << 29) | ||
964 | #define OMAP4_USB2PHY_CHG_DET_EXT_CTL_SHIFT 28 | ||
965 | #define OMAP4_USB2PHY_CHG_DET_EXT_CTL_MASK (1 << 28) | ||
966 | #define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_SHIFT 27 | ||
967 | #define OMAP4_USB2PHY_RDM_PD_CHGDET_EN_MASK (1 << 27) | ||
968 | #define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_SHIFT 26 | ||
969 | #define OMAP4_USB2PHY_RDP_PU_CHGDET_EN_MASK (1 << 26) | ||
970 | #define OMAP4_USB2PHY_CHG_VSRC_EN_SHIFT 25 | ||
971 | #define OMAP4_USB2PHY_CHG_VSRC_EN_MASK (1 << 25) | ||
972 | #define OMAP4_USB2PHY_CHG_ISINK_EN_SHIFT 24 | ||
973 | #define OMAP4_USB2PHY_CHG_ISINK_EN_MASK (1 << 24) | ||
974 | #define OMAP4_USB2PHY_CHG_DET_STATUS_SHIFT 21 | ||
975 | #define OMAP4_USB2PHY_CHG_DET_STATUS_MASK (0x7 << 21) | ||
976 | #define OMAP4_USB2PHY_CHG_DET_DM_COMP_SHIFT 20 | ||
977 | #define OMAP4_USB2PHY_CHG_DET_DM_COMP_MASK (1 << 20) | ||
978 | #define OMAP4_USB2PHY_CHG_DET_DP_COMP_SHIFT 19 | ||
979 | #define OMAP4_USB2PHY_CHG_DET_DP_COMP_MASK (1 << 19) | ||
980 | #define OMAP4_USB2PHY_DATADET_SHIFT 18 | ||
981 | #define OMAP4_USB2PHY_DATADET_MASK (1 << 18) | ||
982 | #define OMAP4_USB2PHY_SINKONDP_SHIFT 17 | ||
983 | #define OMAP4_USB2PHY_SINKONDP_MASK (1 << 17) | ||
984 | #define OMAP4_USB2PHY_SRCONDM_SHIFT 16 | ||
985 | #define OMAP4_USB2PHY_SRCONDM_MASK (1 << 16) | ||
986 | #define OMAP4_USB2PHY_RESTARTCHGDET_SHIFT 15 | ||
987 | #define OMAP4_USB2PHY_RESTARTCHGDET_MASK (1 << 15) | ||
988 | #define OMAP4_USB2PHY_CHGDETDONE_SHIFT 14 | ||
989 | #define OMAP4_USB2PHY_CHGDETDONE_MASK (1 << 14) | ||
990 | #define OMAP4_USB2PHY_CHGDETECTED_SHIFT 13 | ||
991 | #define OMAP4_USB2PHY_CHGDETECTED_MASK (1 << 13) | ||
992 | #define OMAP4_USB2PHY_MCPCPUEN_SHIFT 12 | ||
993 | #define OMAP4_USB2PHY_MCPCPUEN_MASK (1 << 12) | ||
994 | #define OMAP4_USB2PHY_MCPCMODEEN_SHIFT 11 | ||
995 | #define OMAP4_USB2PHY_MCPCMODEEN_MASK (1 << 11) | ||
996 | #define OMAP4_USB2PHY_RESETDONEMCLK_SHIFT 10 | ||
997 | #define OMAP4_USB2PHY_RESETDONEMCLK_MASK (1 << 10) | ||
998 | #define OMAP4_USB2PHY_UTMIRESETDONE_SHIFT 9 | ||
999 | #define OMAP4_USB2PHY_UTMIRESETDONE_MASK (1 << 9) | ||
1000 | #define OMAP4_USB2PHY_TXBITSTUFFENABLE_SHIFT 8 | ||
1001 | #define OMAP4_USB2PHY_TXBITSTUFFENABLE_MASK (1 << 8) | ||
1002 | #define OMAP4_USB2PHY_DATAPOLARITYN_SHIFT 7 | ||
1003 | #define OMAP4_USB2PHY_DATAPOLARITYN_MASK (1 << 7) | ||
1004 | #define OMAP4_USBDPLL_FREQLOCK_SHIFT 6 | ||
1005 | #define OMAP4_USBDPLL_FREQLOCK_MASK (1 << 6) | ||
1006 | #define OMAP4_USB2PHY_RESETDONETCLK_SHIFT 5 | ||
1007 | #define OMAP4_USB2PHY_RESETDONETCLK_MASK (1 << 5) | ||
1008 | |||
1009 | /* CONTROL_I2C_1 */ | ||
1010 | #define OMAP4_HDMI_DDC_SDA_GLFENB_SHIFT 31 | ||
1011 | #define OMAP4_HDMI_DDC_SDA_GLFENB_MASK (1 << 31) | ||
1012 | #define OMAP4_HDMI_DDC_SDA_LOAD_BITS_SHIFT 29 | ||
1013 | #define OMAP4_HDMI_DDC_SDA_LOAD_BITS_MASK (0x3 << 29) | ||
1014 | #define OMAP4_HDMI_DDC_SDA_PULLUPRESX_SHIFT 28 | ||
1015 | #define OMAP4_HDMI_DDC_SDA_PULLUPRESX_MASK (1 << 28) | ||
1016 | #define OMAP4_HDMI_DDC_SCL_GLFENB_SHIFT 27 | ||
1017 | #define OMAP4_HDMI_DDC_SCL_GLFENB_MASK (1 << 27) | ||
1018 | #define OMAP4_HDMI_DDC_SCL_LOAD_BITS_SHIFT 25 | ||
1019 | #define OMAP4_HDMI_DDC_SCL_LOAD_BITS_MASK (0x3 << 25) | ||
1020 | #define OMAP4_HDMI_DDC_SCL_PULLUPRESX_SHIFT 24 | ||
1021 | #define OMAP4_HDMI_DDC_SCL_PULLUPRESX_MASK (1 << 24) | ||
1022 | #define OMAP4_HDMI_DDC_SDA_HSMODE_SHIFT 23 | ||
1023 | #define OMAP4_HDMI_DDC_SDA_HSMODE_MASK (1 << 23) | ||
1024 | #define OMAP4_HDMI_DDC_SDA_NMODE_SHIFT 22 | ||
1025 | #define OMAP4_HDMI_DDC_SDA_NMODE_MASK (1 << 22) | ||
1026 | #define OMAP4_HDMI_DDC_SCL_HSMODE_SHIFT 21 | ||
1027 | #define OMAP4_HDMI_DDC_SCL_HSMODE_MASK (1 << 21) | ||
1028 | #define OMAP4_HDMI_DDC_SCL_NMODE_SHIFT 20 | ||
1029 | #define OMAP4_HDMI_DDC_SCL_NMODE_MASK (1 << 20) | ||
1030 | |||
1031 | /* CONTROL_MMC1 */ | ||
1032 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP0_SHIFT 31 | ||
1033 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP0_MASK (1 << 31) | ||
1034 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP1_SHIFT 30 | ||
1035 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP1_MASK (1 << 30) | ||
1036 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP2_SHIFT 29 | ||
1037 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP2_MASK (1 << 29) | ||
1038 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP3_SHIFT 28 | ||
1039 | #define OMAP4_SDMMC1_PUSTRENGTH_GRP3_MASK (1 << 28) | ||
1040 | #define OMAP4_SDMMC1_DR0_SPEEDCTRL_SHIFT 27 | ||
1041 | #define OMAP4_SDMMC1_DR0_SPEEDCTRL_MASK (1 << 27) | ||
1042 | #define OMAP4_SDMMC1_DR1_SPEEDCTRL_SHIFT 26 | ||
1043 | #define OMAP4_SDMMC1_DR1_SPEEDCTRL_MASK (1 << 26) | ||
1044 | #define OMAP4_SDMMC1_DR2_SPEEDCTRL_SHIFT 25 | ||
1045 | #define OMAP4_SDMMC1_DR2_SPEEDCTRL_MASK (1 << 25) | ||
1046 | #define OMAP4_USBC1_DR0_SPEEDCTRL_SHIFT 24 | ||
1047 | #define OMAP4_USBC1_DR0_SPEEDCTRL_MASK (1 << 24) | ||
1048 | #define OMAP4_USB_FD_CDEN_SHIFT 23 | ||
1049 | #define OMAP4_USB_FD_CDEN_MASK (1 << 23) | ||
1050 | #define OMAP4_USBC1_ICUSB_DP_PDDIS_SHIFT 22 | ||
1051 | #define OMAP4_USBC1_ICUSB_DP_PDDIS_MASK (1 << 22) | ||
1052 | #define OMAP4_USBC1_ICUSB_DM_PDDIS_SHIFT 21 | ||
1053 | #define OMAP4_USBC1_ICUSB_DM_PDDIS_MASK (1 << 21) | ||
1054 | |||
1055 | /* CONTROL_HSI */ | ||
1056 | #define OMAP4_HSI1_CALLOOP_SEL_SHIFT 31 | ||
1057 | #define OMAP4_HSI1_CALLOOP_SEL_MASK (1 << 31) | ||
1058 | #define OMAP4_HSI1_CALMUX_SEL_SHIFT 30 | ||
1059 | #define OMAP4_HSI1_CALMUX_SEL_MASK (1 << 30) | ||
1060 | #define OMAP4_HSI2_CALLOOP_SEL_SHIFT 29 | ||
1061 | #define OMAP4_HSI2_CALLOOP_SEL_MASK (1 << 29) | ||
1062 | #define OMAP4_HSI2_CALMUX_SEL_SHIFT 28 | ||
1063 | #define OMAP4_HSI2_CALMUX_SEL_MASK (1 << 28) | ||
1064 | |||
1065 | /* CONTROL_USB */ | ||
1066 | #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_SHIFT 31 | ||
1067 | #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT0_AUTO_EN_MASK (1 << 31) | ||
1068 | #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_SHIFT 30 | ||
1069 | #define OMAP4_CARKIT_USBA0_ULPIPHY_DAT1_AUTO_EN_MASK (1 << 30) | ||
1070 | |||
1071 | /* CONTROL_HDQ */ | ||
1072 | #define OMAP4_HDQ_SIO_PWRDNZ_SHIFT 31 | ||
1073 | #define OMAP4_HDQ_SIO_PWRDNZ_MASK (1 << 31) | ||
1074 | |||
1075 | /* CONTROL_LPDDR2IO1_0 */ | ||
1076 | #define OMAP4_LPDDR2IO1_GR4_SR_SHIFT 30 | ||
1077 | #define OMAP4_LPDDR2IO1_GR4_SR_MASK (0x3 << 30) | ||
1078 | #define OMAP4_LPDDR2IO1_GR4_I_SHIFT 27 | ||
1079 | #define OMAP4_LPDDR2IO1_GR4_I_MASK (0x7 << 27) | ||
1080 | #define OMAP4_LPDDR2IO1_GR4_WD_SHIFT 25 | ||
1081 | #define OMAP4_LPDDR2IO1_GR4_WD_MASK (0x3 << 25) | ||
1082 | #define OMAP4_LPDDR2IO1_GR3_SR_SHIFT 22 | ||
1083 | #define OMAP4_LPDDR2IO1_GR3_SR_MASK (0x3 << 22) | ||
1084 | #define OMAP4_LPDDR2IO1_GR3_I_SHIFT 19 | ||
1085 | #define OMAP4_LPDDR2IO1_GR3_I_MASK (0x7 << 19) | ||
1086 | #define OMAP4_LPDDR2IO1_GR3_WD_SHIFT 17 | ||
1087 | #define OMAP4_LPDDR2IO1_GR3_WD_MASK (0x3 << 17) | ||
1088 | #define OMAP4_LPDDR2IO1_GR2_SR_SHIFT 14 | ||
1089 | #define OMAP4_LPDDR2IO1_GR2_SR_MASK (0x3 << 14) | ||
1090 | #define OMAP4_LPDDR2IO1_GR2_I_SHIFT 11 | ||
1091 | #define OMAP4_LPDDR2IO1_GR2_I_MASK (0x7 << 11) | ||
1092 | #define OMAP4_LPDDR2IO1_GR2_WD_SHIFT 9 | ||
1093 | #define OMAP4_LPDDR2IO1_GR2_WD_MASK (0x3 << 9) | ||
1094 | #define OMAP4_LPDDR2IO1_GR1_SR_SHIFT 6 | ||
1095 | #define OMAP4_LPDDR2IO1_GR1_SR_MASK (0x3 << 6) | ||
1096 | #define OMAP4_LPDDR2IO1_GR1_I_SHIFT 3 | ||
1097 | #define OMAP4_LPDDR2IO1_GR1_I_MASK (0x7 << 3) | ||
1098 | #define OMAP4_LPDDR2IO1_GR1_WD_SHIFT 1 | ||
1099 | #define OMAP4_LPDDR2IO1_GR1_WD_MASK (0x3 << 1) | ||
1100 | |||
1101 | /* CONTROL_LPDDR2IO1_1 */ | ||
1102 | #define OMAP4_LPDDR2IO1_GR8_SR_SHIFT 30 | ||
1103 | #define OMAP4_LPDDR2IO1_GR8_SR_MASK (0x3 << 30) | ||
1104 | #define OMAP4_LPDDR2IO1_GR8_I_SHIFT 27 | ||
1105 | #define OMAP4_LPDDR2IO1_GR8_I_MASK (0x7 << 27) | ||
1106 | #define OMAP4_LPDDR2IO1_GR8_WD_SHIFT 25 | ||
1107 | #define OMAP4_LPDDR2IO1_GR8_WD_MASK (0x3 << 25) | ||
1108 | #define OMAP4_LPDDR2IO1_GR7_SR_SHIFT 22 | ||
1109 | #define OMAP4_LPDDR2IO1_GR7_SR_MASK (0x3 << 22) | ||
1110 | #define OMAP4_LPDDR2IO1_GR7_I_SHIFT 19 | ||
1111 | #define OMAP4_LPDDR2IO1_GR7_I_MASK (0x7 << 19) | ||
1112 | #define OMAP4_LPDDR2IO1_GR7_WD_SHIFT 17 | ||
1113 | #define OMAP4_LPDDR2IO1_GR7_WD_MASK (0x3 << 17) | ||
1114 | #define OMAP4_LPDDR2IO1_GR6_SR_SHIFT 14 | ||
1115 | #define OMAP4_LPDDR2IO1_GR6_SR_MASK (0x3 << 14) | ||
1116 | #define OMAP4_LPDDR2IO1_GR6_I_SHIFT 11 | ||
1117 | #define OMAP4_LPDDR2IO1_GR6_I_MASK (0x7 << 11) | ||
1118 | #define OMAP4_LPDDR2IO1_GR6_WD_SHIFT 9 | ||
1119 | #define OMAP4_LPDDR2IO1_GR6_WD_MASK (0x3 << 9) | ||
1120 | #define OMAP4_LPDDR2IO1_GR5_SR_SHIFT 6 | ||
1121 | #define OMAP4_LPDDR2IO1_GR5_SR_MASK (0x3 << 6) | ||
1122 | #define OMAP4_LPDDR2IO1_GR5_I_SHIFT 3 | ||
1123 | #define OMAP4_LPDDR2IO1_GR5_I_MASK (0x7 << 3) | ||
1124 | #define OMAP4_LPDDR2IO1_GR5_WD_SHIFT 1 | ||
1125 | #define OMAP4_LPDDR2IO1_GR5_WD_MASK (0x3 << 1) | ||
1126 | |||
1127 | /* CONTROL_LPDDR2IO1_2 */ | ||
1128 | #define OMAP4_LPDDR2IO1_GR11_SR_SHIFT 30 | ||
1129 | #define OMAP4_LPDDR2IO1_GR11_SR_MASK (0x3 << 30) | ||
1130 | #define OMAP4_LPDDR2IO1_GR11_I_SHIFT 27 | ||
1131 | #define OMAP4_LPDDR2IO1_GR11_I_MASK (0x7 << 27) | ||
1132 | #define OMAP4_LPDDR2IO1_GR11_WD_SHIFT 25 | ||
1133 | #define OMAP4_LPDDR2IO1_GR11_WD_MASK (0x3 << 25) | ||
1134 | #define OMAP4_LPDDR2IO1_GR10_SR_SHIFT 22 | ||
1135 | #define OMAP4_LPDDR2IO1_GR10_SR_MASK (0x3 << 22) | ||
1136 | #define OMAP4_LPDDR2IO1_GR10_I_SHIFT 19 | ||
1137 | #define OMAP4_LPDDR2IO1_GR10_I_MASK (0x7 << 19) | ||
1138 | #define OMAP4_LPDDR2IO1_GR10_WD_SHIFT 17 | ||
1139 | #define OMAP4_LPDDR2IO1_GR10_WD_MASK (0x3 << 17) | ||
1140 | #define OMAP4_LPDDR2IO1_GR9_SR_SHIFT 14 | ||
1141 | #define OMAP4_LPDDR2IO1_GR9_SR_MASK (0x3 << 14) | ||
1142 | #define OMAP4_LPDDR2IO1_GR9_I_SHIFT 11 | ||
1143 | #define OMAP4_LPDDR2IO1_GR9_I_MASK (0x7 << 11) | ||
1144 | #define OMAP4_LPDDR2IO1_GR9_WD_SHIFT 9 | ||
1145 | #define OMAP4_LPDDR2IO1_GR9_WD_MASK (0x3 << 9) | ||
1146 | |||
1147 | /* CONTROL_LPDDR2IO1_3 */ | ||
1148 | #define OMAP4_LPDDR21_VREF_CA_CCAP0_SHIFT 31 | ||
1149 | #define OMAP4_LPDDR21_VREF_CA_CCAP0_MASK (1 << 31) | ||
1150 | #define OMAP4_LPDDR21_VREF_CA_CCAP1_SHIFT 30 | ||
1151 | #define OMAP4_LPDDR21_VREF_CA_CCAP1_MASK (1 << 30) | ||
1152 | #define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_SHIFT 29 | ||
1153 | #define OMAP4_LPDDR21_VREF_CA_INT_CCAP0_MASK (1 << 29) | ||
1154 | #define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_SHIFT 28 | ||
1155 | #define OMAP4_LPDDR21_VREF_CA_INT_CCAP1_MASK (1 << 28) | ||
1156 | #define OMAP4_LPDDR21_VREF_CA_INT_TAP0_SHIFT 27 | ||
1157 | #define OMAP4_LPDDR21_VREF_CA_INT_TAP0_MASK (1 << 27) | ||
1158 | #define OMAP4_LPDDR21_VREF_CA_INT_TAP1_SHIFT 26 | ||
1159 | #define OMAP4_LPDDR21_VREF_CA_INT_TAP1_MASK (1 << 26) | ||
1160 | #define OMAP4_LPDDR21_VREF_CA_TAP0_SHIFT 25 | ||
1161 | #define OMAP4_LPDDR21_VREF_CA_TAP0_MASK (1 << 25) | ||
1162 | #define OMAP4_LPDDR21_VREF_CA_TAP1_SHIFT 24 | ||
1163 | #define OMAP4_LPDDR21_VREF_CA_TAP1_MASK (1 << 24) | ||
1164 | #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_SHIFT 23 | ||
1165 | #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP0_MASK (1 << 23) | ||
1166 | #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_SHIFT 22 | ||
1167 | #define OMAP4_LPDDR21_VREF_DQ0_INT_CCAP1_MASK (1 << 22) | ||
1168 | #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_SHIFT 21 | ||
1169 | #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP0_MASK (1 << 21) | ||
1170 | #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_SHIFT 20 | ||
1171 | #define OMAP4_LPDDR21_VREF_DQ0_INT_TAP1_MASK (1 << 20) | ||
1172 | #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_SHIFT 19 | ||
1173 | #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP0_MASK (1 << 19) | ||
1174 | #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_SHIFT 18 | ||
1175 | #define OMAP4_LPDDR21_VREF_DQ1_INT_CCAP1_MASK (1 << 18) | ||
1176 | #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_SHIFT 17 | ||
1177 | #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP0_MASK (1 << 17) | ||
1178 | #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_SHIFT 16 | ||
1179 | #define OMAP4_LPDDR21_VREF_DQ1_INT_TAP1_MASK (1 << 16) | ||
1180 | #define OMAP4_LPDDR21_VREF_DQ_CCAP0_SHIFT 15 | ||
1181 | #define OMAP4_LPDDR21_VREF_DQ_CCAP0_MASK (1 << 15) | ||
1182 | #define OMAP4_LPDDR21_VREF_DQ_CCAP1_SHIFT 14 | ||
1183 | #define OMAP4_LPDDR21_VREF_DQ_CCAP1_MASK (1 << 14) | ||
1184 | #define OMAP4_LPDDR21_VREF_DQ_TAP0_SHIFT 13 | ||
1185 | #define OMAP4_LPDDR21_VREF_DQ_TAP0_MASK (1 << 13) | ||
1186 | #define OMAP4_LPDDR21_VREF_DQ_TAP1_SHIFT 12 | ||
1187 | #define OMAP4_LPDDR21_VREF_DQ_TAP1_MASK (1 << 12) | ||
1188 | |||
1189 | /* CONTROL_LPDDR2IO2_0 */ | ||
1190 | #define OMAP4_LPDDR2IO2_GR4_SR_SHIFT 30 | ||
1191 | #define OMAP4_LPDDR2IO2_GR4_SR_MASK (0x3 << 30) | ||
1192 | #define OMAP4_LPDDR2IO2_GR4_I_SHIFT 27 | ||
1193 | #define OMAP4_LPDDR2IO2_GR4_I_MASK (0x7 << 27) | ||
1194 | #define OMAP4_LPDDR2IO2_GR4_WD_SHIFT 25 | ||
1195 | #define OMAP4_LPDDR2IO2_GR4_WD_MASK (0x3 << 25) | ||
1196 | #define OMAP4_LPDDR2IO2_GR3_SR_SHIFT 22 | ||
1197 | #define OMAP4_LPDDR2IO2_GR3_SR_MASK (0x3 << 22) | ||
1198 | #define OMAP4_LPDDR2IO2_GR3_I_SHIFT 19 | ||
1199 | #define OMAP4_LPDDR2IO2_GR3_I_MASK (0x7 << 19) | ||
1200 | #define OMAP4_LPDDR2IO2_GR3_WD_SHIFT 17 | ||
1201 | #define OMAP4_LPDDR2IO2_GR3_WD_MASK (0x3 << 17) | ||
1202 | #define OMAP4_LPDDR2IO2_GR2_SR_SHIFT 14 | ||
1203 | #define OMAP4_LPDDR2IO2_GR2_SR_MASK (0x3 << 14) | ||
1204 | #define OMAP4_LPDDR2IO2_GR2_I_SHIFT 11 | ||
1205 | #define OMAP4_LPDDR2IO2_GR2_I_MASK (0x7 << 11) | ||
1206 | #define OMAP4_LPDDR2IO2_GR2_WD_SHIFT 9 | ||
1207 | #define OMAP4_LPDDR2IO2_GR2_WD_MASK (0x3 << 9) | ||
1208 | #define OMAP4_LPDDR2IO2_GR1_SR_SHIFT 6 | ||
1209 | #define OMAP4_LPDDR2IO2_GR1_SR_MASK (0x3 << 6) | ||
1210 | #define OMAP4_LPDDR2IO2_GR1_I_SHIFT 3 | ||
1211 | #define OMAP4_LPDDR2IO2_GR1_I_MASK (0x7 << 3) | ||
1212 | #define OMAP4_LPDDR2IO2_GR1_WD_SHIFT 1 | ||
1213 | #define OMAP4_LPDDR2IO2_GR1_WD_MASK (0x3 << 1) | ||
1214 | |||
1215 | /* CONTROL_LPDDR2IO2_1 */ | ||
1216 | #define OMAP4_LPDDR2IO2_GR8_SR_SHIFT 30 | ||
1217 | #define OMAP4_LPDDR2IO2_GR8_SR_MASK (0x3 << 30) | ||
1218 | #define OMAP4_LPDDR2IO2_GR8_I_SHIFT 27 | ||
1219 | #define OMAP4_LPDDR2IO2_GR8_I_MASK (0x7 << 27) | ||
1220 | #define OMAP4_LPDDR2IO2_GR8_WD_SHIFT 25 | ||
1221 | #define OMAP4_LPDDR2IO2_GR8_WD_MASK (0x3 << 25) | ||
1222 | #define OMAP4_LPDDR2IO2_GR7_SR_SHIFT 22 | ||
1223 | #define OMAP4_LPDDR2IO2_GR7_SR_MASK (0x3 << 22) | ||
1224 | #define OMAP4_LPDDR2IO2_GR7_I_SHIFT 19 | ||
1225 | #define OMAP4_LPDDR2IO2_GR7_I_MASK (0x7 << 19) | ||
1226 | #define OMAP4_LPDDR2IO2_GR7_WD_SHIFT 17 | ||
1227 | #define OMAP4_LPDDR2IO2_GR7_WD_MASK (0x3 << 17) | ||
1228 | #define OMAP4_LPDDR2IO2_GR6_SR_SHIFT 14 | ||
1229 | #define OMAP4_LPDDR2IO2_GR6_SR_MASK (0x3 << 14) | ||
1230 | #define OMAP4_LPDDR2IO2_GR6_I_SHIFT 11 | ||
1231 | #define OMAP4_LPDDR2IO2_GR6_I_MASK (0x7 << 11) | ||
1232 | #define OMAP4_LPDDR2IO2_GR6_WD_SHIFT 9 | ||
1233 | #define OMAP4_LPDDR2IO2_GR6_WD_MASK (0x3 << 9) | ||
1234 | #define OMAP4_LPDDR2IO2_GR5_SR_SHIFT 6 | ||
1235 | #define OMAP4_LPDDR2IO2_GR5_SR_MASK (0x3 << 6) | ||
1236 | #define OMAP4_LPDDR2IO2_GR5_I_SHIFT 3 | ||
1237 | #define OMAP4_LPDDR2IO2_GR5_I_MASK (0x7 << 3) | ||
1238 | #define OMAP4_LPDDR2IO2_GR5_WD_SHIFT 1 | ||
1239 | #define OMAP4_LPDDR2IO2_GR5_WD_MASK (0x3 << 1) | ||
1240 | |||
1241 | /* CONTROL_LPDDR2IO2_2 */ | ||
1242 | #define OMAP4_LPDDR2IO2_GR11_SR_SHIFT 30 | ||
1243 | #define OMAP4_LPDDR2IO2_GR11_SR_MASK (0x3 << 30) | ||
1244 | #define OMAP4_LPDDR2IO2_GR11_I_SHIFT 27 | ||
1245 | #define OMAP4_LPDDR2IO2_GR11_I_MASK (0x7 << 27) | ||
1246 | #define OMAP4_LPDDR2IO2_GR11_WD_SHIFT 25 | ||
1247 | #define OMAP4_LPDDR2IO2_GR11_WD_MASK (0x3 << 25) | ||
1248 | #define OMAP4_LPDDR2IO2_GR10_SR_SHIFT 22 | ||
1249 | #define OMAP4_LPDDR2IO2_GR10_SR_MASK (0x3 << 22) | ||
1250 | #define OMAP4_LPDDR2IO2_GR10_I_SHIFT 19 | ||
1251 | #define OMAP4_LPDDR2IO2_GR10_I_MASK (0x7 << 19) | ||
1252 | #define OMAP4_LPDDR2IO2_GR10_WD_SHIFT 17 | ||
1253 | #define OMAP4_LPDDR2IO2_GR10_WD_MASK (0x3 << 17) | ||
1254 | #define OMAP4_LPDDR2IO2_GR9_SR_SHIFT 14 | ||
1255 | #define OMAP4_LPDDR2IO2_GR9_SR_MASK (0x3 << 14) | ||
1256 | #define OMAP4_LPDDR2IO2_GR9_I_SHIFT 11 | ||
1257 | #define OMAP4_LPDDR2IO2_GR9_I_MASK (0x7 << 11) | ||
1258 | #define OMAP4_LPDDR2IO2_GR9_WD_SHIFT 9 | ||
1259 | #define OMAP4_LPDDR2IO2_GR9_WD_MASK (0x3 << 9) | ||
1260 | |||
1261 | /* CONTROL_LPDDR2IO2_3 */ | ||
1262 | #define OMAP4_LPDDR22_VREF_CA_CCAP0_SHIFT 31 | ||
1263 | #define OMAP4_LPDDR22_VREF_CA_CCAP0_MASK (1 << 31) | ||
1264 | #define OMAP4_LPDDR22_VREF_CA_CCAP1_SHIFT 30 | ||
1265 | #define OMAP4_LPDDR22_VREF_CA_CCAP1_MASK (1 << 30) | ||
1266 | #define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_SHIFT 29 | ||
1267 | #define OMAP4_LPDDR22_VREF_CA_INT_CCAP0_MASK (1 << 29) | ||
1268 | #define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_SHIFT 28 | ||
1269 | #define OMAP4_LPDDR22_VREF_CA_INT_CCAP1_MASK (1 << 28) | ||
1270 | #define OMAP4_LPDDR22_VREF_CA_INT_TAP0_SHIFT 27 | ||
1271 | #define OMAP4_LPDDR22_VREF_CA_INT_TAP0_MASK (1 << 27) | ||
1272 | #define OMAP4_LPDDR22_VREF_CA_INT_TAP1_SHIFT 26 | ||
1273 | #define OMAP4_LPDDR22_VREF_CA_INT_TAP1_MASK (1 << 26) | ||
1274 | #define OMAP4_LPDDR22_VREF_CA_TAP0_SHIFT 25 | ||
1275 | #define OMAP4_LPDDR22_VREF_CA_TAP0_MASK (1 << 25) | ||
1276 | #define OMAP4_LPDDR22_VREF_CA_TAP1_SHIFT 24 | ||
1277 | #define OMAP4_LPDDR22_VREF_CA_TAP1_MASK (1 << 24) | ||
1278 | #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_SHIFT 23 | ||
1279 | #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP0_MASK (1 << 23) | ||
1280 | #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_SHIFT 22 | ||
1281 | #define OMAP4_LPDDR22_VREF_DQ0_INT_CCAP1_MASK (1 << 22) | ||
1282 | #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_SHIFT 21 | ||
1283 | #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP0_MASK (1 << 21) | ||
1284 | #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_SHIFT 20 | ||
1285 | #define OMAP4_LPDDR22_VREF_DQ0_INT_TAP1_MASK (1 << 20) | ||
1286 | #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_SHIFT 19 | ||
1287 | #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP0_MASK (1 << 19) | ||
1288 | #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_SHIFT 18 | ||
1289 | #define OMAP4_LPDDR22_VREF_DQ1_INT_CCAP1_MASK (1 << 18) | ||
1290 | #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_SHIFT 17 | ||
1291 | #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP0_MASK (1 << 17) | ||
1292 | #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_SHIFT 16 | ||
1293 | #define OMAP4_LPDDR22_VREF_DQ1_INT_TAP1_MASK (1 << 16) | ||
1294 | #define OMAP4_LPDDR22_VREF_DQ_CCAP0_SHIFT 15 | ||
1295 | #define OMAP4_LPDDR22_VREF_DQ_CCAP0_MASK (1 << 15) | ||
1296 | #define OMAP4_LPDDR22_VREF_DQ_CCAP1_SHIFT 14 | ||
1297 | #define OMAP4_LPDDR22_VREF_DQ_CCAP1_MASK (1 << 14) | ||
1298 | #define OMAP4_LPDDR22_VREF_DQ_TAP0_SHIFT 13 | ||
1299 | #define OMAP4_LPDDR22_VREF_DQ_TAP0_MASK (1 << 13) | ||
1300 | #define OMAP4_LPDDR22_VREF_DQ_TAP1_SHIFT 12 | ||
1301 | #define OMAP4_LPDDR22_VREF_DQ_TAP1_MASK (1 << 12) | ||
1302 | |||
1303 | /* CONTROL_BUS_HOLD */ | ||
1304 | #define OMAP4_ABE_DMIC_DIN3_EN_SHIFT 31 | ||
1305 | #define OMAP4_ABE_DMIC_DIN3_EN_MASK (1 << 31) | ||
1306 | #define OMAP4_MCSPI1_CS3_EN_SHIFT 30 | ||
1307 | #define OMAP4_MCSPI1_CS3_EN_MASK (1 << 30) | ||
1308 | |||
1309 | /* CONTROL_C2C */ | ||
1310 | #define OMAP4_MIRROR_MODE_EN_SHIFT 31 | ||
1311 | #define OMAP4_MIRROR_MODE_EN_MASK (1 << 31) | ||
1312 | #define OMAP4_C2C_SPARE_SHIFT 24 | ||
1313 | #define OMAP4_C2C_SPARE_MASK (0x7f << 24) | ||
1314 | |||
1315 | /* CORE_CONTROL_SPARE_RW */ | ||
1316 | #define OMAP4_CORE_CONTROL_SPARE_RW_SHIFT 0 | ||
1317 | #define OMAP4_CORE_CONTROL_SPARE_RW_MASK (0xffffffff << 0) | ||
1318 | |||
1319 | /* CORE_CONTROL_SPARE_R */ | ||
1320 | #define OMAP4_CORE_CONTROL_SPARE_R_SHIFT 0 | ||
1321 | #define OMAP4_CORE_CONTROL_SPARE_R_MASK (0xffffffff << 0) | ||
1322 | |||
1323 | /* CORE_CONTROL_SPARE_R_C0 */ | ||
1324 | #define OMAP4_CORE_CONTROL_SPARE_R_C0_SHIFT 31 | ||
1325 | #define OMAP4_CORE_CONTROL_SPARE_R_C0_MASK (1 << 31) | ||
1326 | #define OMAP4_CORE_CONTROL_SPARE_R_C1_SHIFT 30 | ||
1327 | #define OMAP4_CORE_CONTROL_SPARE_R_C1_MASK (1 << 30) | ||
1328 | #define OMAP4_CORE_CONTROL_SPARE_R_C2_SHIFT 29 | ||
1329 | #define OMAP4_CORE_CONTROL_SPARE_R_C2_MASK (1 << 29) | ||
1330 | #define OMAP4_CORE_CONTROL_SPARE_R_C3_SHIFT 28 | ||
1331 | #define OMAP4_CORE_CONTROL_SPARE_R_C3_MASK (1 << 28) | ||
1332 | #define OMAP4_CORE_CONTROL_SPARE_R_C4_SHIFT 27 | ||
1333 | #define OMAP4_CORE_CONTROL_SPARE_R_C4_MASK (1 << 27) | ||
1334 | #define OMAP4_CORE_CONTROL_SPARE_R_C5_SHIFT 26 | ||
1335 | #define OMAP4_CORE_CONTROL_SPARE_R_C5_MASK (1 << 26) | ||
1336 | #define OMAP4_CORE_CONTROL_SPARE_R_C6_SHIFT 25 | ||
1337 | #define OMAP4_CORE_CONTROL_SPARE_R_C6_MASK (1 << 25) | ||
1338 | #define OMAP4_CORE_CONTROL_SPARE_R_C7_SHIFT 24 | ||
1339 | #define OMAP4_CORE_CONTROL_SPARE_R_C7_MASK (1 << 24) | ||
1340 | |||
1341 | /* CONTROL_EFUSE_1 */ | ||
1342 | #define OMAP4_AVDAC_TRIM_BYTE3_SHIFT 24 | ||
1343 | #define OMAP4_AVDAC_TRIM_BYTE3_MASK (0x7f << 24) | ||
1344 | #define OMAP4_AVDAC_TRIM_BYTE2_SHIFT 16 | ||
1345 | #define OMAP4_AVDAC_TRIM_BYTE2_MASK (0xff << 16) | ||
1346 | #define OMAP4_AVDAC_TRIM_BYTE1_SHIFT 8 | ||
1347 | #define OMAP4_AVDAC_TRIM_BYTE1_MASK (0xff << 8) | ||
1348 | #define OMAP4_AVDAC_TRIM_BYTE0_SHIFT 0 | ||
1349 | #define OMAP4_AVDAC_TRIM_BYTE0_MASK (0xff << 0) | ||
1350 | |||
1351 | /* CONTROL_EFUSE_2 */ | ||
1352 | #define OMAP4_EFUSE_SMART2TEST_P0_SHIFT 31 | ||
1353 | #define OMAP4_EFUSE_SMART2TEST_P0_MASK (1 << 31) | ||
1354 | #define OMAP4_EFUSE_SMART2TEST_P1_SHIFT 30 | ||
1355 | #define OMAP4_EFUSE_SMART2TEST_P1_MASK (1 << 30) | ||
1356 | #define OMAP4_EFUSE_SMART2TEST_P2_SHIFT 29 | ||
1357 | #define OMAP4_EFUSE_SMART2TEST_P2_MASK (1 << 29) | ||
1358 | #define OMAP4_EFUSE_SMART2TEST_P3_SHIFT 28 | ||
1359 | #define OMAP4_EFUSE_SMART2TEST_P3_MASK (1 << 28) | ||
1360 | #define OMAP4_EFUSE_SMART2TEST_N0_SHIFT 27 | ||
1361 | #define OMAP4_EFUSE_SMART2TEST_N0_MASK (1 << 27) | ||
1362 | #define OMAP4_EFUSE_SMART2TEST_N1_SHIFT 26 | ||
1363 | #define OMAP4_EFUSE_SMART2TEST_N1_MASK (1 << 26) | ||
1364 | #define OMAP4_EFUSE_SMART2TEST_N2_SHIFT 25 | ||
1365 | #define OMAP4_EFUSE_SMART2TEST_N2_MASK (1 << 25) | ||
1366 | #define OMAP4_EFUSE_SMART2TEST_N3_SHIFT 24 | ||
1367 | #define OMAP4_EFUSE_SMART2TEST_N3_MASK (1 << 24) | ||
1368 | #define OMAP4_LPDDR2_PTV_N1_SHIFT 23 | ||
1369 | #define OMAP4_LPDDR2_PTV_N1_MASK (1 << 23) | ||
1370 | #define OMAP4_LPDDR2_PTV_N2_SHIFT 22 | ||
1371 | #define OMAP4_LPDDR2_PTV_N2_MASK (1 << 22) | ||
1372 | #define OMAP4_LPDDR2_PTV_N3_SHIFT 21 | ||
1373 | #define OMAP4_LPDDR2_PTV_N3_MASK (1 << 21) | ||
1374 | #define OMAP4_LPDDR2_PTV_N4_SHIFT 20 | ||
1375 | #define OMAP4_LPDDR2_PTV_N4_MASK (1 << 20) | ||
1376 | #define OMAP4_LPDDR2_PTV_N5_SHIFT 19 | ||
1377 | #define OMAP4_LPDDR2_PTV_N5_MASK (1 << 19) | ||
1378 | #define OMAP4_LPDDR2_PTV_P1_SHIFT 18 | ||
1379 | #define OMAP4_LPDDR2_PTV_P1_MASK (1 << 18) | ||
1380 | #define OMAP4_LPDDR2_PTV_P2_SHIFT 17 | ||
1381 | #define OMAP4_LPDDR2_PTV_P2_MASK (1 << 17) | ||
1382 | #define OMAP4_LPDDR2_PTV_P3_SHIFT 16 | ||
1383 | #define OMAP4_LPDDR2_PTV_P3_MASK (1 << 16) | ||
1384 | #define OMAP4_LPDDR2_PTV_P4_SHIFT 15 | ||
1385 | #define OMAP4_LPDDR2_PTV_P4_MASK (1 << 15) | ||
1386 | #define OMAP4_LPDDR2_PTV_P5_SHIFT 14 | ||
1387 | #define OMAP4_LPDDR2_PTV_P5_MASK (1 << 14) | ||
1388 | |||
1389 | /* CONTROL_EFUSE_3 */ | ||
1390 | #define OMAP4_STD_FUSE_SPARE_1_SHIFT 24 | ||
1391 | #define OMAP4_STD_FUSE_SPARE_1_MASK (0xff << 24) | ||
1392 | #define OMAP4_STD_FUSE_SPARE_2_SHIFT 16 | ||
1393 | #define OMAP4_STD_FUSE_SPARE_2_MASK (0xff << 16) | ||
1394 | #define OMAP4_STD_FUSE_SPARE_3_SHIFT 8 | ||
1395 | #define OMAP4_STD_FUSE_SPARE_3_MASK (0xff << 8) | ||
1396 | #define OMAP4_STD_FUSE_SPARE_4_SHIFT 0 | ||
1397 | #define OMAP4_STD_FUSE_SPARE_4_MASK (0xff << 0) | ||
1398 | |||
1399 | /* CONTROL_EFUSE_4 */ | ||
1400 | #define OMAP4_STD_FUSE_SPARE_5_SHIFT 24 | ||
1401 | #define OMAP4_STD_FUSE_SPARE_5_MASK (0xff << 24) | ||
1402 | #define OMAP4_STD_FUSE_SPARE_6_SHIFT 16 | ||
1403 | #define OMAP4_STD_FUSE_SPARE_6_MASK (0xff << 16) | ||
1404 | #define OMAP4_STD_FUSE_SPARE_7_SHIFT 8 | ||
1405 | #define OMAP4_STD_FUSE_SPARE_7_MASK (0xff << 8) | ||
1406 | #define OMAP4_STD_FUSE_SPARE_8_SHIFT 0 | ||
1407 | #define OMAP4_STD_FUSE_SPARE_8_MASK (0xff << 0) | ||
1408 | |||
1409 | #endif | ||
diff --git a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h b/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h deleted file mode 100644 index 17c9b37042c0..000000000000 --- a/arch/arm/mach-omap2/ctrl_module_pad_wkup_44xx.h +++ /dev/null | |||
@@ -1,236 +0,0 @@ | |||
1 | /* | ||
2 | * OMAP44xx CTRL_MODULE_PAD_WKUP registers and bitfields | ||
3 | * | ||
4 | * Copyright (C) 2009-2010 Texas Instruments, Inc. | ||
5 | * | ||
6 | * Benoit Cousson (b-cousson@ti.com) | ||
7 | * Santosh Shilimkar (santosh.shilimkar@ti.com) | ||
8 | * | ||
9 | * This file is automatically generated from the OMAP hardware databases. | ||
10 | * We respectfully ask that any modifications to this file be coordinated | ||
11 | * with the public linux-omap@vger.kernel.org mailing list and the | ||
12 | * authors above to ensure that the autogeneration scripts are kept | ||
13 | * up-to-date with the file contents. | ||
14 | * | ||
15 | * This program is free software; you can redistribute it and/or modify | ||
16 | * it under the terms of the GNU General Public License version 2 as | ||
17 | * published by the Free Software Foundation. | ||
18 | */ | ||
19 | |||
20 | #ifndef __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H | ||
21 | #define __ARCH_ARM_MACH_OMAP2_CTRL_MODULE_PAD_WKUP_44XX_H | ||
22 | |||
23 | |||
24 | /* Base address */ | ||
25 | #define OMAP4_CTRL_MODULE_PAD_WKUP 0x4a31e000 | ||
26 | |||
27 | /* Registers offset */ | ||
28 | #define OMAP4_CTRL_MODULE_PAD_WKUP_IP_REVISION 0x0000 | ||
29 | #define OMAP4_CTRL_MODULE_PAD_WKUP_IP_HWINFO 0x0004 | ||
30 | #define OMAP4_CTRL_MODULE_PAD_WKUP_IP_SYSCONFIG 0x0010 | ||
31 | #define OMAP4_CTRL_MODULE_PAD_WKUP_PADCONF_WAKEUPEVENT_0 0x007c | ||
32 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_0 0x05a0 | ||
33 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SMART1NOPMIO_PADCONF_1 0x05a4 | ||
34 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_PADCONF_MODE 0x05a8 | ||
35 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_XTAL_OSCILLATOR 0x05ac | ||
36 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_USIMIO 0x0600 | ||
37 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_I2C_2 0x0604 | ||
38 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_JTAG 0x0608 | ||
39 | #define OMAP4_CTRL_MODULE_PAD_WKUP_CONTROL_SYS 0x060c | ||
40 | #define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_RW 0x0614 | ||
41 | #define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R 0x0618 | ||
42 | #define OMAP4_CTRL_MODULE_PAD_WKUP_WKUP_CONTROL_SPARE_R_C0 0x061c | ||
43 | |||
44 | /* Registers shifts and masks */ | ||
45 | |||
46 | /* IP_REVISION */ | ||
47 | #define OMAP4_IP_REV_SCHEME_SHIFT 30 | ||
48 | #define OMAP4_IP_REV_SCHEME_MASK (0x3 << 30) | ||
49 | #define OMAP4_IP_REV_FUNC_SHIFT 16 | ||
50 | #define OMAP4_IP_REV_FUNC_MASK (0xfff << 16) | ||
51 | #define OMAP4_IP_REV_RTL_SHIFT 11 | ||
52 | #define OMAP4_IP_REV_RTL_MASK (0x1f << 11) | ||
53 | #define OMAP4_IP_REV_MAJOR_SHIFT 8 | ||
54 | #define OMAP4_IP_REV_MAJOR_MASK (0x7 << 8) | ||
55 | #define OMAP4_IP_REV_CUSTOM_SHIFT 6 | ||
56 | #define OMAP4_IP_REV_CUSTOM_MASK (0x3 << 6) | ||
57 | #define OMAP4_IP_REV_MINOR_SHIFT 0 | ||
58 | #define OMAP4_IP_REV_MINOR_MASK (0x3f << 0) | ||
59 | |||
60 | /* IP_HWINFO */ | ||
61 | #define OMAP4_IP_HWINFO_SHIFT 0 | ||
62 | #define OMAP4_IP_HWINFO_MASK (0xffffffff << 0) | ||
63 | |||
64 | /* IP_SYSCONFIG */ | ||
65 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_SHIFT 2 | ||
66 | #define OMAP4_IP_SYSCONFIG_IDLEMODE_MASK (0x3 << 2) | ||
67 | |||
68 | /* PADCONF_WAKEUPEVENT_0 */ | ||
69 | #define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_SHIFT 24 | ||
70 | #define OMAP4_JTAG_TDO_DUPLICATEWAKEUPEVENT_MASK (1 << 24) | ||
71 | #define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_SHIFT 23 | ||
72 | #define OMAP4_JTAG_TDI_DUPLICATEWAKEUPEVENT_MASK (1 << 23) | ||
73 | #define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_SHIFT 22 | ||
74 | #define OMAP4_JTAG_TMS_TMSC_DUPLICATEWAKEUPEVENT_MASK (1 << 22) | ||
75 | #define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_SHIFT 21 | ||
76 | #define OMAP4_JTAG_RTCK_DUPLICATEWAKEUPEVENT_MASK (1 << 21) | ||
77 | #define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_SHIFT 20 | ||
78 | #define OMAP4_JTAG_TCK_DUPLICATEWAKEUPEVENT_MASK (1 << 20) | ||
79 | #define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_SHIFT 19 | ||
80 | #define OMAP4_JTAG_NTRST_DUPLICATEWAKEUPEVENT_MASK (1 << 19) | ||
81 | #define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_SHIFT 18 | ||
82 | #define OMAP4_SYS_BOOT7_DUPLICATEWAKEUPEVENT_MASK (1 << 18) | ||
83 | #define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_SHIFT 17 | ||
84 | #define OMAP4_SYS_BOOT6_DUPLICATEWAKEUPEVENT_MASK (1 << 17) | ||
85 | #define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_SHIFT 16 | ||
86 | #define OMAP4_SYS_PWRON_RESET_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 16) | ||
87 | #define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_SHIFT 15 | ||
88 | #define OMAP4_SYS_PWR_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 15) | ||
89 | #define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_SHIFT 14 | ||
90 | #define OMAP4_SYS_NRESWARM_DUPLICATEWAKEUPEVENT_MASK (1 << 14) | ||
91 | #define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_SHIFT 13 | ||
92 | #define OMAP4_SYS_32K_DUPLICATEWAKEUPEVENT_MASK (1 << 13) | ||
93 | #define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_SHIFT 12 | ||
94 | #define OMAP4_FREF_CLK4_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 12) | ||
95 | #define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_SHIFT 11 | ||
96 | #define OMAP4_FREF_CLK4_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 11) | ||
97 | #define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_SHIFT 10 | ||
98 | #define OMAP4_FREF_CLK3_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 10) | ||
99 | #define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_SHIFT 9 | ||
100 | #define OMAP4_FREF_CLK3_REQ_DUPLICATEWAKEUPEVENT_MASK (1 << 9) | ||
101 | #define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_SHIFT 8 | ||
102 | #define OMAP4_FREF_CLK0_OUT_DUPLICATEWAKEUPEVENT_MASK (1 << 8) | ||
103 | #define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_SHIFT 7 | ||
104 | #define OMAP4_FREF_CLK_IOREQ_DUPLICATEWAKEUPEVENT_MASK (1 << 7) | ||
105 | #define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_SHIFT 6 | ||
106 | #define OMAP4_SR_SDA_DUPLICATEWAKEUPEVENT_MASK (1 << 6) | ||
107 | #define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_SHIFT 5 | ||
108 | #define OMAP4_SR_SCL_DUPLICATEWAKEUPEVENT_MASK (1 << 5) | ||
109 | #define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_SHIFT 4 | ||
110 | #define OMAP4_SIM_PWRCTRL_DUPLICATEWAKEUPEVENT_MASK (1 << 4) | ||
111 | #define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_SHIFT 3 | ||
112 | #define OMAP4_SIM_CD_DUPLICATEWAKEUPEVENT_MASK (1 << 3) | ||
113 | #define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_SHIFT 2 | ||
114 | #define OMAP4_SIM_RESET_DUPLICATEWAKEUPEVENT_MASK (1 << 2) | ||
115 | #define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_SHIFT 1 | ||
116 | #define OMAP4_SIM_CLK_DUPLICATEWAKEUPEVENT_MASK (1 << 1) | ||
117 | #define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_SHIFT 0 | ||
118 | #define OMAP4_SIM_IO_DUPLICATEWAKEUPEVENT_MASK (1 << 0) | ||
119 | |||
120 | /* CONTROL_SMART1NOPMIO_PADCONF_0 */ | ||
121 | #define OMAP4_FREF_DR0_SC_SHIFT 30 | ||
122 | #define OMAP4_FREF_DR0_SC_MASK (0x3 << 30) | ||
123 | #define OMAP4_FREF_DR1_SC_SHIFT 28 | ||
124 | #define OMAP4_FREF_DR1_SC_MASK (0x3 << 28) | ||
125 | #define OMAP4_FREF_DR4_SC_SHIFT 26 | ||
126 | #define OMAP4_FREF_DR4_SC_MASK (0x3 << 26) | ||
127 | #define OMAP4_FREF_DR5_SC_SHIFT 24 | ||
128 | #define OMAP4_FREF_DR5_SC_MASK (0x3 << 24) | ||
129 | #define OMAP4_FREF_DR6_SC_SHIFT 22 | ||
130 | #define OMAP4_FREF_DR6_SC_MASK (0x3 << 22) | ||
131 | #define OMAP4_FREF_DR7_SC_SHIFT 20 | ||
132 | #define OMAP4_FREF_DR7_SC_MASK (0x3 << 20) | ||
133 | #define OMAP4_GPIO_DR7_SC_SHIFT 18 | ||
134 | #define OMAP4_GPIO_DR7_SC_MASK (0x3 << 18) | ||
135 | #define OMAP4_DPM_DR0_SC_SHIFT 14 | ||
136 | #define OMAP4_DPM_DR0_SC_MASK (0x3 << 14) | ||
137 | #define OMAP4_SIM_DR0_SC_SHIFT 12 | ||
138 | #define OMAP4_SIM_DR0_SC_MASK (0x3 << 12) | ||
139 | |||
140 | /* CONTROL_SMART1NOPMIO_PADCONF_1 */ | ||
141 | #define OMAP4_FREF_DR0_LB_SHIFT 30 | ||
142 | #define OMAP4_FREF_DR0_LB_MASK (0x3 << 30) | ||
143 | #define OMAP4_FREF_DR1_LB_SHIFT 28 | ||
144 | #define OMAP4_FREF_DR1_LB_MASK (0x3 << 28) | ||
145 | #define OMAP4_FREF_DR4_LB_SHIFT 26 | ||
146 | #define OMAP4_FREF_DR4_LB_MASK (0x3 << 26) | ||
147 | #define OMAP4_FREF_DR5_LB_SHIFT 24 | ||
148 | #define OMAP4_FREF_DR5_LB_MASK (0x3 << 24) | ||
149 | #define OMAP4_FREF_DR6_LB_SHIFT 22 | ||
150 | #define OMAP4_FREF_DR6_LB_MASK (0x3 << 22) | ||
151 | #define OMAP4_FREF_DR7_LB_SHIFT 20 | ||
152 | #define OMAP4_FREF_DR7_LB_MASK (0x3 << 20) | ||
153 | #define OMAP4_GPIO_DR7_LB_SHIFT 18 | ||
154 | #define OMAP4_GPIO_DR7_LB_MASK (0x3 << 18) | ||
155 | #define OMAP4_DPM_DR0_LB_SHIFT 14 | ||
156 | #define OMAP4_DPM_DR0_LB_MASK (0x3 << 14) | ||
157 | #define OMAP4_SIM_DR0_LB_SHIFT 12 | ||
158 | #define OMAP4_SIM_DR0_LB_MASK (0x3 << 12) | ||
159 | |||
160 | /* CONTROL_PADCONF_MODE */ | ||
161 | #define OMAP4_VDDS_DV_FREF_SHIFT 31 | ||
162 | #define OMAP4_VDDS_DV_FREF_MASK (1 << 31) | ||
163 | #define OMAP4_VDDS_DV_BANK2_SHIFT 30 | ||
164 | #define OMAP4_VDDS_DV_BANK2_MASK (1 << 30) | ||
165 | |||
166 | /* CONTROL_XTAL_OSCILLATOR */ | ||
167 | #define OMAP4_OSCILLATOR_BOOST_SHIFT 31 | ||
168 | #define OMAP4_OSCILLATOR_BOOST_MASK (1 << 31) | ||
169 | #define OMAP4_OSCILLATOR_OS_OUT_SHIFT 30 | ||
170 | #define OMAP4_OSCILLATOR_OS_OUT_MASK (1 << 30) | ||
171 | |||
172 | /* CONTROL_USIMIO */ | ||
173 | #define OMAP4_PAD_USIM_CLK_LOW_SHIFT 31 | ||
174 | #define OMAP4_PAD_USIM_CLK_LOW_MASK (1 << 31) | ||
175 | #define OMAP4_PAD_USIM_RST_LOW_SHIFT 29 | ||
176 | #define OMAP4_PAD_USIM_RST_LOW_MASK (1 << 29) | ||
177 | #define OMAP4_USIM_PWRDNZ_SHIFT 28 | ||
178 | #define OMAP4_USIM_PWRDNZ_MASK (1 << 28) | ||
179 | |||
180 | /* CONTROL_I2C_2 */ | ||
181 | #define OMAP4_SR_SDA_GLFENB_SHIFT 31 | ||
182 | #define OMAP4_SR_SDA_GLFENB_MASK (1 << 31) | ||
183 | #define OMAP4_SR_SDA_LOAD_BITS_SHIFT 29 | ||
184 | #define OMAP4_SR_SDA_LOAD_BITS_MASK (0x3 << 29) | ||
185 | #define OMAP4_SR_SDA_PULLUPRESX_SHIFT 28 | ||
186 | #define OMAP4_SR_SDA_PULLUPRESX_MASK (1 << 28) | ||
187 | #define OMAP4_SR_SCL_GLFENB_SHIFT 27 | ||
188 | #define OMAP4_SR_SCL_GLFENB_MASK (1 << 27) | ||
189 | #define OMAP4_SR_SCL_LOAD_BITS_SHIFT 25 | ||
190 | #define OMAP4_SR_SCL_LOAD_BITS_MASK (0x3 << 25) | ||
191 | #define OMAP4_SR_SCL_PULLUPRESX_SHIFT 24 | ||
192 | #define OMAP4_SR_SCL_PULLUPRESX_MASK (1 << 24) | ||
193 | |||
194 | /* CONTROL_JTAG */ | ||
195 | #define OMAP4_JTAG_NTRST_EN_SHIFT 31 | ||
196 | #define OMAP4_JTAG_NTRST_EN_MASK (1 << 31) | ||
197 | #define OMAP4_JTAG_TCK_EN_SHIFT 30 | ||
198 | #define OMAP4_JTAG_TCK_EN_MASK (1 << 30) | ||
199 | #define OMAP4_JTAG_RTCK_EN_SHIFT 29 | ||
200 | #define OMAP4_JTAG_RTCK_EN_MASK (1 << 29) | ||
201 | #define OMAP4_JTAG_TDI_EN_SHIFT 28 | ||
202 | #define OMAP4_JTAG_TDI_EN_MASK (1 << 28) | ||
203 | #define OMAP4_JTAG_TDO_EN_SHIFT 27 | ||
204 | #define OMAP4_JTAG_TDO_EN_MASK (1 << 27) | ||
205 | |||
206 | /* CONTROL_SYS */ | ||
207 | #define OMAP4_SYS_NRESWARM_PIPU_SHIFT 31 | ||
208 | #define OMAP4_SYS_NRESWARM_PIPU_MASK (1 << 31) | ||
209 | |||
210 | /* WKUP_CONTROL_SPARE_RW */ | ||
211 | #define OMAP4_WKUP_CONTROL_SPARE_RW_SHIFT 0 | ||
212 | #define OMAP4_WKUP_CONTROL_SPARE_RW_MASK (0xffffffff << 0) | ||
213 | |||
214 | /* WKUP_CONTROL_SPARE_R */ | ||
215 | #define OMAP4_WKUP_CONTROL_SPARE_R_SHIFT 0 | ||
216 | #define OMAP4_WKUP_CONTROL_SPARE_R_MASK (0xffffffff << 0) | ||
217 | |||
218 | /* WKUP_CONTROL_SPARE_R_C0 */ | ||
219 | #define OMAP4_WKUP_CONTROL_SPARE_R_C0_SHIFT 31 | ||
220 | #define OMAP4_WKUP_CONTROL_SPARE_R_C0_MASK (1 << 31) | ||
221 | #define OMAP4_WKUP_CONTROL_SPARE_R_C1_SHIFT 30 | ||
222 | #define OMAP4_WKUP_CONTROL_SPARE_R_C1_MASK (1 << 30) | ||
223 | #define OMAP4_WKUP_CONTROL_SPARE_R_C2_SHIFT 29 | ||
224 | #define OMAP4_WKUP_CONTROL_SPARE_R_C2_MASK (1 << 29) | ||
225 | #define OMAP4_WKUP_CONTROL_SPARE_R_C3_SHIFT 28 | ||
226 | #define OMAP4_WKUP_CONTROL_SPARE_R_C3_MASK (1 << 28) | ||
227 | #define OMAP4_WKUP_CONTROL_SPARE_R_C4_SHIFT 27 | ||
228 | #define OMAP4_WKUP_CONTROL_SPARE_R_C4_MASK (1 << 27) | ||
229 | #define OMAP4_WKUP_CONTROL_SPARE_R_C5_SHIFT 26 | ||
230 | #define OMAP4_WKUP_CONTROL_SPARE_R_C5_MASK (1 << 26) | ||
231 | #define OMAP4_WKUP_CONTROL_SPARE_R_C6_SHIFT 25 | ||
232 | #define OMAP4_WKUP_CONTROL_SPARE_R_C6_MASK (1 << 25) | ||
233 | #define OMAP4_WKUP_CONTROL_SPARE_R_C7_SHIFT 24 | ||
234 | #define OMAP4_WKUP_CONTROL_SPARE_R_C7_MASK (1 << 24) | ||
235 | |||
236 | #endif | ||
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c index 6d7ba37e2257..cd5f3a0b97bd 100644 --- a/arch/arm/mach-omap2/dpll3xxx.c +++ b/arch/arm/mach-omap2/dpll3xxx.c | |||
@@ -28,11 +28,8 @@ | |||
28 | #include <linux/bitops.h> | 28 | #include <linux/bitops.h> |
29 | #include <linux/clkdev.h> | 29 | #include <linux/clkdev.h> |
30 | 30 | ||
31 | #include "soc.h" | ||
32 | #include "clockdomain.h" | 31 | #include "clockdomain.h" |
33 | #include "clock.h" | 32 | #include "clock.h" |
34 | #include "cm2xxx_3xxx.h" | ||
35 | #include "cm-regbits-34xx.h" | ||
36 | 33 | ||
37 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ | 34 | /* CM_AUTOIDLE_PLL*.AUTO_* bit values */ |
38 | #define DPLL_AUTOIDLE_DISABLE 0x0 | 35 | #define DPLL_AUTOIDLE_DISABLE 0x0 |
@@ -310,7 +307,7 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel) | |||
310 | * Set jitter correction. Jitter correction applicable for OMAP343X | 307 | * Set jitter correction. Jitter correction applicable for OMAP343X |
311 | * only since freqsel field is no longer present on other devices. | 308 | * only since freqsel field is no longer present on other devices. |
312 | */ | 309 | */ |
313 | if (cpu_is_omap343x()) { | 310 | if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { |
314 | v = omap2_clk_readl(clk, dd->control_reg); | 311 | v = omap2_clk_readl(clk, dd->control_reg); |
315 | v &= ~dd->freqsel_mask; | 312 | v &= ~dd->freqsel_mask; |
316 | v |= freqsel << __ffs(dd->freqsel_mask); | 313 | v |= freqsel << __ffs(dd->freqsel_mask); |
@@ -512,7 +509,7 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, | |||
512 | return -EINVAL; | 509 | return -EINVAL; |
513 | 510 | ||
514 | /* Freqsel is available only on OMAP343X devices */ | 511 | /* Freqsel is available only on OMAP343X devices */ |
515 | if (cpu_is_omap343x()) { | 512 | if (ti_clk_features.flags & TI_CLK_DPLL_HAS_FREQSEL) { |
516 | freqsel = _omap3_dpll_compute_freqsel(clk, | 513 | freqsel = _omap3_dpll_compute_freqsel(clk, |
517 | dd->last_rounded_n); | 514 | dd->last_rounded_n); |
518 | WARN_ON(!freqsel); | 515 | WARN_ON(!freqsel); |
diff --git a/arch/arm/mach-omap2/dpll44xx.c b/arch/arm/mach-omap2/dpll44xx.c index 52f9438b92f2..4613f1e86988 100644 --- a/arch/arm/mach-omap2/dpll44xx.c +++ b/arch/arm/mach-omap2/dpll44xx.c | |||
@@ -15,10 +15,7 @@ | |||
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | #include <linux/bitops.h> | 16 | #include <linux/bitops.h> |
17 | 17 | ||
18 | #include "soc.h" | ||
19 | #include "clock.h" | 18 | #include "clock.h" |
20 | #include "clock44xx.h" | ||
21 | #include "cm-regbits-44xx.h" | ||
22 | 19 | ||
23 | /* | 20 | /* |
24 | * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that | 21 | * Maximum DPLL input frequency (FINT) and output frequency (FOUT) that |
@@ -29,13 +26,23 @@ | |||
29 | #define OMAP4_DPLL_LP_FINT_MAX 1000000 | 26 | #define OMAP4_DPLL_LP_FINT_MAX 1000000 |
30 | #define OMAP4_DPLL_LP_FOUT_MAX 100000000 | 27 | #define OMAP4_DPLL_LP_FOUT_MAX 100000000 |
31 | 28 | ||
29 | /* | ||
30 | * Bitfield declarations | ||
31 | */ | ||
32 | #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8) | ||
33 | #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10) | ||
34 | #define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11) | ||
35 | |||
36 | /* Static rate multiplier for OMAP4 REGM4XEN clocks */ | ||
37 | #define OMAP4430_REGM4XEN_MULT 4 | ||
38 | |||
32 | /* Supported only on OMAP4 */ | 39 | /* Supported only on OMAP4 */ |
33 | int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) | 40 | int omap4_dpllmx_gatectrl_read(struct clk_hw_omap *clk) |
34 | { | 41 | { |
35 | u32 v; | 42 | u32 v; |
36 | u32 mask; | 43 | u32 mask; |
37 | 44 | ||
38 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | 45 | if (!clk || !clk->clksel_reg) |
39 | return -EINVAL; | 46 | return -EINVAL; |
40 | 47 | ||
41 | mask = clk->flags & CLOCK_CLKOUTX2 ? | 48 | mask = clk->flags & CLOCK_CLKOUTX2 ? |
@@ -54,7 +61,7 @@ void omap4_dpllmx_allow_gatectrl(struct clk_hw_omap *clk) | |||
54 | u32 v; | 61 | u32 v; |
55 | u32 mask; | 62 | u32 mask; |
56 | 63 | ||
57 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | 64 | if (!clk || !clk->clksel_reg) |
58 | return; | 65 | return; |
59 | 66 | ||
60 | mask = clk->flags & CLOCK_CLKOUTX2 ? | 67 | mask = clk->flags & CLOCK_CLKOUTX2 ? |
@@ -72,7 +79,7 @@ void omap4_dpllmx_deny_gatectrl(struct clk_hw_omap *clk) | |||
72 | u32 v; | 79 | u32 v; |
73 | u32 mask; | 80 | u32 mask; |
74 | 81 | ||
75 | if (!clk || !clk->clksel_reg || !cpu_is_omap44xx()) | 82 | if (!clk || !clk->clksel_reg) |
76 | return; | 83 | return; |
77 | 84 | ||
78 | mask = clk->flags & CLOCK_CLKOUTX2 ? | 85 | mask = clk->flags & CLOCK_CLKOUTX2 ? |
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c index 93914d220069..8897ad7035fd 100644 --- a/arch/arm/mach-omap2/gpmc-nand.c +++ b/arch/arm/mach-omap2/gpmc-nand.c | |||
@@ -24,25 +24,6 @@ | |||
24 | /* minimum size for IO mapping */ | 24 | /* minimum size for IO mapping */ |
25 | #define NAND_IO_SIZE 4 | 25 | #define NAND_IO_SIZE 4 |
26 | 26 | ||
27 | static struct resource gpmc_nand_resource[] = { | ||
28 | { | ||
29 | .flags = IORESOURCE_MEM, | ||
30 | }, | ||
31 | { | ||
32 | .flags = IORESOURCE_IRQ, | ||
33 | }, | ||
34 | { | ||
35 | .flags = IORESOURCE_IRQ, | ||
36 | }, | ||
37 | }; | ||
38 | |||
39 | static struct platform_device gpmc_nand_device = { | ||
40 | .name = "omap2-nand", | ||
41 | .id = 0, | ||
42 | .num_resources = ARRAY_SIZE(gpmc_nand_resource), | ||
43 | .resource = gpmc_nand_resource, | ||
44 | }; | ||
45 | |||
46 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) | 27 | static bool gpmc_hwecc_bch_capable(enum omap_ecc ecc_opt) |
47 | { | 28 | { |
48 | /* platforms which support all ECC schemes */ | 29 | /* platforms which support all ECC schemes */ |
@@ -95,43 +76,41 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, | |||
95 | { | 76 | { |
96 | int err = 0; | 77 | int err = 0; |
97 | struct gpmc_settings s; | 78 | struct gpmc_settings s; |
98 | struct device *dev = &gpmc_nand_device.dev; | 79 | struct platform_device *pdev; |
99 | 80 | struct resource gpmc_nand_res[] = { | |
100 | memset(&s, 0, sizeof(struct gpmc_settings)); | 81 | { .flags = IORESOURCE_MEM, }, |
82 | { .flags = IORESOURCE_IRQ, }, | ||
83 | { .flags = IORESOURCE_IRQ, }, | ||
84 | }; | ||
101 | 85 | ||
102 | gpmc_nand_device.dev.platform_data = gpmc_nand_data; | 86 | BUG_ON(gpmc_nand_data->cs >= GPMC_CS_NUM); |
103 | 87 | ||
104 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, | 88 | err = gpmc_cs_request(gpmc_nand_data->cs, NAND_IO_SIZE, |
105 | (unsigned long *)&gpmc_nand_resource[0].start); | 89 | (unsigned long *)&gpmc_nand_res[0].start); |
106 | if (err < 0) { | 90 | if (err < 0) { |
107 | dev_err(dev, "Cannot request GPMC CS %d, error %d\n", | 91 | pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n", |
108 | gpmc_nand_data->cs, err); | 92 | gpmc_nand_data->cs, err); |
109 | return err; | 93 | return err; |
110 | } | 94 | } |
111 | 95 | gpmc_nand_res[0].end = gpmc_nand_res[0].start + NAND_IO_SIZE - 1; | |
112 | gpmc_nand_resource[0].end = gpmc_nand_resource[0].start + | 96 | gpmc_nand_res[1].start = gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); |
113 | NAND_IO_SIZE - 1; | 97 | gpmc_nand_res[2].start = gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); |
114 | |||
115 | gpmc_nand_resource[1].start = | ||
116 | gpmc_get_client_irq(GPMC_IRQ_FIFOEVENTENABLE); | ||
117 | gpmc_nand_resource[2].start = | ||
118 | gpmc_get_client_irq(GPMC_IRQ_COUNT_EVENT); | ||
119 | 98 | ||
120 | if (gpmc_t) { | 99 | if (gpmc_t) { |
121 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); | 100 | err = gpmc_cs_set_timings(gpmc_nand_data->cs, gpmc_t); |
122 | if (err < 0) { | 101 | if (err < 0) { |
123 | dev_err(dev, "Unable to set gpmc timings: %d\n", err); | 102 | pr_err("omap2-gpmc: Unable to set gpmc timings: %d\n", err); |
124 | return err; | 103 | return err; |
125 | } | 104 | } |
126 | } | 105 | } |
127 | 106 | ||
107 | memset(&s, 0, sizeof(struct gpmc_settings)); | ||
128 | if (gpmc_nand_data->of_node) | 108 | if (gpmc_nand_data->of_node) |
129 | gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); | 109 | gpmc_read_settings_dt(gpmc_nand_data->of_node, &s); |
130 | else | 110 | else |
131 | gpmc_set_legacy(gpmc_nand_data, &s); | 111 | gpmc_set_legacy(gpmc_nand_data, &s); |
132 | 112 | ||
133 | s.device_nand = true; | 113 | s.device_nand = true; |
134 | |||
135 | err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); | 114 | err = gpmc_cs_program_settings(gpmc_nand_data->cs, &s); |
136 | if (err < 0) | 115 | if (err < 0) |
137 | goto out_free_cs; | 116 | goto out_free_cs; |
@@ -143,18 +122,34 @@ int gpmc_nand_init(struct omap_nand_platform_data *gpmc_nand_data, | |||
143 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); | 122 | gpmc_update_nand_reg(&gpmc_nand_data->reg, gpmc_nand_data->cs); |
144 | 123 | ||
145 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { | 124 | if (!gpmc_hwecc_bch_capable(gpmc_nand_data->ecc_opt)) { |
146 | dev_err(dev, "Unsupported NAND ECC scheme selected\n"); | 125 | pr_err("omap2-nand: Unsupported NAND ECC scheme selected\n"); |
147 | return -EINVAL; | 126 | err = -EINVAL; |
127 | goto out_free_cs; | ||
148 | } | 128 | } |
149 | 129 | ||
150 | err = platform_device_register(&gpmc_nand_device); | 130 | |
151 | if (err < 0) { | 131 | pdev = platform_device_alloc("omap2-nand", gpmc_nand_data->cs); |
152 | dev_err(dev, "Unable to register NAND device\n"); | 132 | if (pdev) { |
153 | goto out_free_cs; | 133 | err = platform_device_add_resources(pdev, gpmc_nand_res, |
134 | ARRAY_SIZE(gpmc_nand_res)); | ||
135 | if (!err) | ||
136 | pdev->dev.platform_data = gpmc_nand_data; | ||
137 | } else { | ||
138 | err = -ENOMEM; | ||
139 | } | ||
140 | if (err) | ||
141 | goto out_free_pdev; | ||
142 | |||
143 | err = platform_device_add(pdev); | ||
144 | if (err) { | ||
145 | dev_err(&pdev->dev, "Unable to register NAND device\n"); | ||
146 | goto out_free_pdev; | ||
154 | } | 147 | } |
155 | 148 | ||
156 | return 0; | 149 | return 0; |
157 | 150 | ||
151 | out_free_pdev: | ||
152 | platform_device_put(pdev); | ||
158 | out_free_cs: | 153 | out_free_cs: |
159 | gpmc_cs_free(gpmc_nand_data->cs); | 154 | gpmc_cs_free(gpmc_nand_data->cs); |
160 | 155 | ||
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c index 8f559450c876..1fae5c123f79 100644 --- a/arch/arm/mach-omap2/io.c +++ b/arch/arm/mach-omap2/io.c | |||
@@ -728,6 +728,8 @@ int __init omap_clk_init(void) | |||
728 | if (!omap_clk_soc_init) | 728 | if (!omap_clk_soc_init) |
729 | return 0; | 729 | return 0; |
730 | 730 | ||
731 | ti_clk_init_features(); | ||
732 | |||
731 | ret = of_prcm_init(); | 733 | ret = of_prcm_init(); |
732 | if (!ret) | 734 | if (!ret) |
733 | ret = omap_clk_soc_init(); | 735 | ret = omap_clk_soc_init(); |
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c index a5ea988ff340..d76694b7a591 100644 --- a/arch/arm/mach-omap2/pm24xx.c +++ b/arch/arm/mach-omap2/pm24xx.c | |||
@@ -75,9 +75,9 @@ static int omap2_enter_full_retention(void) | |||
75 | 75 | ||
76 | /* Clear old wake-up events */ | 76 | /* Clear old wake-up events */ |
77 | /* REVISIT: These write to reserved bits? */ | 77 | /* REVISIT: These write to reserved bits? */ |
78 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); | 78 | omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); |
79 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | 79 | omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); |
80 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | 80 | omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); |
81 | 81 | ||
82 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); | 82 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_RET); |
83 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); | 83 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
@@ -104,23 +104,18 @@ no_sleep: | |||
104 | clk_enable(osc_ck); | 104 | clk_enable(osc_ck); |
105 | 105 | ||
106 | /* clear CORE wake-up events */ | 106 | /* clear CORE wake-up events */ |
107 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); | 107 | omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); |
108 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | 108 | omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); |
109 | 109 | ||
110 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ | 110 | /* wakeup domain events - bit 1: GPT1, bit5 GPIO */ |
111 | omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD, PM_WKST); | 111 | omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, 0x4 | 0x1); |
112 | 112 | ||
113 | /* MPU domain wake events */ | 113 | /* MPU domain wake events */ |
114 | l = omap2_prm_read_mod_reg(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | 114 | omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, |
115 | if (l & 0x01) | 115 | 0x1); |
116 | omap2_prm_write_mod_reg(0x01, OCP_MOD, | ||
117 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | ||
118 | if (l & 0x20) | ||
119 | omap2_prm_write_mod_reg(0x20, OCP_MOD, | ||
120 | OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | ||
121 | 116 | ||
122 | /* Mask future PRCM-to-MPU interrupts */ | 117 | omap2xxx_prm_clear_mod_irqs(OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET, |
123 | omap2_prm_write_mod_reg(0x0, OCP_MOD, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET); | 118 | 0x20); |
124 | 119 | ||
125 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); | 120 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_ON); |
126 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); | 121 | pwrdm_set_next_pwrst(core_pwrdm, PWRDM_POWER_ON); |
@@ -148,9 +143,9 @@ static void omap2_enter_mpu_retention(void) | |||
148 | * it is in retention mode. */ | 143 | * it is in retention mode. */ |
149 | if (omap2_allow_mpu_retention()) { | 144 | if (omap2_allow_mpu_retention()) { |
150 | /* REVISIT: These write to reserved bits? */ | 145 | /* REVISIT: These write to reserved bits? */ |
151 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); | 146 | omap2xxx_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); |
152 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); | 147 | omap2xxx_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); |
153 | omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD, PM_WKST); | 148 | omap2xxx_prm_clear_mod_irqs(WKUP_MOD, PM_WKST, ~0); |
154 | 149 | ||
155 | /* Try to enter MPU retention */ | 150 | /* Try to enter MPU retention */ |
156 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); | 151 | pwrdm_set_next_pwrst(mpu_pwrdm, PWRDM_POWER_RET); |
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c index 507d8eeaab95..3f80929a5f7e 100644 --- a/arch/arm/mach-omap2/pm34xx.c +++ b/arch/arm/mach-omap2/pm34xx.c | |||
@@ -133,60 +133,13 @@ static void omap3_save_secure_ram_context(void) | |||
133 | } | 133 | } |
134 | } | 134 | } |
135 | 135 | ||
136 | /* | ||
137 | * PRCM Interrupt Handler Helper Function | ||
138 | * | ||
139 | * The purpose of this function is to clear any wake-up events latched | ||
140 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | ||
141 | * may occur whilst attempting to clear a PM_WKST_x register and thus | ||
142 | * set another bit in this register. A while loop is used to ensure | ||
143 | * that any peripheral wake-up events occurring while attempting to | ||
144 | * clear the PM_WKST_x are detected and cleared. | ||
145 | */ | ||
146 | static int prcm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) | ||
147 | { | ||
148 | u32 wkst, fclk, iclk, clken; | ||
149 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; | ||
150 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | ||
151 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | ||
152 | u16 grpsel_off = (regs == 3) ? | ||
153 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | ||
154 | int c = 0; | ||
155 | |||
156 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | ||
157 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); | ||
158 | wkst &= ~ignore_bits; | ||
159 | if (wkst) { | ||
160 | iclk = omap2_cm_read_mod_reg(module, iclk_off); | ||
161 | fclk = omap2_cm_read_mod_reg(module, fclk_off); | ||
162 | while (wkst) { | ||
163 | clken = wkst; | ||
164 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); | ||
165 | /* | ||
166 | * For USBHOST, we don't know whether HOST1 or | ||
167 | * HOST2 woke us up, so enable both f-clocks | ||
168 | */ | ||
169 | if (module == OMAP3430ES2_USBHOST_MOD) | ||
170 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | ||
171 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); | ||
172 | omap2_prm_write_mod_reg(wkst, module, wkst_off); | ||
173 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | ||
174 | wkst &= ~ignore_bits; | ||
175 | c++; | ||
176 | } | ||
177 | omap2_cm_write_mod_reg(iclk, module, iclk_off); | ||
178 | omap2_cm_write_mod_reg(fclk, module, fclk_off); | ||
179 | } | ||
180 | |||
181 | return c; | ||
182 | } | ||
183 | |||
184 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) | 136 | static irqreturn_t _prcm_int_handle_io(int irq, void *unused) |
185 | { | 137 | { |
186 | int c; | 138 | int c; |
187 | 139 | ||
188 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, | 140 | c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, |
189 | ~(OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK)); | 141 | ~(OMAP3430_ST_IO_MASK | |
142 | OMAP3430_ST_IO_CHAIN_MASK)); | ||
190 | 143 | ||
191 | return c ? IRQ_HANDLED : IRQ_NONE; | 144 | return c ? IRQ_HANDLED : IRQ_NONE; |
192 | } | 145 | } |
@@ -200,13 +153,14 @@ static irqreturn_t _prcm_int_handle_wakeup(int irq, void *unused) | |||
200 | * these are handled in a separate handler to avoid acking | 153 | * these are handled in a separate handler to avoid acking |
201 | * IO events before parsing in mux code | 154 | * IO events before parsing in mux code |
202 | */ | 155 | */ |
203 | c = prcm_clear_mod_irqs(WKUP_MOD, 1, | 156 | c = omap3xxx_prm_clear_mod_irqs(WKUP_MOD, 1, |
204 | OMAP3430_ST_IO_MASK | OMAP3430_ST_IO_CHAIN_MASK); | 157 | OMAP3430_ST_IO_MASK | |
205 | c += prcm_clear_mod_irqs(CORE_MOD, 1, 0); | 158 | OMAP3430_ST_IO_CHAIN_MASK); |
206 | c += prcm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); | 159 | c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 1, 0); |
160 | c += omap3xxx_prm_clear_mod_irqs(OMAP3430_PER_MOD, 1, 0); | ||
207 | if (omap_rev() > OMAP3430_REV_ES1_0) { | 161 | if (omap_rev() > OMAP3430_REV_ES1_0) { |
208 | c += prcm_clear_mod_irqs(CORE_MOD, 3, 0); | 162 | c += omap3xxx_prm_clear_mod_irqs(CORE_MOD, 3, 0); |
209 | c += prcm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); | 163 | c += omap3xxx_prm_clear_mod_irqs(OMAP3430ES2_USBHOST_MOD, 1, 0); |
210 | } | 164 | } |
211 | 165 | ||
212 | return c ? IRQ_HANDLED : IRQ_NONE; | 166 | return c ? IRQ_HANDLED : IRQ_NONE; |
@@ -399,159 +353,11 @@ restore: | |||
399 | #define omap3_pm_suspend NULL | 353 | #define omap3_pm_suspend NULL |
400 | #endif /* CONFIG_SUSPEND */ | 354 | #endif /* CONFIG_SUSPEND */ |
401 | 355 | ||
402 | |||
403 | /** | ||
404 | * omap3_iva_idle(): ensure IVA is in idle so it can be put into | ||
405 | * retention | ||
406 | * | ||
407 | * In cases where IVA2 is activated by bootcode, it may prevent | ||
408 | * full-chip retention or off-mode because it is not idle. This | ||
409 | * function forces the IVA2 into idle state so it can go | ||
410 | * into retention/off and thus allow full-chip retention/off. | ||
411 | * | ||
412 | **/ | ||
413 | static void __init omap3_iva_idle(void) | ||
414 | { | ||
415 | /* ensure IVA2 clock is disabled */ | ||
416 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
417 | |||
418 | /* if no clock activity, nothing else to do */ | ||
419 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & | ||
420 | OMAP3430_CLKACTIVITY_IVA2_MASK)) | ||
421 | return; | ||
422 | |||
423 | /* Reset IVA2 */ | ||
424 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | | ||
425 | OMAP3430_RST2_IVA2_MASK | | ||
426 | OMAP3430_RST3_IVA2_MASK, | ||
427 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | ||
428 | |||
429 | /* Enable IVA2 clock */ | ||
430 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, | ||
431 | OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
432 | |||
433 | /* Set IVA2 boot mode to 'idle' */ | ||
434 | omap3_ctrl_set_iva_bootmode_idle(); | ||
435 | |||
436 | /* Un-reset IVA2 */ | ||
437 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | ||
438 | |||
439 | /* Disable IVA2 clock */ | ||
440 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
441 | |||
442 | /* Reset IVA2 */ | ||
443 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | | ||
444 | OMAP3430_RST2_IVA2_MASK | | ||
445 | OMAP3430_RST3_IVA2_MASK, | ||
446 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | ||
447 | } | ||
448 | |||
449 | static void __init omap3_d2d_idle(void) | ||
450 | { | ||
451 | u16 mask, padconf; | ||
452 | |||
453 | /* In a stand alone OMAP3430 where there is not a stacked | ||
454 | * modem for the D2D Idle Ack and D2D MStandby must be pulled | ||
455 | * high. S CONTROL_PADCONF_SAD2D_IDLEACK and | ||
456 | * CONTROL_PADCONF_SAD2D_MSTDBY to have a pull up. */ | ||
457 | mask = (1 << 4) | (1 << 3); /* pull-up, enabled */ | ||
458 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_MSTANDBY); | ||
459 | padconf |= mask; | ||
460 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_MSTANDBY); | ||
461 | |||
462 | padconf = omap_ctrl_readw(OMAP3_PADCONF_SAD2D_IDLEACK); | ||
463 | padconf |= mask; | ||
464 | omap_ctrl_writew(padconf, OMAP3_PADCONF_SAD2D_IDLEACK); | ||
465 | |||
466 | /* reset modem */ | ||
467 | omap2_prm_write_mod_reg(OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | | ||
468 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, | ||
469 | CORE_MOD, OMAP2_RM_RSTCTRL); | ||
470 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); | ||
471 | } | ||
472 | |||
473 | static void __init prcm_setup_regs(void) | 356 | static void __init prcm_setup_regs(void) |
474 | { | 357 | { |
475 | u32 omap3630_en_uart4_mask = cpu_is_omap3630() ? | 358 | omap3_ctrl_init(); |
476 | OMAP3630_EN_UART4_MASK : 0; | ||
477 | u32 omap3630_grpsel_uart4_mask = cpu_is_omap3630() ? | ||
478 | OMAP3630_GRPSEL_UART4_MASK : 0; | ||
479 | |||
480 | /* XXX This should be handled by hwmod code or SCM init code */ | ||
481 | omap_ctrl_writel(OMAP3430_AUTOIDLE_MASK, OMAP2_CONTROL_SYSCONFIG); | ||
482 | |||
483 | /* | ||
484 | * Enable control of expternal oscillator through | ||
485 | * sys_clkreq. In the long run clock framework should | ||
486 | * take care of this. | ||
487 | */ | ||
488 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, | ||
489 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, | ||
490 | OMAP3430_GR_MOD, | ||
491 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | ||
492 | |||
493 | /* setup wakup source */ | ||
494 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | | ||
495 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, | ||
496 | WKUP_MOD, PM_WKEN); | ||
497 | /* No need to write EN_IO, that is always enabled */ | ||
498 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | | ||
499 | OMAP3430_GRPSEL_GPT1_MASK | | ||
500 | OMAP3430_GRPSEL_GPT12_MASK, | ||
501 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | ||
502 | |||
503 | /* Enable PM_WKEN to support DSS LPR */ | ||
504 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, | ||
505 | OMAP3430_DSS_MOD, PM_WKEN); | ||
506 | |||
507 | /* Enable wakeups in PER */ | ||
508 | omap2_prm_write_mod_reg(omap3630_en_uart4_mask | | ||
509 | OMAP3430_EN_GPIO2_MASK | OMAP3430_EN_GPIO3_MASK | | ||
510 | OMAP3430_EN_GPIO4_MASK | OMAP3430_EN_GPIO5_MASK | | ||
511 | OMAP3430_EN_GPIO6_MASK | OMAP3430_EN_UART3_MASK | | ||
512 | OMAP3430_EN_MCBSP2_MASK | OMAP3430_EN_MCBSP3_MASK | | ||
513 | OMAP3430_EN_MCBSP4_MASK, | ||
514 | OMAP3430_PER_MOD, PM_WKEN); | ||
515 | /* and allow them to wake up MPU */ | ||
516 | omap2_prm_write_mod_reg(omap3630_grpsel_uart4_mask | | ||
517 | OMAP3430_GRPSEL_GPIO2_MASK | | ||
518 | OMAP3430_GRPSEL_GPIO3_MASK | | ||
519 | OMAP3430_GRPSEL_GPIO4_MASK | | ||
520 | OMAP3430_GRPSEL_GPIO5_MASK | | ||
521 | OMAP3430_GRPSEL_GPIO6_MASK | | ||
522 | OMAP3430_GRPSEL_UART3_MASK | | ||
523 | OMAP3430_GRPSEL_MCBSP2_MASK | | ||
524 | OMAP3430_GRPSEL_MCBSP3_MASK | | ||
525 | OMAP3430_GRPSEL_MCBSP4_MASK, | ||
526 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | ||
527 | |||
528 | /* Don't attach IVA interrupts */ | ||
529 | if (omap3_has_iva()) { | ||
530 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | ||
531 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | ||
532 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | ||
533 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, | ||
534 | OMAP3430_PM_IVAGRPSEL); | ||
535 | } | ||
536 | |||
537 | /* Clear any pending 'reset' flags */ | ||
538 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); | ||
539 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | ||
540 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | ||
541 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | ||
542 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | ||
543 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | ||
544 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, OMAP2_RM_RSTST); | ||
545 | |||
546 | /* Clear any pending PRCM interrupts */ | ||
547 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | ||
548 | |||
549 | /* | ||
550 | * We need to idle iva2_pwrdm even on am3703 with no iva2. | ||
551 | */ | ||
552 | omap3_iva_idle(); | ||
553 | 359 | ||
554 | omap3_d2d_idle(); | 360 | omap3_prm_init_pm(cpu_is_omap3630(), omap3_has_iva()); |
555 | } | 361 | } |
556 | 362 | ||
557 | void omap3_pm_off_mode_enable(int enable) | 363 | void omap3_pm_off_mode_enable(int enable) |
diff --git a/arch/arm/mach-omap2/prm2xxx.c b/arch/arm/mach-omap2/prm2xxx.c index a3a3cca2bcc4..86958050547a 100644 --- a/arch/arm/mach-omap2/prm2xxx.c +++ b/arch/arm/mach-omap2/prm2xxx.c | |||
@@ -114,6 +114,24 @@ void omap2xxx_prm_dpll_reset(void) | |||
114 | omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); | 114 | omap2_prm_read_mod_reg(WKUP_MOD, OMAP2_RM_RSTCTRL); |
115 | } | 115 | } |
116 | 116 | ||
117 | /** | ||
118 | * omap2xxx_prm_clear_mod_irqs - clear wakeup status bits for a module | ||
119 | * @module: PRM module to clear wakeups from | ||
120 | * @regs: register offset to clear | ||
121 | * @wkst_mask: wakeup status mask to clear | ||
122 | * | ||
123 | * Clears wakeup status bits for a given module, so that the device can | ||
124 | * re-enter idle. | ||
125 | */ | ||
126 | void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask) | ||
127 | { | ||
128 | u32 wkst; | ||
129 | |||
130 | wkst = omap2_prm_read_mod_reg(module, regs); | ||
131 | wkst &= wkst_mask; | ||
132 | omap2_prm_write_mod_reg(wkst, module, regs); | ||
133 | } | ||
134 | |||
117 | int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) | 135 | int omap2xxx_clkdm_sleep(struct clockdomain *clkdm) |
118 | { | 136 | { |
119 | omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, | 137 | omap2_prm_set_mod_reg_bits(OMAP24XX_FORCESTATE_MASK, |
diff --git a/arch/arm/mach-omap2/prm2xxx.h b/arch/arm/mach-omap2/prm2xxx.h index d2cb6365716f..d73414139292 100644 --- a/arch/arm/mach-omap2/prm2xxx.h +++ b/arch/arm/mach-omap2/prm2xxx.h | |||
@@ -125,6 +125,7 @@ extern int omap2xxx_clkdm_sleep(struct clockdomain *clkdm); | |||
125 | extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); | 125 | extern int omap2xxx_clkdm_wakeup(struct clockdomain *clkdm); |
126 | 126 | ||
127 | extern void omap2xxx_prm_dpll_reset(void); | 127 | extern void omap2xxx_prm_dpll_reset(void); |
128 | void omap2xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 wkst_mask); | ||
128 | 129 | ||
129 | extern int __init omap2xxx_prm_init(void); | 130 | extern int __init omap2xxx_prm_init(void); |
130 | 131 | ||
diff --git a/arch/arm/mach-omap2/prm3xxx.c b/arch/arm/mach-omap2/prm3xxx.c index 4bd7a2dca8af..2458be6fc67b 100644 --- a/arch/arm/mach-omap2/prm3xxx.c +++ b/arch/arm/mach-omap2/prm3xxx.c | |||
@@ -26,6 +26,8 @@ | |||
26 | #include "prm2xxx_3xxx.h" | 26 | #include "prm2xxx_3xxx.h" |
27 | #include "cm2xxx_3xxx.h" | 27 | #include "cm2xxx_3xxx.h" |
28 | #include "prm-regbits-34xx.h" | 28 | #include "prm-regbits-34xx.h" |
29 | #include "cm3xxx.h" | ||
30 | #include "cm-regbits-34xx.h" | ||
29 | 31 | ||
30 | static const struct omap_prcm_irq omap3_prcm_irqs[] = { | 32 | static const struct omap_prcm_irq omap3_prcm_irqs[] = { |
31 | OMAP_PRCM_IRQ("wkup", 0, 0), | 33 | OMAP_PRCM_IRQ("wkup", 0, 0), |
@@ -206,6 +208,167 @@ void omap3xxx_prm_restore_irqen(u32 *saved_mask) | |||
206 | } | 208 | } |
207 | 209 | ||
208 | /** | 210 | /** |
211 | * omap3xxx_prm_clear_mod_irqs - clear wake-up events from PRCM interrupt | ||
212 | * @module: PRM module to clear wakeups from | ||
213 | * @regs: register set to clear, 1 or 3 | ||
214 | * @ignore_bits: wakeup status bits to ignore | ||
215 | * | ||
216 | * The purpose of this function is to clear any wake-up events latched | ||
217 | * in the PRCM PM_WKST_x registers. It is possible that a wake-up event | ||
218 | * may occur whilst attempting to clear a PM_WKST_x register and thus | ||
219 | * set another bit in this register. A while loop is used to ensure | ||
220 | * that any peripheral wake-up events occurring while attempting to | ||
221 | * clear the PM_WKST_x are detected and cleared. | ||
222 | */ | ||
223 | int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits) | ||
224 | { | ||
225 | u32 wkst, fclk, iclk, clken; | ||
226 | u16 wkst_off = (regs == 3) ? OMAP3430ES2_PM_WKST3 : PM_WKST1; | ||
227 | u16 fclk_off = (regs == 3) ? OMAP3430ES2_CM_FCLKEN3 : CM_FCLKEN1; | ||
228 | u16 iclk_off = (regs == 3) ? CM_ICLKEN3 : CM_ICLKEN1; | ||
229 | u16 grpsel_off = (regs == 3) ? | ||
230 | OMAP3430ES2_PM_MPUGRPSEL3 : OMAP3430_PM_MPUGRPSEL; | ||
231 | int c = 0; | ||
232 | |||
233 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | ||
234 | wkst &= omap2_prm_read_mod_reg(module, grpsel_off); | ||
235 | wkst &= ~ignore_bits; | ||
236 | if (wkst) { | ||
237 | iclk = omap2_cm_read_mod_reg(module, iclk_off); | ||
238 | fclk = omap2_cm_read_mod_reg(module, fclk_off); | ||
239 | while (wkst) { | ||
240 | clken = wkst; | ||
241 | omap2_cm_set_mod_reg_bits(clken, module, iclk_off); | ||
242 | /* | ||
243 | * For USBHOST, we don't know whether HOST1 or | ||
244 | * HOST2 woke us up, so enable both f-clocks | ||
245 | */ | ||
246 | if (module == OMAP3430ES2_USBHOST_MOD) | ||
247 | clken |= 1 << OMAP3430ES2_EN_USBHOST2_SHIFT; | ||
248 | omap2_cm_set_mod_reg_bits(clken, module, fclk_off); | ||
249 | omap2_prm_write_mod_reg(wkst, module, wkst_off); | ||
250 | wkst = omap2_prm_read_mod_reg(module, wkst_off); | ||
251 | wkst &= ~ignore_bits; | ||
252 | c++; | ||
253 | } | ||
254 | omap2_cm_write_mod_reg(iclk, module, iclk_off); | ||
255 | omap2_cm_write_mod_reg(fclk, module, fclk_off); | ||
256 | } | ||
257 | |||
258 | return c; | ||
259 | } | ||
260 | |||
261 | /** | ||
262 | * omap3_prm_reset_modem - toggle reset signal for modem | ||
263 | * | ||
264 | * Toggles the reset signal to modem IP block. Required to allow | ||
265 | * OMAP3430 without stacked modem to idle properly. | ||
266 | */ | ||
267 | void __init omap3_prm_reset_modem(void) | ||
268 | { | ||
269 | omap2_prm_write_mod_reg( | ||
270 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RSTPWRON_MASK | | ||
271 | OMAP3430_RM_RSTCTRL_CORE_MODEM_SW_RST_MASK, | ||
272 | CORE_MOD, OMAP2_RM_RSTCTRL); | ||
273 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); | ||
274 | } | ||
275 | |||
276 | /** | ||
277 | * omap3_prm_init_pm - initialize PM related registers for PRM | ||
278 | * @has_uart4: SoC has UART4 | ||
279 | * @has_iva: SoC has IVA | ||
280 | * | ||
281 | * Initializes PRM registers for PM use. Called from PM init. | ||
282 | */ | ||
283 | void __init omap3_prm_init_pm(bool has_uart4, bool has_iva) | ||
284 | { | ||
285 | u32 en_uart4_mask; | ||
286 | u32 grpsel_uart4_mask; | ||
287 | |||
288 | /* | ||
289 | * Enable control of expternal oscillator through | ||
290 | * sys_clkreq. In the long run clock framework should | ||
291 | * take care of this. | ||
292 | */ | ||
293 | omap2_prm_rmw_mod_reg_bits(OMAP_AUTOEXTCLKMODE_MASK, | ||
294 | 1 << OMAP_AUTOEXTCLKMODE_SHIFT, | ||
295 | OMAP3430_GR_MOD, | ||
296 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | ||
297 | |||
298 | /* setup wakup source */ | ||
299 | omap2_prm_write_mod_reg(OMAP3430_EN_IO_MASK | OMAP3430_EN_GPIO1_MASK | | ||
300 | OMAP3430_EN_GPT1_MASK | OMAP3430_EN_GPT12_MASK, | ||
301 | WKUP_MOD, PM_WKEN); | ||
302 | /* No need to write EN_IO, that is always enabled */ | ||
303 | omap2_prm_write_mod_reg(OMAP3430_GRPSEL_GPIO1_MASK | | ||
304 | OMAP3430_GRPSEL_GPT1_MASK | | ||
305 | OMAP3430_GRPSEL_GPT12_MASK, | ||
306 | WKUP_MOD, OMAP3430_PM_MPUGRPSEL); | ||
307 | |||
308 | /* Enable PM_WKEN to support DSS LPR */ | ||
309 | omap2_prm_write_mod_reg(OMAP3430_PM_WKEN_DSS_EN_DSS_MASK, | ||
310 | OMAP3430_DSS_MOD, PM_WKEN); | ||
311 | |||
312 | if (has_uart4) { | ||
313 | en_uart4_mask = OMAP3630_EN_UART4_MASK; | ||
314 | grpsel_uart4_mask = OMAP3630_GRPSEL_UART4_MASK; | ||
315 | } | ||
316 | |||
317 | /* Enable wakeups in PER */ | ||
318 | omap2_prm_write_mod_reg(en_uart4_mask | | ||
319 | OMAP3430_EN_GPIO2_MASK | | ||
320 | OMAP3430_EN_GPIO3_MASK | | ||
321 | OMAP3430_EN_GPIO4_MASK | | ||
322 | OMAP3430_EN_GPIO5_MASK | | ||
323 | OMAP3430_EN_GPIO6_MASK | | ||
324 | OMAP3430_EN_UART3_MASK | | ||
325 | OMAP3430_EN_MCBSP2_MASK | | ||
326 | OMAP3430_EN_MCBSP3_MASK | | ||
327 | OMAP3430_EN_MCBSP4_MASK, | ||
328 | OMAP3430_PER_MOD, PM_WKEN); | ||
329 | |||
330 | /* and allow them to wake up MPU */ | ||
331 | omap2_prm_write_mod_reg(grpsel_uart4_mask | | ||
332 | OMAP3430_GRPSEL_GPIO2_MASK | | ||
333 | OMAP3430_GRPSEL_GPIO3_MASK | | ||
334 | OMAP3430_GRPSEL_GPIO4_MASK | | ||
335 | OMAP3430_GRPSEL_GPIO5_MASK | | ||
336 | OMAP3430_GRPSEL_GPIO6_MASK | | ||
337 | OMAP3430_GRPSEL_UART3_MASK | | ||
338 | OMAP3430_GRPSEL_MCBSP2_MASK | | ||
339 | OMAP3430_GRPSEL_MCBSP3_MASK | | ||
340 | OMAP3430_GRPSEL_MCBSP4_MASK, | ||
341 | OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); | ||
342 | |||
343 | /* Don't attach IVA interrupts */ | ||
344 | if (has_iva) { | ||
345 | omap2_prm_write_mod_reg(0, WKUP_MOD, OMAP3430_PM_IVAGRPSEL); | ||
346 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); | ||
347 | omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); | ||
348 | omap2_prm_write_mod_reg(0, OMAP3430_PER_MOD, | ||
349 | OMAP3430_PM_IVAGRPSEL); | ||
350 | } | ||
351 | |||
352 | /* Clear any pending 'reset' flags */ | ||
353 | omap2_prm_write_mod_reg(0xffffffff, MPU_MOD, OMAP2_RM_RSTST); | ||
354 | omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); | ||
355 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_PER_MOD, OMAP2_RM_RSTST); | ||
356 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_EMU_MOD, OMAP2_RM_RSTST); | ||
357 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_NEON_MOD, OMAP2_RM_RSTST); | ||
358 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430_DSS_MOD, OMAP2_RM_RSTST); | ||
359 | omap2_prm_write_mod_reg(0xffffffff, OMAP3430ES2_USBHOST_MOD, | ||
360 | OMAP2_RM_RSTST); | ||
361 | |||
362 | /* Clear any pending PRCM interrupts */ | ||
363 | omap2_prm_write_mod_reg(0, OCP_MOD, OMAP3_PRM_IRQSTATUS_MPU_OFFSET); | ||
364 | |||
365 | /* We need to idle iva2_pwrdm even on am3703 with no iva2. */ | ||
366 | omap3xxx_prm_iva_idle(); | ||
367 | |||
368 | omap3_prm_reset_modem(); | ||
369 | } | ||
370 | |||
371 | /** | ||
209 | * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain | 372 | * omap3xxx_prm_reconfigure_io_chain - clear latches and reconfigure I/O chain |
210 | * | 373 | * |
211 | * Clear any previously-latched I/O wakeup events and ensure that the | 374 | * Clear any previously-latched I/O wakeup events and ensure that the |
@@ -276,6 +439,76 @@ static u32 omap3xxx_prm_read_reset_sources(void) | |||
276 | return r; | 439 | return r; |
277 | } | 440 | } |
278 | 441 | ||
442 | /** | ||
443 | * omap3xxx_prm_iva_idle - ensure IVA is in idle so it can be put into retention | ||
444 | * | ||
445 | * In cases where IVA2 is activated by bootcode, it may prevent | ||
446 | * full-chip retention or off-mode because it is not idle. This | ||
447 | * function forces the IVA2 into idle state so it can go | ||
448 | * into retention/off and thus allow full-chip retention/off. | ||
449 | */ | ||
450 | void omap3xxx_prm_iva_idle(void) | ||
451 | { | ||
452 | /* ensure IVA2 clock is disabled */ | ||
453 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
454 | |||
455 | /* if no clock activity, nothing else to do */ | ||
456 | if (!(omap2_cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKSTST) & | ||
457 | OMAP3430_CLKACTIVITY_IVA2_MASK)) | ||
458 | return; | ||
459 | |||
460 | /* Reset IVA2 */ | ||
461 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | | ||
462 | OMAP3430_RST2_IVA2_MASK | | ||
463 | OMAP3430_RST3_IVA2_MASK, | ||
464 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | ||
465 | |||
466 | /* Enable IVA2 clock */ | ||
467 | omap2_cm_write_mod_reg(OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK, | ||
468 | OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
469 | |||
470 | /* Un-reset IVA2 */ | ||
471 | omap2_prm_write_mod_reg(0, OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | ||
472 | |||
473 | /* Disable IVA2 clock */ | ||
474 | omap2_cm_write_mod_reg(0, OMAP3430_IVA2_MOD, CM_FCLKEN); | ||
475 | |||
476 | /* Reset IVA2 */ | ||
477 | omap2_prm_write_mod_reg(OMAP3430_RST1_IVA2_MASK | | ||
478 | OMAP3430_RST2_IVA2_MASK | | ||
479 | OMAP3430_RST3_IVA2_MASK, | ||
480 | OMAP3430_IVA2_MOD, OMAP2_RM_RSTCTRL); | ||
481 | } | ||
482 | |||
483 | /** | ||
484 | * omap3xxx_prm_clear_global_cold_reset - checks the global cold reset status | ||
485 | * and clears it if asserted | ||
486 | * | ||
487 | * Checks if cold-reset has occurred and clears the status bit if yes. Returns | ||
488 | * 1 if cold-reset has occurred, 0 otherwise. | ||
489 | */ | ||
490 | int omap3xxx_prm_clear_global_cold_reset(void) | ||
491 | { | ||
492 | if (omap2_prm_read_mod_reg(OMAP3430_GR_MOD, OMAP3_PRM_RSTST_OFFSET) & | ||
493 | OMAP3430_GLOBAL_COLD_RST_MASK) { | ||
494 | omap2_prm_set_mod_reg_bits(OMAP3430_GLOBAL_COLD_RST_MASK, | ||
495 | OMAP3430_GR_MOD, | ||
496 | OMAP3_PRM_RSTST_OFFSET); | ||
497 | return 1; | ||
498 | } | ||
499 | |||
500 | return 0; | ||
501 | } | ||
502 | |||
503 | void omap3_prm_save_scratchpad_contents(u32 *ptr) | ||
504 | { | ||
505 | *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, | ||
506 | OMAP3_PRM_CLKSRC_CTRL_OFFSET); | ||
507 | |||
508 | *ptr++ = omap2_prm_read_mod_reg(OMAP3430_GR_MOD, | ||
509 | OMAP3_PRM_CLKSEL_OFFSET); | ||
510 | } | ||
511 | |||
279 | /* Powerdomain low-level functions */ | 512 | /* Powerdomain low-level functions */ |
280 | 513 | ||
281 | static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) | 514 | static int omap3_pwrdm_set_next_pwrst(struct powerdomain *pwrdm, u8 pwrst) |
diff --git a/arch/arm/mach-omap2/prm3xxx.h b/arch/arm/mach-omap2/prm3xxx.h index 1dacfc5b1959..bc37d42a8704 100644 --- a/arch/arm/mach-omap2/prm3xxx.h +++ b/arch/arm/mach-omap2/prm3xxx.h | |||
@@ -162,6 +162,12 @@ extern void omap3xxx_prm_dpll3_reset(void); | |||
162 | 162 | ||
163 | extern int __init omap3xxx_prm_init(void); | 163 | extern int __init omap3xxx_prm_init(void); |
164 | extern u32 omap3xxx_prm_get_reset_sources(void); | 164 | extern u32 omap3xxx_prm_get_reset_sources(void); |
165 | int omap3xxx_prm_clear_mod_irqs(s16 module, u8 regs, u32 ignore_bits); | ||
166 | void omap3xxx_prm_iva_idle(void); | ||
167 | void omap3_prm_reset_modem(void); | ||
168 | int omap3xxx_prm_clear_global_cold_reset(void); | ||
169 | void omap3_prm_save_scratchpad_contents(u32 *ptr); | ||
170 | void omap3_prm_init_pm(bool has_uart4, bool has_iva); | ||
165 | 171 | ||
166 | #endif /* __ASSEMBLER */ | 172 | #endif /* __ASSEMBLER */ |
167 | 173 | ||
diff --git a/arch/arm/mach-omap2/usb-tusb6010.c b/arch/arm/mach-omap2/usb-tusb6010.c index e832bc7b8e2d..8333400898fb 100644 --- a/arch/arm/mach-omap2/usb-tusb6010.c +++ b/arch/arm/mach-omap2/usb-tusb6010.c | |||
@@ -95,7 +95,6 @@ static int tusb_set_sync_mode(unsigned sysclk_ps) | |||
95 | dev_t.t_avdp_w = t_scsnh_advnh; | 95 | dev_t.t_avdp_w = t_scsnh_advnh; |
96 | dev_t.cyc_aavdh_we = 3; | 96 | dev_t.cyc_aavdh_we = 3; |
97 | dev_t.cyc_wpl = 6; | 97 | dev_t.cyc_wpl = 6; |
98 | dev_t.t_ce_rdyz = 7000; | ||
99 | 98 | ||
100 | gpmc_calc_timings(&t, &tusb_sync, &dev_t); | 99 | gpmc_calc_timings(&t, &tusb_sync, &dev_t); |
101 | 100 | ||
diff --git a/arch/arm/mach-pxa/corgi.c b/arch/arm/mach-pxa/corgi.c index 91dd1c7cdbcd..06022b235730 100644 --- a/arch/arm/mach-pxa/corgi.c +++ b/arch/arm/mach-pxa/corgi.c | |||
@@ -514,7 +514,7 @@ static struct pxa2xx_udc_mach_info udc_info __initdata = { | |||
514 | .gpio_pullup = CORGI_GPIO_USB_PULLUP, | 514 | .gpio_pullup = CORGI_GPIO_USB_PULLUP, |
515 | }; | 515 | }; |
516 | 516 | ||
517 | #if defined(CONFIG_SPI_PXA2XX) || defined(CONFIG_SPI_PXA2XX_MASTER) | 517 | #if IS_ENABLED(CONFIG_SPI_PXA2XX) |
518 | static struct pxa2xx_spi_master corgi_spi_info = { | 518 | static struct pxa2xx_spi_master corgi_spi_info = { |
519 | .num_chipselect = 3, | 519 | .num_chipselect = 3, |
520 | }; | 520 | }; |
diff --git a/arch/arm/mach-pxa/generic.c b/arch/arm/mach-pxa/generic.c index 6f38e1af45af..630fa916bbc6 100644 --- a/arch/arm/mach-pxa/generic.c +++ b/arch/arm/mach-pxa/generic.c | |||
@@ -90,19 +90,15 @@ EXPORT_SYMBOL(get_clk_frequency_khz); | |||
90 | */ | 90 | */ |
91 | static struct map_desc common_io_desc[] __initdata = { | 91 | static struct map_desc common_io_desc[] __initdata = { |
92 | { /* Devs */ | 92 | { /* Devs */ |
93 | .virtual = 0xf2000000, | 93 | .virtual = (unsigned long)PERIPH_VIRT, |
94 | .pfn = __phys_to_pfn(0x40000000), | 94 | .pfn = __phys_to_pfn(PERIPH_PHYS), |
95 | .length = 0x02000000, | 95 | .length = PERIPH_SIZE, |
96 | .type = MT_DEVICE | ||
97 | }, { /* UNCACHED_PHYS_0 */ | ||
98 | .virtual = 0xff000000, | ||
99 | .pfn = __phys_to_pfn(0x00000000), | ||
100 | .length = 0x00100000, | ||
101 | .type = MT_DEVICE | 96 | .type = MT_DEVICE |
102 | } | 97 | } |
103 | }; | 98 | }; |
104 | 99 | ||
105 | void __init pxa_map_io(void) | 100 | void __init pxa_map_io(void) |
106 | { | 101 | { |
102 | debug_ll_io_init(); | ||
107 | iotable_init(ARRAY_AND_SIZE(common_io_desc)); | 103 | iotable_init(ARRAY_AND_SIZE(common_io_desc)); |
108 | } | 104 | } |
diff --git a/arch/arm/mach-pxa/include/mach/hardware.h b/arch/arm/mach-pxa/include/mach/hardware.h index ccb06e485520..8d63c211b22f 100644 --- a/arch/arm/mach-pxa/include/mach/hardware.h +++ b/arch/arm/mach-pxa/include/mach/hardware.h | |||
@@ -19,8 +19,8 @@ | |||
19 | * Workarounds for at least 2 errata so far require this. | 19 | * Workarounds for at least 2 errata so far require this. |
20 | * The mapping is set in mach-pxa/generic.c. | 20 | * The mapping is set in mach-pxa/generic.c. |
21 | */ | 21 | */ |
22 | #define UNCACHED_PHYS_0 0xff000000 | 22 | #define UNCACHED_PHYS_0 0xfe000000 |
23 | #define UNCACHED_ADDR UNCACHED_PHYS_0 | 23 | #define UNCACHED_PHYS_0_SIZE 0x00100000 |
24 | 24 | ||
25 | /* | 25 | /* |
26 | * Intel PXA2xx internal register mapping: | 26 | * Intel PXA2xx internal register mapping: |
diff --git a/arch/arm/mach-pxa/pxa25x.c b/arch/arm/mach-pxa/pxa25x.c index f2c28972084d..66e4a2b6316e 100644 --- a/arch/arm/mach-pxa/pxa25x.c +++ b/arch/arm/mach-pxa/pxa25x.c | |||
@@ -331,7 +331,12 @@ static struct map_desc pxa25x_io_desc[] __initdata = { | |||
331 | { /* Mem Ctl */ | 331 | { /* Mem Ctl */ |
332 | .virtual = (unsigned long)SMEMC_VIRT, | 332 | .virtual = (unsigned long)SMEMC_VIRT, |
333 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), | 333 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), |
334 | .length = 0x00200000, | 334 | .length = SMEMC_SIZE, |
335 | .type = MT_DEVICE | ||
336 | }, { /* UNCACHED_PHYS_0 */ | ||
337 | .virtual = UNCACHED_PHYS_0, | ||
338 | .pfn = __phys_to_pfn(0x00000000), | ||
339 | .length = UNCACHED_PHYS_0_SIZE, | ||
335 | .type = MT_DEVICE | 340 | .type = MT_DEVICE |
336 | }, | 341 | }, |
337 | }; | 342 | }; |
diff --git a/arch/arm/mach-pxa/pxa27x.c b/arch/arm/mach-pxa/pxa27x.c index 301471a07a10..b040d7d14888 100644 --- a/arch/arm/mach-pxa/pxa27x.c +++ b/arch/arm/mach-pxa/pxa27x.c | |||
@@ -402,12 +402,12 @@ static struct map_desc pxa27x_io_desc[] __initdata = { | |||
402 | { /* Mem Ctl */ | 402 | { /* Mem Ctl */ |
403 | .virtual = (unsigned long)SMEMC_VIRT, | 403 | .virtual = (unsigned long)SMEMC_VIRT, |
404 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), | 404 | .pfn = __phys_to_pfn(PXA2XX_SMEMC_BASE), |
405 | .length = 0x00200000, | 405 | .length = SMEMC_SIZE, |
406 | .type = MT_DEVICE | 406 | .type = MT_DEVICE |
407 | }, { /* IMem ctl */ | 407 | }, { /* UNCACHED_PHYS_0 */ |
408 | .virtual = 0xfe000000, | 408 | .virtual = UNCACHED_PHYS_0, |
409 | .pfn = __phys_to_pfn(0x58000000), | 409 | .pfn = __phys_to_pfn(0x00000000), |
410 | .length = 0x00100000, | 410 | .length = UNCACHED_PHYS_0_SIZE, |
411 | .type = MT_DEVICE | 411 | .type = MT_DEVICE |
412 | }, | 412 | }, |
413 | }; | 413 | }; |
diff --git a/arch/arm/mach-pxa/pxa3xx.c b/arch/arm/mach-pxa/pxa3xx.c index 87011f3de69d..593ccd35ca97 100644 --- a/arch/arm/mach-pxa/pxa3xx.c +++ b/arch/arm/mach-pxa/pxa3xx.c | |||
@@ -416,7 +416,7 @@ static struct map_desc pxa3xx_io_desc[] __initdata = { | |||
416 | { /* Mem Ctl */ | 416 | { /* Mem Ctl */ |
417 | .virtual = (unsigned long)SMEMC_VIRT, | 417 | .virtual = (unsigned long)SMEMC_VIRT, |
418 | .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), | 418 | .pfn = __phys_to_pfn(PXA3XX_SMEMC_BASE), |
419 | .length = 0x00200000, | 419 | .length = SMEMC_SIZE, |
420 | .type = MT_DEVICE | 420 | .type = MT_DEVICE |
421 | } | 421 | } |
422 | }; | 422 | }; |
diff --git a/arch/arm/mach-pxa/sleep.S b/arch/arm/mach-pxa/sleep.S index 1e544be9905d..6c5b3ffd2cd3 100644 --- a/arch/arm/mach-pxa/sleep.S +++ b/arch/arm/mach-pxa/sleep.S | |||
@@ -157,7 +157,7 @@ pxa_cpu_do_suspend: | |||
157 | @ Do not reorder... | 157 | @ Do not reorder... |
158 | @ Intel PXA270 Specification Update notes problems performing | 158 | @ Intel PXA270 Specification Update notes problems performing |
159 | @ external accesses after SDRAM is put in self-refresh mode | 159 | @ external accesses after SDRAM is put in self-refresh mode |
160 | @ (see Errata 39 ...hangs when entering self-refresh mode) | 160 | @ (see Errata 38 ...hangs when entering self-refresh mode) |
161 | 161 | ||
162 | @ force address lines low by reading at physical address 0 | 162 | @ force address lines low by reading at physical address 0 |
163 | ldr r3, [r2] | 163 | ldr r3, [r2] |
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 8c1b39a0caa0..850e506926df 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c | |||
@@ -25,6 +25,7 @@ | |||
25 | #include <linux/interrupt.h> | 25 | #include <linux/interrupt.h> |
26 | #include <linux/amba/bus.h> | 26 | #include <linux/amba/bus.h> |
27 | #include <linux/amba/clcd.h> | 27 | #include <linux/amba/clcd.h> |
28 | #include <linux/platform_data/video-clcd-versatile.h> | ||
28 | #include <linux/io.h> | 29 | #include <linux/io.h> |
29 | #include <linux/smsc911x.h> | 30 | #include <linux/smsc911x.h> |
30 | #include <linux/ata_platform.h> | 31 | #include <linux/ata_platform.h> |
@@ -48,7 +49,6 @@ | |||
48 | #include <mach/irqs.h> | 49 | #include <mach/irqs.h> |
49 | #include <asm/hardware/timer-sp.h> | 50 | #include <asm/hardware/timer-sp.h> |
50 | 51 | ||
51 | #include <plat/clcd.h> | ||
52 | #include <plat/sched_clock.h> | 52 | #include <plat/sched_clock.h> |
53 | 53 | ||
54 | #include "core.h" | 54 | #include "core.h" |
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig deleted file mode 100644 index 26003e23796d..000000000000 --- a/arch/arm/mach-s5p64x0/Kconfig +++ /dev/null | |||
@@ -1,102 +0,0 @@ | |||
1 | # arch/arm/mach-s5p64x0/Kconfig | ||
2 | # | ||
3 | # Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | # http://www.samsung.com/ | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | if ARCH_S5P64X0 | ||
9 | |||
10 | config CPU_S5P6440 | ||
11 | bool | ||
12 | select ARM_AMBA | ||
13 | select PL330_DMA if DMADEVICES | ||
14 | select S5P_SLEEP if PM | ||
15 | select SAMSUNG_WAKEMASK if PM | ||
16 | help | ||
17 | Enable S5P6440 CPU support | ||
18 | |||
19 | config CPU_S5P6450 | ||
20 | bool | ||
21 | select ARM_AMBA | ||
22 | select PL330_DMA if DMADEVICES | ||
23 | select S5P_SLEEP if PM | ||
24 | select SAMSUNG_WAKEMASK if PM | ||
25 | help | ||
26 | Enable S5P6450 CPU support | ||
27 | |||
28 | config S5P64X0_SETUP_FB_24BPP | ||
29 | bool | ||
30 | help | ||
31 | Common setup code for S5P64X0 based boards with a LCD display | ||
32 | through RGB interface. | ||
33 | |||
34 | config S5P64X0_SETUP_I2C1 | ||
35 | bool | ||
36 | help | ||
37 | Common setup code for i2c bus 1. | ||
38 | |||
39 | config S5P64X0_SETUP_SPI | ||
40 | bool | ||
41 | help | ||
42 | Common setup code for SPI GPIO configurations | ||
43 | |||
44 | config S5P64X0_SETUP_SDHCI_GPIO | ||
45 | bool | ||
46 | help | ||
47 | Common setup code for SDHCI gpio. | ||
48 | |||
49 | # machine support | ||
50 | |||
51 | config MACH_SMDK6440 | ||
52 | bool "SMDK6440" | ||
53 | select CPU_S5P6440 | ||
54 | select S3C_DEV_FB | ||
55 | select S3C_DEV_HSMMC | ||
56 | select S3C_DEV_HSMMC1 | ||
57 | select S3C_DEV_HSMMC2 | ||
58 | select S3C_DEV_I2C1 | ||
59 | select S3C_DEV_RTC | ||
60 | select S3C_DEV_WDT | ||
61 | select S5P64X0_SETUP_FB_24BPP | ||
62 | select S5P64X0_SETUP_I2C1 | ||
63 | select S5P64X0_SETUP_SDHCI_GPIO | ||
64 | select SAMSUNG_DEV_ADC | ||
65 | select SAMSUNG_DEV_BACKLIGHT | ||
66 | select SAMSUNG_DEV_PWM | ||
67 | select SAMSUNG_DEV_TS | ||
68 | help | ||
69 | Machine support for the Samsung SMDK6440 | ||
70 | |||
71 | config MACH_SMDK6450 | ||
72 | bool "SMDK6450" | ||
73 | select CPU_S5P6450 | ||
74 | select S3C_DEV_FB | ||
75 | select S3C_DEV_HSMMC | ||
76 | select S3C_DEV_HSMMC1 | ||
77 | select S3C_DEV_HSMMC2 | ||
78 | select S3C_DEV_I2C1 | ||
79 | select S3C_DEV_RTC | ||
80 | select S3C_DEV_WDT | ||
81 | select S5P64X0_SETUP_FB_24BPP | ||
82 | select S5P64X0_SETUP_I2C1 | ||
83 | select S5P64X0_SETUP_SDHCI_GPIO | ||
84 | select SAMSUNG_DEV_ADC | ||
85 | select SAMSUNG_DEV_BACKLIGHT | ||
86 | select SAMSUNG_DEV_PWM | ||
87 | select SAMSUNG_DEV_TS | ||
88 | help | ||
89 | Machine support for the Samsung SMDK6450 | ||
90 | |||
91 | menu "Use 8-bit SDHCI bus width" | ||
92 | |||
93 | config S5P64X0_SD_CH1_8BIT | ||
94 | bool "SDHCI Channel 1 (Slot 1)" | ||
95 | depends on MACH_SMDK6450 || MACH_SMDK6440 | ||
96 | help | ||
97 | Support SDHCI Channel 1 8-bit bus. | ||
98 | If selected, Channel 2 is disabled. | ||
99 | |||
100 | endmenu | ||
101 | |||
102 | endif | ||
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile deleted file mode 100644 index 12bb951187a4..000000000000 --- a/arch/arm/mach-s5p64x0/Makefile +++ /dev/null | |||
@@ -1,36 +0,0 @@ | |||
1 | # arch/arm/mach-s5p64x0/Makefile | ||
2 | # | ||
3 | # Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | # http://www.samsung.com | ||
5 | # | ||
6 | # Licensed under GPLv2 | ||
7 | |||
8 | obj-y := | ||
9 | obj-m := | ||
10 | obj-n := | ||
11 | obj- := | ||
12 | |||
13 | # Core | ||
14 | |||
15 | obj-y += common.o clock.o | ||
16 | obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o | ||
17 | obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o | ||
18 | |||
19 | obj-$(CONFIG_PM) += pm.o irq-pm.o | ||
20 | |||
21 | obj-y += dma.o | ||
22 | |||
23 | # machine support | ||
24 | |||
25 | obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o | ||
26 | obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o | ||
27 | |||
28 | # device support | ||
29 | |||
30 | obj-y += dev-audio.o | ||
31 | |||
32 | obj-y += setup-i2c0.o | ||
33 | obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o | ||
34 | obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o | ||
35 | obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o | ||
36 | obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | ||
diff --git a/arch/arm/mach-s5p64x0/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot deleted file mode 100644 index 79ece4055b02..000000000000 --- a/arch/arm/mach-s5p64x0/Makefile.boot +++ /dev/null | |||
@@ -1,2 +0,0 @@ | |||
1 | zreladdr-y += 0x20008000 | ||
2 | params_phys-y := 0x20000100 | ||
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c deleted file mode 100644 index ae34a1d5e10a..000000000000 --- a/arch/arm/mach-s5p64x0/clock-s5p6440.c +++ /dev/null | |||
@@ -1,632 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P6440 - Clock support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/errno.h> | ||
18 | #include <linux/err.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/device.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | #include <mach/map.h> | ||
25 | #include <mach/regs-clock.h> | ||
26 | |||
27 | #include <plat/cpu-freq.h> | ||
28 | #include <plat/clock.h> | ||
29 | #include <plat/cpu.h> | ||
30 | #include <plat/pll.h> | ||
31 | #include <plat/s5p-clock.h> | ||
32 | #include <plat/clock-clksrc.h> | ||
33 | |||
34 | #include "clock.h" | ||
35 | #include "common.h" | ||
36 | |||
37 | static u32 epll_div[][5] = { | ||
38 | { 36000000, 0, 48, 1, 4 }, | ||
39 | { 48000000, 0, 32, 1, 3 }, | ||
40 | { 60000000, 0, 40, 1, 3 }, | ||
41 | { 72000000, 0, 48, 1, 3 }, | ||
42 | { 84000000, 0, 28, 1, 2 }, | ||
43 | { 96000000, 0, 32, 1, 2 }, | ||
44 | { 32768000, 45264, 43, 1, 4 }, | ||
45 | { 45158000, 6903, 30, 1, 3 }, | ||
46 | { 49152000, 50332, 32, 1, 3 }, | ||
47 | { 67738000, 10398, 45, 1, 3 }, | ||
48 | { 73728000, 9961, 49, 1, 3 } | ||
49 | }; | ||
50 | |||
51 | static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate) | ||
52 | { | ||
53 | unsigned int epll_con, epll_con_k; | ||
54 | unsigned int i; | ||
55 | |||
56 | if (clk->rate == rate) /* Return if nothing changed */ | ||
57 | return 0; | ||
58 | |||
59 | epll_con = __raw_readl(S5P64X0_EPLL_CON); | ||
60 | epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K); | ||
61 | |||
62 | epll_con_k &= ~(PLL90XX_KDIV_MASK); | ||
63 | epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK); | ||
64 | |||
65 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | ||
66 | if (epll_div[i][0] == rate) { | ||
67 | epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT); | ||
68 | epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) | | ||
69 | (epll_div[i][3] << PLL90XX_PDIV_SHIFT) | | ||
70 | (epll_div[i][4] << PLL90XX_SDIV_SHIFT); | ||
71 | break; | ||
72 | } | ||
73 | } | ||
74 | |||
75 | if (i == ARRAY_SIZE(epll_div)) { | ||
76 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | ||
77 | return -EINVAL; | ||
78 | } | ||
79 | |||
80 | __raw_writel(epll_con, S5P64X0_EPLL_CON); | ||
81 | __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K); | ||
82 | |||
83 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", | ||
84 | clk->rate, rate); | ||
85 | |||
86 | clk->rate = rate; | ||
87 | |||
88 | return 0; | ||
89 | } | ||
90 | |||
91 | static struct clk_ops s5p6440_epll_ops = { | ||
92 | .get_rate = s5p_epll_get_rate, | ||
93 | .set_rate = s5p6440_epll_set_rate, | ||
94 | }; | ||
95 | |||
96 | static struct clksrc_clk clk_hclk = { | ||
97 | .clk = { | ||
98 | .name = "clk_hclk", | ||
99 | .parent = &clk_armclk.clk, | ||
100 | }, | ||
101 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, | ||
102 | }; | ||
103 | |||
104 | static struct clksrc_clk clk_pclk = { | ||
105 | .clk = { | ||
106 | .name = "clk_pclk", | ||
107 | .parent = &clk_hclk.clk, | ||
108 | }, | ||
109 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, | ||
110 | }; | ||
111 | static struct clksrc_clk clk_hclk_low = { | ||
112 | .clk = { | ||
113 | .name = "clk_hclk_low", | ||
114 | }, | ||
115 | .sources = &clkset_hclk_low, | ||
116 | .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 }, | ||
117 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 }, | ||
118 | }; | ||
119 | |||
120 | static struct clksrc_clk clk_pclk_low = { | ||
121 | .clk = { | ||
122 | .name = "clk_pclk_low", | ||
123 | .parent = &clk_hclk_low.clk, | ||
124 | }, | ||
125 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, | ||
126 | }; | ||
127 | |||
128 | /* | ||
129 | * The following clocks will be disabled during clock initialization. It is | ||
130 | * recommended to keep the following clocks disabled until the driver requests | ||
131 | * for enabling the clock. | ||
132 | */ | ||
133 | static struct clk init_clocks_off[] = { | ||
134 | { | ||
135 | .name = "nand", | ||
136 | .parent = &clk_hclk.clk, | ||
137 | .enable = s5p64x0_mem_ctrl, | ||
138 | .ctrlbit = (1 << 2), | ||
139 | }, { | ||
140 | .name = "post", | ||
141 | .parent = &clk_hclk_low.clk, | ||
142 | .enable = s5p64x0_hclk0_ctrl, | ||
143 | .ctrlbit = (1 << 5) | ||
144 | }, { | ||
145 | .name = "2d", | ||
146 | .parent = &clk_hclk.clk, | ||
147 | .enable = s5p64x0_hclk0_ctrl, | ||
148 | .ctrlbit = (1 << 8), | ||
149 | }, { | ||
150 | .name = "dma", | ||
151 | .devname = "dma-pl330", | ||
152 | .parent = &clk_hclk_low.clk, | ||
153 | .enable = s5p64x0_hclk0_ctrl, | ||
154 | .ctrlbit = (1 << 12), | ||
155 | }, { | ||
156 | .name = "hsmmc", | ||
157 | .devname = "s3c-sdhci.0", | ||
158 | .parent = &clk_hclk_low.clk, | ||
159 | .enable = s5p64x0_hclk0_ctrl, | ||
160 | .ctrlbit = (1 << 17), | ||
161 | }, { | ||
162 | .name = "hsmmc", | ||
163 | .devname = "s3c-sdhci.1", | ||
164 | .parent = &clk_hclk_low.clk, | ||
165 | .enable = s5p64x0_hclk0_ctrl, | ||
166 | .ctrlbit = (1 << 18), | ||
167 | }, { | ||
168 | .name = "hsmmc", | ||
169 | .devname = "s3c-sdhci.2", | ||
170 | .parent = &clk_hclk_low.clk, | ||
171 | .enable = s5p64x0_hclk0_ctrl, | ||
172 | .ctrlbit = (1 << 19), | ||
173 | }, { | ||
174 | .name = "otg", | ||
175 | .parent = &clk_hclk_low.clk, | ||
176 | .enable = s5p64x0_hclk0_ctrl, | ||
177 | .ctrlbit = (1 << 20) | ||
178 | }, { | ||
179 | .name = "irom", | ||
180 | .parent = &clk_hclk.clk, | ||
181 | .enable = s5p64x0_hclk0_ctrl, | ||
182 | .ctrlbit = (1 << 25), | ||
183 | }, { | ||
184 | .name = "lcd", | ||
185 | .parent = &clk_hclk_low.clk, | ||
186 | .enable = s5p64x0_hclk1_ctrl, | ||
187 | .ctrlbit = (1 << 1), | ||
188 | }, { | ||
189 | .name = "hclk_fimgvg", | ||
190 | .parent = &clk_hclk.clk, | ||
191 | .enable = s5p64x0_hclk1_ctrl, | ||
192 | .ctrlbit = (1 << 2), | ||
193 | }, { | ||
194 | .name = "tsi", | ||
195 | .parent = &clk_hclk_low.clk, | ||
196 | .enable = s5p64x0_hclk1_ctrl, | ||
197 | .ctrlbit = (1 << 0), | ||
198 | }, { | ||
199 | .name = "watchdog", | ||
200 | .parent = &clk_pclk_low.clk, | ||
201 | .enable = s5p64x0_pclk_ctrl, | ||
202 | .ctrlbit = (1 << 5), | ||
203 | }, { | ||
204 | .name = "rtc", | ||
205 | .parent = &clk_pclk_low.clk, | ||
206 | .enable = s5p64x0_pclk_ctrl, | ||
207 | .ctrlbit = (1 << 6), | ||
208 | }, { | ||
209 | .name = "timers", | ||
210 | .parent = &clk_pclk_low.clk, | ||
211 | .enable = s5p64x0_pclk_ctrl, | ||
212 | .ctrlbit = (1 << 7), | ||
213 | }, { | ||
214 | .name = "pcm", | ||
215 | .parent = &clk_pclk_low.clk, | ||
216 | .enable = s5p64x0_pclk_ctrl, | ||
217 | .ctrlbit = (1 << 8), | ||
218 | }, { | ||
219 | .name = "adc", | ||
220 | .parent = &clk_pclk_low.clk, | ||
221 | .enable = s5p64x0_pclk_ctrl, | ||
222 | .ctrlbit = (1 << 12), | ||
223 | }, { | ||
224 | .name = "i2c", | ||
225 | .parent = &clk_pclk_low.clk, | ||
226 | .enable = s5p64x0_pclk_ctrl, | ||
227 | .ctrlbit = (1 << 17), | ||
228 | }, { | ||
229 | .name = "spi", | ||
230 | .devname = "s5p64x0-spi.0", | ||
231 | .parent = &clk_pclk_low.clk, | ||
232 | .enable = s5p64x0_pclk_ctrl, | ||
233 | .ctrlbit = (1 << 21), | ||
234 | }, { | ||
235 | .name = "spi", | ||
236 | .devname = "s5p64x0-spi.1", | ||
237 | .parent = &clk_pclk_low.clk, | ||
238 | .enable = s5p64x0_pclk_ctrl, | ||
239 | .ctrlbit = (1 << 22), | ||
240 | }, { | ||
241 | .name = "gps", | ||
242 | .parent = &clk_pclk_low.clk, | ||
243 | .enable = s5p64x0_pclk_ctrl, | ||
244 | .ctrlbit = (1 << 25), | ||
245 | }, { | ||
246 | .name = "dsim", | ||
247 | .parent = &clk_pclk_low.clk, | ||
248 | .enable = s5p64x0_pclk_ctrl, | ||
249 | .ctrlbit = (1 << 28), | ||
250 | }, { | ||
251 | .name = "etm", | ||
252 | .parent = &clk_pclk.clk, | ||
253 | .enable = s5p64x0_pclk_ctrl, | ||
254 | .ctrlbit = (1 << 29), | ||
255 | }, { | ||
256 | .name = "dmc0", | ||
257 | .parent = &clk_pclk.clk, | ||
258 | .enable = s5p64x0_pclk_ctrl, | ||
259 | .ctrlbit = (1 << 30), | ||
260 | }, { | ||
261 | .name = "pclk_fimgvg", | ||
262 | .parent = &clk_pclk.clk, | ||
263 | .enable = s5p64x0_pclk_ctrl, | ||
264 | .ctrlbit = (1 << 31), | ||
265 | }, { | ||
266 | .name = "mmc_48m", | ||
267 | .devname = "s3c-sdhci.0", | ||
268 | .parent = &clk_48m, | ||
269 | .enable = s5p64x0_sclk_ctrl, | ||
270 | .ctrlbit = (1 << 27), | ||
271 | }, { | ||
272 | .name = "mmc_48m", | ||
273 | .devname = "s3c-sdhci.1", | ||
274 | .parent = &clk_48m, | ||
275 | .enable = s5p64x0_sclk_ctrl, | ||
276 | .ctrlbit = (1 << 28), | ||
277 | }, { | ||
278 | .name = "mmc_48m", | ||
279 | .devname = "s3c-sdhci.2", | ||
280 | .parent = &clk_48m, | ||
281 | .enable = s5p64x0_sclk_ctrl, | ||
282 | .ctrlbit = (1 << 29), | ||
283 | }, | ||
284 | }; | ||
285 | |||
286 | /* | ||
287 | * The following clocks will be enabled during clock initialization. | ||
288 | */ | ||
289 | static struct clk init_clocks[] = { | ||
290 | { | ||
291 | .name = "intc", | ||
292 | .parent = &clk_hclk.clk, | ||
293 | .enable = s5p64x0_hclk0_ctrl, | ||
294 | .ctrlbit = (1 << 1), | ||
295 | }, { | ||
296 | .name = "mem", | ||
297 | .parent = &clk_hclk.clk, | ||
298 | .enable = s5p64x0_hclk0_ctrl, | ||
299 | .ctrlbit = (1 << 21), | ||
300 | }, { | ||
301 | .name = "uart", | ||
302 | .devname = "s3c6400-uart.0", | ||
303 | .parent = &clk_pclk_low.clk, | ||
304 | .enable = s5p64x0_pclk_ctrl, | ||
305 | .ctrlbit = (1 << 1), | ||
306 | }, { | ||
307 | .name = "uart", | ||
308 | .devname = "s3c6400-uart.1", | ||
309 | .parent = &clk_pclk_low.clk, | ||
310 | .enable = s5p64x0_pclk_ctrl, | ||
311 | .ctrlbit = (1 << 2), | ||
312 | }, { | ||
313 | .name = "uart", | ||
314 | .devname = "s3c6400-uart.2", | ||
315 | .parent = &clk_pclk_low.clk, | ||
316 | .enable = s5p64x0_pclk_ctrl, | ||
317 | .ctrlbit = (1 << 3), | ||
318 | }, { | ||
319 | .name = "uart", | ||
320 | .devname = "s3c6400-uart.3", | ||
321 | .parent = &clk_pclk_low.clk, | ||
322 | .enable = s5p64x0_pclk_ctrl, | ||
323 | .ctrlbit = (1 << 4), | ||
324 | }, { | ||
325 | .name = "gpio", | ||
326 | .parent = &clk_pclk_low.clk, | ||
327 | .enable = s5p64x0_pclk_ctrl, | ||
328 | .ctrlbit = (1 << 18), | ||
329 | }, | ||
330 | }; | ||
331 | |||
332 | static struct clk clk_iis_cd_v40 = { | ||
333 | .name = "iis_cdclk_v40", | ||
334 | }; | ||
335 | |||
336 | static struct clk clk_pcm_cd = { | ||
337 | .name = "pcm_cdclk", | ||
338 | }; | ||
339 | |||
340 | static struct clk *clkset_group1_list[] = { | ||
341 | &clk_mout_epll.clk, | ||
342 | &clk_dout_mpll.clk, | ||
343 | &clk_fin_epll, | ||
344 | }; | ||
345 | |||
346 | static struct clksrc_sources clkset_group1 = { | ||
347 | .sources = clkset_group1_list, | ||
348 | .nr_sources = ARRAY_SIZE(clkset_group1_list), | ||
349 | }; | ||
350 | |||
351 | static struct clk *clkset_uart_list[] = { | ||
352 | &clk_mout_epll.clk, | ||
353 | &clk_dout_mpll.clk, | ||
354 | }; | ||
355 | |||
356 | static struct clksrc_sources clkset_uart = { | ||
357 | .sources = clkset_uart_list, | ||
358 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
359 | }; | ||
360 | |||
361 | static struct clk *clkset_audio_list[] = { | ||
362 | &clk_mout_epll.clk, | ||
363 | &clk_dout_mpll.clk, | ||
364 | &clk_fin_epll, | ||
365 | &clk_iis_cd_v40, | ||
366 | &clk_pcm_cd, | ||
367 | }; | ||
368 | |||
369 | static struct clksrc_sources clkset_audio = { | ||
370 | .sources = clkset_audio_list, | ||
371 | .nr_sources = ARRAY_SIZE(clkset_audio_list), | ||
372 | }; | ||
373 | |||
374 | static struct clksrc_clk clksrcs[] = { | ||
375 | { | ||
376 | .clk = { | ||
377 | .name = "sclk_post", | ||
378 | .ctrlbit = (1 << 10), | ||
379 | .enable = s5p64x0_sclk_ctrl, | ||
380 | }, | ||
381 | .sources = &clkset_group1, | ||
382 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 }, | ||
383 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 }, | ||
384 | }, { | ||
385 | .clk = { | ||
386 | .name = "sclk_dispcon", | ||
387 | .ctrlbit = (1 << 1), | ||
388 | .enable = s5p64x0_sclk1_ctrl, | ||
389 | }, | ||
390 | .sources = &clkset_group1, | ||
391 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 }, | ||
392 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 }, | ||
393 | }, { | ||
394 | .clk = { | ||
395 | .name = "sclk_fimgvg", | ||
396 | .ctrlbit = (1 << 2), | ||
397 | .enable = s5p64x0_sclk1_ctrl, | ||
398 | }, | ||
399 | .sources = &clkset_group1, | ||
400 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 }, | ||
401 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 }, | ||
402 | }, | ||
403 | }; | ||
404 | |||
405 | static struct clksrc_clk clk_sclk_mmc0 = { | ||
406 | .clk = { | ||
407 | .name = "sclk_mmc", | ||
408 | .devname = "s3c-sdhci.0", | ||
409 | .ctrlbit = (1 << 24), | ||
410 | .enable = s5p64x0_sclk_ctrl, | ||
411 | }, | ||
412 | .sources = &clkset_group1, | ||
413 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, | ||
414 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, | ||
415 | }; | ||
416 | |||
417 | static struct clksrc_clk clk_sclk_mmc1 = { | ||
418 | .clk = { | ||
419 | .name = "sclk_mmc", | ||
420 | .devname = "s3c-sdhci.1", | ||
421 | .ctrlbit = (1 << 25), | ||
422 | .enable = s5p64x0_sclk_ctrl, | ||
423 | }, | ||
424 | .sources = &clkset_group1, | ||
425 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, | ||
426 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, | ||
427 | }; | ||
428 | |||
429 | static struct clksrc_clk clk_sclk_mmc2 = { | ||
430 | .clk = { | ||
431 | .name = "sclk_mmc", | ||
432 | .devname = "s3c-sdhci.2", | ||
433 | .ctrlbit = (1 << 26), | ||
434 | .enable = s5p64x0_sclk_ctrl, | ||
435 | }, | ||
436 | .sources = &clkset_group1, | ||
437 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, | ||
438 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, | ||
439 | }; | ||
440 | |||
441 | static struct clksrc_clk clk_sclk_uclk = { | ||
442 | .clk = { | ||
443 | .name = "uclk1", | ||
444 | .ctrlbit = (1 << 5), | ||
445 | .enable = s5p64x0_sclk_ctrl, | ||
446 | }, | ||
447 | .sources = &clkset_uart, | ||
448 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, | ||
449 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, | ||
450 | }; | ||
451 | |||
452 | static struct clk clk_i2s0 = { | ||
453 | .name = "iis", | ||
454 | .devname = "samsung-i2s.0", | ||
455 | .parent = &clk_pclk_low.clk, | ||
456 | .enable = s5p64x0_pclk_ctrl, | ||
457 | .ctrlbit = (1 << 26), | ||
458 | }; | ||
459 | |||
460 | static struct clksrc_clk clk_audio_bus2 = { | ||
461 | .clk = { | ||
462 | .name = "sclk_audio2", | ||
463 | .devname = "samsung-i2s.0", | ||
464 | .ctrlbit = (1 << 11), | ||
465 | .enable = s5p64x0_sclk_ctrl, | ||
466 | }, | ||
467 | .sources = &clkset_audio, | ||
468 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 }, | ||
469 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 }, | ||
470 | }; | ||
471 | |||
472 | static struct clksrc_clk clk_sclk_spi0 = { | ||
473 | .clk = { | ||
474 | .name = "sclk_spi", | ||
475 | .devname = "s5p64x0-spi.0", | ||
476 | .ctrlbit = (1 << 20), | ||
477 | .enable = s5p64x0_sclk_ctrl, | ||
478 | }, | ||
479 | .sources = &clkset_group1, | ||
480 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, | ||
481 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, | ||
482 | }; | ||
483 | |||
484 | static struct clksrc_clk clk_sclk_spi1 = { | ||
485 | .clk = { | ||
486 | .name = "sclk_spi", | ||
487 | .devname = "s5p64x0-spi.1", | ||
488 | .ctrlbit = (1 << 21), | ||
489 | .enable = s5p64x0_sclk_ctrl, | ||
490 | }, | ||
491 | .sources = &clkset_group1, | ||
492 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, | ||
493 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, | ||
494 | }; | ||
495 | |||
496 | /* Clock initialization code */ | ||
497 | static struct clksrc_clk *sysclks[] = { | ||
498 | &clk_mout_apll, | ||
499 | &clk_mout_epll, | ||
500 | &clk_mout_mpll, | ||
501 | &clk_dout_mpll, | ||
502 | &clk_armclk, | ||
503 | &clk_hclk, | ||
504 | &clk_pclk, | ||
505 | &clk_hclk_low, | ||
506 | &clk_pclk_low, | ||
507 | }; | ||
508 | |||
509 | static struct clk dummy_apb_pclk = { | ||
510 | .name = "apb_pclk", | ||
511 | .id = -1, | ||
512 | }; | ||
513 | |||
514 | static struct clk *clk_cdev[] = { | ||
515 | &clk_i2s0, | ||
516 | }; | ||
517 | |||
518 | static struct clksrc_clk *clksrc_cdev[] = { | ||
519 | &clk_sclk_uclk, | ||
520 | &clk_sclk_spi0, | ||
521 | &clk_sclk_spi1, | ||
522 | &clk_sclk_mmc0, | ||
523 | &clk_sclk_mmc1, | ||
524 | &clk_sclk_mmc2, | ||
525 | &clk_audio_bus2, | ||
526 | }; | ||
527 | |||
528 | static struct clk_lookup s5p6440_clk_lookup[] = { | ||
529 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), | ||
530 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), | ||
531 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | ||
532 | CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), | ||
533 | CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), | ||
534 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | ||
535 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | ||
536 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | ||
537 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0), | ||
538 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus2.clk), | ||
539 | }; | ||
540 | |||
541 | void __init_or_cpufreq s5p6440_setup_clocks(void) | ||
542 | { | ||
543 | struct clk *xtal_clk; | ||
544 | |||
545 | unsigned long xtal; | ||
546 | unsigned long fclk; | ||
547 | unsigned long hclk; | ||
548 | unsigned long hclk_low; | ||
549 | unsigned long pclk; | ||
550 | unsigned long pclk_low; | ||
551 | |||
552 | unsigned long apll; | ||
553 | unsigned long mpll; | ||
554 | unsigned long epll; | ||
555 | unsigned int ptr; | ||
556 | |||
557 | /* Set S5P6440 functions for clk_fout_epll */ | ||
558 | |||
559 | clk_fout_epll.enable = s5p_epll_enable; | ||
560 | clk_fout_epll.ops = &s5p6440_epll_ops; | ||
561 | |||
562 | clk_48m.enable = s5p64x0_clk48m_ctrl; | ||
563 | |||
564 | xtal_clk = clk_get(NULL, "ext_xtal"); | ||
565 | BUG_ON(IS_ERR(xtal_clk)); | ||
566 | |||
567 | xtal = clk_get_rate(xtal_clk); | ||
568 | clk_put(xtal_clk); | ||
569 | |||
570 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502); | ||
571 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502); | ||
572 | epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON), | ||
573 | __raw_readl(S5P64X0_EPLL_CON_K)); | ||
574 | |||
575 | clk_fout_apll.rate = apll; | ||
576 | clk_fout_mpll.rate = mpll; | ||
577 | clk_fout_epll.rate = epll; | ||
578 | |||
579 | printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ | ||
580 | " E=%ld.%ldMHz\n", | ||
581 | print_mhz(apll), print_mhz(mpll), print_mhz(epll)); | ||
582 | |||
583 | fclk = clk_get_rate(&clk_armclk.clk); | ||
584 | hclk = clk_get_rate(&clk_hclk.clk); | ||
585 | pclk = clk_get_rate(&clk_pclk.clk); | ||
586 | hclk_low = clk_get_rate(&clk_hclk_low.clk); | ||
587 | pclk_low = clk_get_rate(&clk_pclk_low.clk); | ||
588 | |||
589 | printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ | ||
590 | " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", | ||
591 | print_mhz(hclk), print_mhz(hclk_low), | ||
592 | print_mhz(pclk), print_mhz(pclk_low)); | ||
593 | |||
594 | clk_f.rate = fclk; | ||
595 | clk_h.rate = hclk; | ||
596 | clk_p.rate = pclk; | ||
597 | |||
598 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
599 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
600 | } | ||
601 | |||
602 | static struct clk *clks[] __initdata = { | ||
603 | &clk_ext, | ||
604 | &clk_iis_cd_v40, | ||
605 | &clk_pcm_cd, | ||
606 | }; | ||
607 | |||
608 | void __init s5p6440_register_clocks(void) | ||
609 | { | ||
610 | int ptr; | ||
611 | unsigned int cnt; | ||
612 | |||
613 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
614 | |||
615 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | ||
616 | s3c_register_clksrc(sysclks[ptr], 1); | ||
617 | |||
618 | s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); | ||
619 | for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) | ||
620 | s3c_disable_clocks(clk_cdev[cnt], 1); | ||
621 | |||
622 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
623 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
624 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) | ||
625 | s3c_register_clksrc(clksrc_cdev[ptr], 1); | ||
626 | |||
627 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
628 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
629 | clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup)); | ||
630 | |||
631 | s3c24xx_register_clock(&dummy_apb_pclk); | ||
632 | } | ||
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c deleted file mode 100644 index 0b3ca2ed53e9..000000000000 --- a/arch/arm/mach-s5p64x0/clock-s5p6450.c +++ /dev/null | |||
@@ -1,701 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P6450 - Clock support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/errno.h> | ||
18 | #include <linux/err.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/device.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | #include <mach/map.h> | ||
25 | #include <mach/regs-clock.h> | ||
26 | |||
27 | #include <plat/cpu-freq.h> | ||
28 | #include <plat/clock.h> | ||
29 | #include <plat/cpu.h> | ||
30 | #include <plat/pll.h> | ||
31 | #include <plat/s5p-clock.h> | ||
32 | #include <plat/clock-clksrc.h> | ||
33 | |||
34 | #include "clock.h" | ||
35 | #include "common.h" | ||
36 | |||
37 | static struct clksrc_clk clk_mout_dpll = { | ||
38 | .clk = { | ||
39 | .name = "mout_dpll", | ||
40 | }, | ||
41 | .sources = &clk_src_dpll, | ||
42 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 }, | ||
43 | }; | ||
44 | |||
45 | static u32 epll_div[][5] = { | ||
46 | { 133000000, 27307, 55, 2, 2 }, | ||
47 | { 100000000, 43691, 41, 2, 2 }, | ||
48 | { 480000000, 0, 80, 2, 0 }, | ||
49 | }; | ||
50 | |||
51 | static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate) | ||
52 | { | ||
53 | unsigned int epll_con, epll_con_k; | ||
54 | unsigned int i; | ||
55 | |||
56 | if (clk->rate == rate) /* Return if nothing changed */ | ||
57 | return 0; | ||
58 | |||
59 | epll_con = __raw_readl(S5P64X0_EPLL_CON); | ||
60 | epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K); | ||
61 | |||
62 | epll_con_k &= ~(PLL90XX_KDIV_MASK); | ||
63 | epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK); | ||
64 | |||
65 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | ||
66 | if (epll_div[i][0] == rate) { | ||
67 | epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT); | ||
68 | epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) | | ||
69 | (epll_div[i][3] << PLL90XX_PDIV_SHIFT) | | ||
70 | (epll_div[i][4] << PLL90XX_SDIV_SHIFT); | ||
71 | break; | ||
72 | } | ||
73 | } | ||
74 | |||
75 | if (i == ARRAY_SIZE(epll_div)) { | ||
76 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | ||
77 | return -EINVAL; | ||
78 | } | ||
79 | |||
80 | __raw_writel(epll_con, S5P64X0_EPLL_CON); | ||
81 | __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K); | ||
82 | |||
83 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", | ||
84 | clk->rate, rate); | ||
85 | |||
86 | clk->rate = rate; | ||
87 | |||
88 | return 0; | ||
89 | } | ||
90 | |||
91 | static struct clk_ops s5p6450_epll_ops = { | ||
92 | .get_rate = s5p_epll_get_rate, | ||
93 | .set_rate = s5p6450_epll_set_rate, | ||
94 | }; | ||
95 | |||
96 | static struct clksrc_clk clk_dout_epll = { | ||
97 | .clk = { | ||
98 | .name = "dout_epll", | ||
99 | .parent = &clk_mout_epll.clk, | ||
100 | }, | ||
101 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 }, | ||
102 | }; | ||
103 | |||
104 | static struct clksrc_clk clk_mout_hclk_sel = { | ||
105 | .clk = { | ||
106 | .name = "mout_hclk_sel", | ||
107 | }, | ||
108 | .sources = &clkset_hclk_low, | ||
109 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 }, | ||
110 | }; | ||
111 | |||
112 | static struct clk *clkset_hclk_list[] = { | ||
113 | &clk_mout_hclk_sel.clk, | ||
114 | &clk_armclk.clk, | ||
115 | }; | ||
116 | |||
117 | static struct clksrc_sources clkset_hclk = { | ||
118 | .sources = clkset_hclk_list, | ||
119 | .nr_sources = ARRAY_SIZE(clkset_hclk_list), | ||
120 | }; | ||
121 | |||
122 | static struct clksrc_clk clk_hclk = { | ||
123 | .clk = { | ||
124 | .name = "clk_hclk", | ||
125 | }, | ||
126 | .sources = &clkset_hclk, | ||
127 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 }, | ||
128 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 }, | ||
129 | }; | ||
130 | |||
131 | static struct clksrc_clk clk_pclk = { | ||
132 | .clk = { | ||
133 | .name = "clk_pclk", | ||
134 | .parent = &clk_hclk.clk, | ||
135 | }, | ||
136 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 }, | ||
137 | }; | ||
138 | static struct clksrc_clk clk_dout_pwm_ratio0 = { | ||
139 | .clk = { | ||
140 | .name = "clk_dout_pwm_ratio0", | ||
141 | .parent = &clk_mout_hclk_sel.clk, | ||
142 | }, | ||
143 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 }, | ||
144 | }; | ||
145 | |||
146 | static struct clksrc_clk clk_pclk_to_wdt_pwm = { | ||
147 | .clk = { | ||
148 | .name = "clk_pclk_to_wdt_pwm", | ||
149 | .parent = &clk_dout_pwm_ratio0.clk, | ||
150 | }, | ||
151 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 }, | ||
152 | }; | ||
153 | |||
154 | static struct clksrc_clk clk_hclk_low = { | ||
155 | .clk = { | ||
156 | .name = "clk_hclk_low", | ||
157 | }, | ||
158 | .sources = &clkset_hclk_low, | ||
159 | .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 }, | ||
160 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 }, | ||
161 | }; | ||
162 | |||
163 | static struct clksrc_clk clk_pclk_low = { | ||
164 | .clk = { | ||
165 | .name = "clk_pclk_low", | ||
166 | .parent = &clk_hclk_low.clk, | ||
167 | }, | ||
168 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 }, | ||
169 | }; | ||
170 | |||
171 | /* | ||
172 | * The following clocks will be disabled during clock initialization. It is | ||
173 | * recommended to keep the following clocks disabled until the driver requests | ||
174 | * for enabling the clock. | ||
175 | */ | ||
176 | static struct clk init_clocks_off[] = { | ||
177 | { | ||
178 | .name = "usbhost", | ||
179 | .parent = &clk_hclk_low.clk, | ||
180 | .enable = s5p64x0_hclk0_ctrl, | ||
181 | .ctrlbit = (1 << 3), | ||
182 | }, { | ||
183 | .name = "dma", | ||
184 | .devname = "dma-pl330", | ||
185 | .parent = &clk_hclk_low.clk, | ||
186 | .enable = s5p64x0_hclk0_ctrl, | ||
187 | .ctrlbit = (1 << 12), | ||
188 | }, { | ||
189 | .name = "hsmmc", | ||
190 | .devname = "s3c-sdhci.0", | ||
191 | .parent = &clk_hclk_low.clk, | ||
192 | .enable = s5p64x0_hclk0_ctrl, | ||
193 | .ctrlbit = (1 << 17), | ||
194 | }, { | ||
195 | .name = "hsmmc", | ||
196 | .devname = "s3c-sdhci.1", | ||
197 | .parent = &clk_hclk_low.clk, | ||
198 | .enable = s5p64x0_hclk0_ctrl, | ||
199 | .ctrlbit = (1 << 18), | ||
200 | }, { | ||
201 | .name = "hsmmc", | ||
202 | .devname = "s3c-sdhci.2", | ||
203 | .parent = &clk_hclk_low.clk, | ||
204 | .enable = s5p64x0_hclk0_ctrl, | ||
205 | .ctrlbit = (1 << 19), | ||
206 | }, { | ||
207 | .name = "usbotg", | ||
208 | .parent = &clk_hclk_low.clk, | ||
209 | .enable = s5p64x0_hclk0_ctrl, | ||
210 | .ctrlbit = (1 << 20), | ||
211 | }, { | ||
212 | .name = "lcd", | ||
213 | .parent = &clk_h, | ||
214 | .enable = s5p64x0_hclk1_ctrl, | ||
215 | .ctrlbit = (1 << 1), | ||
216 | }, { | ||
217 | .name = "watchdog", | ||
218 | .parent = &clk_pclk_low.clk, | ||
219 | .enable = s5p64x0_pclk_ctrl, | ||
220 | .ctrlbit = (1 << 5), | ||
221 | }, { | ||
222 | .name = "rtc", | ||
223 | .parent = &clk_pclk_low.clk, | ||
224 | .enable = s5p64x0_pclk_ctrl, | ||
225 | .ctrlbit = (1 << 6), | ||
226 | }, { | ||
227 | .name = "adc", | ||
228 | .parent = &clk_pclk_low.clk, | ||
229 | .enable = s5p64x0_pclk_ctrl, | ||
230 | .ctrlbit = (1 << 12), | ||
231 | }, { | ||
232 | .name = "i2c", | ||
233 | .devname = "s3c2440-i2c.0", | ||
234 | .parent = &clk_pclk_low.clk, | ||
235 | .enable = s5p64x0_pclk_ctrl, | ||
236 | .ctrlbit = (1 << 17), | ||
237 | }, { | ||
238 | .name = "spi", | ||
239 | .devname = "s5p64x0-spi.0", | ||
240 | .parent = &clk_pclk_low.clk, | ||
241 | .enable = s5p64x0_pclk_ctrl, | ||
242 | .ctrlbit = (1 << 21), | ||
243 | }, { | ||
244 | .name = "spi", | ||
245 | .devname = "s5p64x0-spi.1", | ||
246 | .parent = &clk_pclk_low.clk, | ||
247 | .enable = s5p64x0_pclk_ctrl, | ||
248 | .ctrlbit = (1 << 22), | ||
249 | }, { | ||
250 | .name = "i2c", | ||
251 | .devname = "s3c2440-i2c.1", | ||
252 | .parent = &clk_pclk_low.clk, | ||
253 | .enable = s5p64x0_pclk_ctrl, | ||
254 | .ctrlbit = (1 << 27), | ||
255 | }, { | ||
256 | .name = "dmc0", | ||
257 | .parent = &clk_pclk.clk, | ||
258 | .enable = s5p64x0_pclk_ctrl, | ||
259 | .ctrlbit = (1 << 30), | ||
260 | } | ||
261 | }; | ||
262 | |||
263 | /* | ||
264 | * The following clocks will be enabled during clock initialization. | ||
265 | */ | ||
266 | static struct clk init_clocks[] = { | ||
267 | { | ||
268 | .name = "intc", | ||
269 | .parent = &clk_hclk.clk, | ||
270 | .enable = s5p64x0_hclk0_ctrl, | ||
271 | .ctrlbit = (1 << 1), | ||
272 | }, { | ||
273 | .name = "mem", | ||
274 | .parent = &clk_hclk.clk, | ||
275 | .enable = s5p64x0_hclk0_ctrl, | ||
276 | .ctrlbit = (1 << 21), | ||
277 | }, { | ||
278 | .name = "uart", | ||
279 | .devname = "s3c6400-uart.0", | ||
280 | .parent = &clk_pclk_low.clk, | ||
281 | .enable = s5p64x0_pclk_ctrl, | ||
282 | .ctrlbit = (1 << 1), | ||
283 | }, { | ||
284 | .name = "uart", | ||
285 | .devname = "s3c6400-uart.1", | ||
286 | .parent = &clk_pclk_low.clk, | ||
287 | .enable = s5p64x0_pclk_ctrl, | ||
288 | .ctrlbit = (1 << 2), | ||
289 | }, { | ||
290 | .name = "uart", | ||
291 | .devname = "s3c6400-uart.2", | ||
292 | .parent = &clk_pclk_low.clk, | ||
293 | .enable = s5p64x0_pclk_ctrl, | ||
294 | .ctrlbit = (1 << 3), | ||
295 | }, { | ||
296 | .name = "uart", | ||
297 | .devname = "s3c6400-uart.3", | ||
298 | .parent = &clk_pclk_low.clk, | ||
299 | .enable = s5p64x0_pclk_ctrl, | ||
300 | .ctrlbit = (1 << 4), | ||
301 | }, { | ||
302 | .name = "timers", | ||
303 | .parent = &clk_pclk_to_wdt_pwm.clk, | ||
304 | .enable = s5p64x0_pclk_ctrl, | ||
305 | .ctrlbit = (1 << 7), | ||
306 | }, { | ||
307 | .name = "gpio", | ||
308 | .parent = &clk_pclk_low.clk, | ||
309 | .enable = s5p64x0_pclk_ctrl, | ||
310 | .ctrlbit = (1 << 18), | ||
311 | }, | ||
312 | }; | ||
313 | |||
314 | static struct clk *clkset_uart_list[] = { | ||
315 | &clk_dout_epll.clk, | ||
316 | &clk_dout_mpll.clk, | ||
317 | }; | ||
318 | |||
319 | static struct clksrc_sources clkset_uart = { | ||
320 | .sources = clkset_uart_list, | ||
321 | .nr_sources = ARRAY_SIZE(clkset_uart_list), | ||
322 | }; | ||
323 | |||
324 | static struct clk *clkset_mali_list[] = { | ||
325 | &clk_mout_epll.clk, | ||
326 | &clk_mout_apll.clk, | ||
327 | &clk_mout_mpll.clk, | ||
328 | }; | ||
329 | |||
330 | static struct clksrc_sources clkset_mali = { | ||
331 | .sources = clkset_mali_list, | ||
332 | .nr_sources = ARRAY_SIZE(clkset_mali_list), | ||
333 | }; | ||
334 | |||
335 | static struct clk *clkset_group2_list[] = { | ||
336 | &clk_dout_epll.clk, | ||
337 | &clk_dout_mpll.clk, | ||
338 | &clk_ext_xtal_mux, | ||
339 | }; | ||
340 | |||
341 | static struct clksrc_sources clkset_group2 = { | ||
342 | .sources = clkset_group2_list, | ||
343 | .nr_sources = ARRAY_SIZE(clkset_group2_list), | ||
344 | }; | ||
345 | |||
346 | static struct clk *clkset_dispcon_list[] = { | ||
347 | &clk_dout_epll.clk, | ||
348 | &clk_dout_mpll.clk, | ||
349 | &clk_ext_xtal_mux, | ||
350 | &clk_mout_dpll.clk, | ||
351 | }; | ||
352 | |||
353 | static struct clksrc_sources clkset_dispcon = { | ||
354 | .sources = clkset_dispcon_list, | ||
355 | .nr_sources = ARRAY_SIZE(clkset_dispcon_list), | ||
356 | }; | ||
357 | |||
358 | static struct clk *clkset_hsmmc44_list[] = { | ||
359 | &clk_dout_epll.clk, | ||
360 | &clk_dout_mpll.clk, | ||
361 | &clk_ext_xtal_mux, | ||
362 | &s5p_clk_27m, | ||
363 | &clk_48m, | ||
364 | }; | ||
365 | |||
366 | static struct clksrc_sources clkset_hsmmc44 = { | ||
367 | .sources = clkset_hsmmc44_list, | ||
368 | .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list), | ||
369 | }; | ||
370 | |||
371 | static struct clk *clkset_sclk_audio0_list[] = { | ||
372 | [0] = &clk_dout_epll.clk, | ||
373 | [1] = &clk_dout_mpll.clk, | ||
374 | [2] = &clk_ext_xtal_mux, | ||
375 | [3] = NULL, | ||
376 | [4] = NULL, | ||
377 | }; | ||
378 | |||
379 | static struct clksrc_sources clkset_sclk_audio0 = { | ||
380 | .sources = clkset_sclk_audio0_list, | ||
381 | .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list), | ||
382 | }; | ||
383 | |||
384 | static struct clksrc_clk clk_sclk_audio0 = { | ||
385 | .clk = { | ||
386 | .name = "audio-bus", | ||
387 | .devname = "samsung-i2s.0", | ||
388 | .enable = s5p64x0_sclk_ctrl, | ||
389 | .ctrlbit = (1 << 8), | ||
390 | .parent = &clk_dout_epll.clk, | ||
391 | }, | ||
392 | .sources = &clkset_sclk_audio0, | ||
393 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 }, | ||
394 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 }, | ||
395 | }; | ||
396 | |||
397 | static struct clksrc_clk clksrcs[] = { | ||
398 | { | ||
399 | .clk = { | ||
400 | .name = "sclk_fimc", | ||
401 | .ctrlbit = (1 << 10), | ||
402 | .enable = s5p64x0_sclk_ctrl, | ||
403 | }, | ||
404 | .sources = &clkset_group2, | ||
405 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 }, | ||
406 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 }, | ||
407 | }, { | ||
408 | .clk = { | ||
409 | .name = "aclk_mali", | ||
410 | .ctrlbit = (1 << 2), | ||
411 | .enable = s5p64x0_sclk1_ctrl, | ||
412 | }, | ||
413 | .sources = &clkset_mali, | ||
414 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 }, | ||
415 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 }, | ||
416 | }, { | ||
417 | .clk = { | ||
418 | .name = "sclk_2d", | ||
419 | .ctrlbit = (1 << 12), | ||
420 | .enable = s5p64x0_sclk_ctrl, | ||
421 | }, | ||
422 | .sources = &clkset_mali, | ||
423 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 }, | ||
424 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 }, | ||
425 | }, { | ||
426 | .clk = { | ||
427 | .name = "sclk_usi", | ||
428 | .ctrlbit = (1 << 7), | ||
429 | .enable = s5p64x0_sclk_ctrl, | ||
430 | }, | ||
431 | .sources = &clkset_group2, | ||
432 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 }, | ||
433 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 }, | ||
434 | }, { | ||
435 | .clk = { | ||
436 | .name = "sclk_camif", | ||
437 | .ctrlbit = (1 << 6), | ||
438 | .enable = s5p64x0_sclk_ctrl, | ||
439 | }, | ||
440 | .sources = &clkset_group2, | ||
441 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 }, | ||
442 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 }, | ||
443 | }, { | ||
444 | .clk = { | ||
445 | .name = "sclk_dispcon", | ||
446 | .ctrlbit = (1 << 1), | ||
447 | .enable = s5p64x0_sclk1_ctrl, | ||
448 | }, | ||
449 | .sources = &clkset_dispcon, | ||
450 | .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 }, | ||
451 | .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 }, | ||
452 | }, { | ||
453 | .clk = { | ||
454 | .name = "sclk_hsmmc44", | ||
455 | .ctrlbit = (1 << 30), | ||
456 | .enable = s5p64x0_sclk_ctrl, | ||
457 | }, | ||
458 | .sources = &clkset_hsmmc44, | ||
459 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 }, | ||
460 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 }, | ||
461 | }, | ||
462 | }; | ||
463 | |||
464 | static struct clksrc_clk clk_sclk_mmc0 = { | ||
465 | .clk = { | ||
466 | .name = "sclk_mmc", | ||
467 | .devname = "s3c-sdhci.0", | ||
468 | .ctrlbit = (1 << 24), | ||
469 | .enable = s5p64x0_sclk_ctrl, | ||
470 | }, | ||
471 | .sources = &clkset_group2, | ||
472 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 }, | ||
473 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 }, | ||
474 | }; | ||
475 | |||
476 | static struct clksrc_clk clk_sclk_mmc1 = { | ||
477 | .clk = { | ||
478 | .name = "sclk_mmc", | ||
479 | .devname = "s3c-sdhci.1", | ||
480 | .ctrlbit = (1 << 25), | ||
481 | .enable = s5p64x0_sclk_ctrl, | ||
482 | }, | ||
483 | .sources = &clkset_group2, | ||
484 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 }, | ||
485 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 }, | ||
486 | }; | ||
487 | |||
488 | static struct clksrc_clk clk_sclk_mmc2 = { | ||
489 | .clk = { | ||
490 | .name = "sclk_mmc", | ||
491 | .devname = "s3c-sdhci.2", | ||
492 | .ctrlbit = (1 << 26), | ||
493 | .enable = s5p64x0_sclk_ctrl, | ||
494 | }, | ||
495 | .sources = &clkset_group2, | ||
496 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 }, | ||
497 | .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 }, | ||
498 | }; | ||
499 | |||
500 | static struct clksrc_clk clk_sclk_uclk = { | ||
501 | .clk = { | ||
502 | .name = "uclk1", | ||
503 | .ctrlbit = (1 << 5), | ||
504 | .enable = s5p64x0_sclk_ctrl, | ||
505 | }, | ||
506 | .sources = &clkset_uart, | ||
507 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 }, | ||
508 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 }, | ||
509 | }; | ||
510 | |||
511 | static struct clksrc_clk clk_sclk_spi0 = { | ||
512 | .clk = { | ||
513 | .name = "sclk_spi", | ||
514 | .devname = "s5p64x0-spi.0", | ||
515 | .ctrlbit = (1 << 20), | ||
516 | .enable = s5p64x0_sclk_ctrl, | ||
517 | }, | ||
518 | .sources = &clkset_group2, | ||
519 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 }, | ||
520 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 }, | ||
521 | }; | ||
522 | |||
523 | static struct clksrc_clk clk_sclk_spi1 = { | ||
524 | .clk = { | ||
525 | .name = "sclk_spi", | ||
526 | .devname = "s5p64x0-spi.1", | ||
527 | .ctrlbit = (1 << 21), | ||
528 | .enable = s5p64x0_sclk_ctrl, | ||
529 | }, | ||
530 | .sources = &clkset_group2, | ||
531 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 }, | ||
532 | .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 }, | ||
533 | }; | ||
534 | |||
535 | static struct clk clk_i2s0 = { | ||
536 | .name = "iis", | ||
537 | .devname = "samsung-i2s.0", | ||
538 | .parent = &clk_pclk_low.clk, | ||
539 | .enable = s5p64x0_pclk_ctrl, | ||
540 | .ctrlbit = (1 << 26), | ||
541 | }; | ||
542 | |||
543 | static struct clk clk_i2s1 = { | ||
544 | .name = "iis", | ||
545 | .devname = "samsung-i2s.1", | ||
546 | .parent = &clk_pclk_low.clk, | ||
547 | .enable = s5p64x0_pclk_ctrl, | ||
548 | .ctrlbit = (1 << 15), | ||
549 | }; | ||
550 | |||
551 | static struct clk clk_i2s2 = { | ||
552 | .name = "iis", | ||
553 | .devname = "samsung-i2s.2", | ||
554 | .parent = &clk_pclk_low.clk, | ||
555 | .enable = s5p64x0_pclk_ctrl, | ||
556 | .ctrlbit = (1 << 16), | ||
557 | }; | ||
558 | |||
559 | static struct clk *clk_cdev[] = { | ||
560 | &clk_i2s0, | ||
561 | &clk_i2s1, | ||
562 | &clk_i2s2, | ||
563 | }; | ||
564 | |||
565 | static struct clksrc_clk *clksrc_cdev[] = { | ||
566 | &clk_sclk_uclk, | ||
567 | &clk_sclk_spi0, | ||
568 | &clk_sclk_spi1, | ||
569 | &clk_sclk_mmc0, | ||
570 | &clk_sclk_mmc1, | ||
571 | &clk_sclk_mmc2, | ||
572 | &clk_sclk_audio0, | ||
573 | }; | ||
574 | |||
575 | static struct clk_lookup s5p6450_clk_lookup[] = { | ||
576 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk), | ||
577 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk), | ||
578 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | ||
579 | CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk), | ||
580 | CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk), | ||
581 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | ||
582 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | ||
583 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | ||
584 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0), | ||
585 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_sclk_audio0.clk), | ||
586 | CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1), | ||
587 | CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2), | ||
588 | }; | ||
589 | |||
590 | /* Clock initialization code */ | ||
591 | static struct clksrc_clk *sysclks[] = { | ||
592 | &clk_mout_apll, | ||
593 | &clk_mout_epll, | ||
594 | &clk_dout_epll, | ||
595 | &clk_mout_mpll, | ||
596 | &clk_dout_mpll, | ||
597 | &clk_armclk, | ||
598 | &clk_mout_hclk_sel, | ||
599 | &clk_dout_pwm_ratio0, | ||
600 | &clk_pclk_to_wdt_pwm, | ||
601 | &clk_hclk, | ||
602 | &clk_pclk, | ||
603 | &clk_hclk_low, | ||
604 | &clk_pclk_low, | ||
605 | }; | ||
606 | |||
607 | static struct clk dummy_apb_pclk = { | ||
608 | .name = "apb_pclk", | ||
609 | .id = -1, | ||
610 | }; | ||
611 | |||
612 | void __init_or_cpufreq s5p6450_setup_clocks(void) | ||
613 | { | ||
614 | struct clk *xtal_clk; | ||
615 | |||
616 | unsigned long xtal; | ||
617 | unsigned long fclk; | ||
618 | unsigned long hclk; | ||
619 | unsigned long hclk_low; | ||
620 | unsigned long pclk; | ||
621 | unsigned long pclk_low; | ||
622 | |||
623 | unsigned long apll; | ||
624 | unsigned long mpll; | ||
625 | unsigned long epll; | ||
626 | unsigned long dpll; | ||
627 | unsigned int ptr; | ||
628 | |||
629 | /* Set S5P6450 functions for clk_fout_epll */ | ||
630 | |||
631 | clk_fout_epll.enable = s5p_epll_enable; | ||
632 | clk_fout_epll.ops = &s5p6450_epll_ops; | ||
633 | |||
634 | clk_48m.enable = s5p64x0_clk48m_ctrl; | ||
635 | |||
636 | xtal_clk = clk_get(NULL, "ext_xtal"); | ||
637 | BUG_ON(IS_ERR(xtal_clk)); | ||
638 | |||
639 | xtal = clk_get_rate(xtal_clk); | ||
640 | clk_put(xtal_clk); | ||
641 | |||
642 | apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502); | ||
643 | mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502); | ||
644 | epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON), | ||
645 | __raw_readl(S5P64X0_EPLL_CON_K)); | ||
646 | dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON), | ||
647 | __raw_readl(S5P6450_DPLL_CON_K), pll_4650c); | ||
648 | |||
649 | clk_fout_apll.rate = apll; | ||
650 | clk_fout_mpll.rate = mpll; | ||
651 | clk_fout_epll.rate = epll; | ||
652 | clk_fout_dpll.rate = dpll; | ||
653 | |||
654 | printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \ | ||
655 | " E=%ld.%ldMHz, D=%ld.%ldMHz\n", | ||
656 | print_mhz(apll), print_mhz(mpll), print_mhz(epll), | ||
657 | print_mhz(dpll)); | ||
658 | |||
659 | fclk = clk_get_rate(&clk_armclk.clk); | ||
660 | hclk = clk_get_rate(&clk_hclk.clk); | ||
661 | pclk = clk_get_rate(&clk_pclk.clk); | ||
662 | hclk_low = clk_get_rate(&clk_hclk_low.clk); | ||
663 | pclk_low = clk_get_rate(&clk_pclk_low.clk); | ||
664 | |||
665 | printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \ | ||
666 | " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n", | ||
667 | print_mhz(hclk), print_mhz(hclk_low), | ||
668 | print_mhz(pclk), print_mhz(pclk_low)); | ||
669 | |||
670 | clk_f.rate = fclk; | ||
671 | clk_h.rate = hclk; | ||
672 | clk_p.rate = pclk; | ||
673 | |||
674 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
675 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
676 | } | ||
677 | |||
678 | void __init s5p6450_register_clocks(void) | ||
679 | { | ||
680 | int ptr; | ||
681 | unsigned int cnt; | ||
682 | |||
683 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | ||
684 | s3c_register_clksrc(sysclks[ptr], 1); | ||
685 | |||
686 | |||
687 | s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); | ||
688 | for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++) | ||
689 | s3c_disable_clocks(clk_cdev[cnt], 1); | ||
690 | |||
691 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
692 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
693 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) | ||
694 | s3c_register_clksrc(clksrc_cdev[ptr], 1); | ||
695 | |||
696 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
697 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
698 | clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup)); | ||
699 | |||
700 | s3c24xx_register_clock(&dummy_apb_pclk); | ||
701 | } | ||
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c deleted file mode 100644 index 57e718957ef3..000000000000 --- a/arch/arm/mach-s5p64x0/clock.c +++ /dev/null | |||
@@ -1,236 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/clock.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - Clock support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/errno.h> | ||
18 | #include <linux/err.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/device.h> | ||
21 | #include <linux/io.h> | ||
22 | |||
23 | #include <mach/hardware.h> | ||
24 | #include <mach/map.h> | ||
25 | #include <mach/regs-clock.h> | ||
26 | |||
27 | #include <plat/cpu-freq.h> | ||
28 | #include <plat/clock.h> | ||
29 | #include <plat/cpu.h> | ||
30 | #include <plat/pll.h> | ||
31 | #include <plat/s5p-clock.h> | ||
32 | #include <plat/clock-clksrc.h> | ||
33 | |||
34 | #include "common.h" | ||
35 | |||
36 | struct clksrc_clk clk_mout_apll = { | ||
37 | .clk = { | ||
38 | .name = "mout_apll", | ||
39 | .id = -1, | ||
40 | }, | ||
41 | .sources = &clk_src_apll, | ||
42 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 }, | ||
43 | }; | ||
44 | |||
45 | struct clksrc_clk clk_mout_mpll = { | ||
46 | .clk = { | ||
47 | .name = "mout_mpll", | ||
48 | .id = -1, | ||
49 | }, | ||
50 | .sources = &clk_src_mpll, | ||
51 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 }, | ||
52 | }; | ||
53 | |||
54 | struct clksrc_clk clk_mout_epll = { | ||
55 | .clk = { | ||
56 | .name = "mout_epll", | ||
57 | .id = -1, | ||
58 | }, | ||
59 | .sources = &clk_src_epll, | ||
60 | .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 }, | ||
61 | }; | ||
62 | |||
63 | enum perf_level { | ||
64 | L0 = 532*1000, | ||
65 | L1 = 266*1000, | ||
66 | L2 = 133*1000, | ||
67 | }; | ||
68 | |||
69 | static const u32 clock_table[][3] = { | ||
70 | /*{ARM_CLK, DIVarm, DIVhclk}*/ | ||
71 | {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, | ||
72 | {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, | ||
73 | {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)}, | ||
74 | }; | ||
75 | |||
76 | static unsigned long s5p64x0_armclk_get_rate(struct clk *clk) | ||
77 | { | ||
78 | unsigned long rate = clk_get_rate(clk->parent); | ||
79 | u32 clkdiv; | ||
80 | |||
81 | /* divisor mask starts at bit0, so no need to shift */ | ||
82 | clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK; | ||
83 | |||
84 | return rate / (clkdiv + 1); | ||
85 | } | ||
86 | |||
87 | static unsigned long s5p64x0_armclk_round_rate(struct clk *clk, | ||
88 | unsigned long rate) | ||
89 | { | ||
90 | u32 iter; | ||
91 | |||
92 | for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) { | ||
93 | if (rate > clock_table[iter][0]) | ||
94 | return clock_table[iter-1][0]; | ||
95 | } | ||
96 | |||
97 | return clock_table[ARRAY_SIZE(clock_table) - 1][0]; | ||
98 | } | ||
99 | |||
100 | static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate) | ||
101 | { | ||
102 | u32 round_tmp; | ||
103 | u32 iter; | ||
104 | u32 clk_div0_tmp; | ||
105 | u32 cur_rate = clk->ops->get_rate(clk); | ||
106 | unsigned long flags; | ||
107 | |||
108 | round_tmp = clk->ops->round_rate(clk, rate); | ||
109 | if (round_tmp == cur_rate) | ||
110 | return 0; | ||
111 | |||
112 | |||
113 | for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) { | ||
114 | if (round_tmp == clock_table[iter][0]) | ||
115 | break; | ||
116 | } | ||
117 | |||
118 | if (iter >= ARRAY_SIZE(clock_table)) | ||
119 | iter = ARRAY_SIZE(clock_table) - 1; | ||
120 | |||
121 | local_irq_save(flags); | ||
122 | if (cur_rate > round_tmp) { | ||
123 | /* Frequency Down */ | ||
124 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); | ||
125 | clk_div0_tmp |= clock_table[iter][1]; | ||
126 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
127 | |||
128 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & | ||
129 | ~(S5P64X0_CLKDIV0_HCLK_MASK); | ||
130 | clk_div0_tmp |= clock_table[iter][2]; | ||
131 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
132 | |||
133 | |||
134 | } else { | ||
135 | /* Frequency Up */ | ||
136 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & | ||
137 | ~(S5P64X0_CLKDIV0_HCLK_MASK); | ||
138 | clk_div0_tmp |= clock_table[iter][2]; | ||
139 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
140 | |||
141 | clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK); | ||
142 | clk_div0_tmp |= clock_table[iter][1]; | ||
143 | __raw_writel(clk_div0_tmp, ARM_CLK_DIV); | ||
144 | } | ||
145 | local_irq_restore(flags); | ||
146 | |||
147 | clk->rate = clock_table[iter][0]; | ||
148 | |||
149 | return 0; | ||
150 | } | ||
151 | |||
152 | static struct clk_ops s5p64x0_clkarm_ops = { | ||
153 | .get_rate = s5p64x0_armclk_get_rate, | ||
154 | .set_rate = s5p64x0_armclk_set_rate, | ||
155 | .round_rate = s5p64x0_armclk_round_rate, | ||
156 | }; | ||
157 | |||
158 | struct clksrc_clk clk_armclk = { | ||
159 | .clk = { | ||
160 | .name = "armclk", | ||
161 | .id = 1, | ||
162 | .parent = &clk_mout_apll.clk, | ||
163 | .ops = &s5p64x0_clkarm_ops, | ||
164 | }, | ||
165 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 }, | ||
166 | }; | ||
167 | |||
168 | struct clksrc_clk clk_dout_mpll = { | ||
169 | .clk = { | ||
170 | .name = "dout_mpll", | ||
171 | .id = -1, | ||
172 | .parent = &clk_mout_mpll.clk, | ||
173 | }, | ||
174 | .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 }, | ||
175 | }; | ||
176 | |||
177 | static struct clk *clkset_hclk_low_list[] = { | ||
178 | &clk_mout_apll.clk, | ||
179 | &clk_mout_mpll.clk, | ||
180 | }; | ||
181 | |||
182 | struct clksrc_sources clkset_hclk_low = { | ||
183 | .sources = clkset_hclk_low_list, | ||
184 | .nr_sources = ARRAY_SIZE(clkset_hclk_low_list), | ||
185 | }; | ||
186 | |||
187 | int s5p64x0_pclk_ctrl(struct clk *clk, int enable) | ||
188 | { | ||
189 | return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable); | ||
190 | } | ||
191 | |||
192 | int s5p64x0_hclk0_ctrl(struct clk *clk, int enable) | ||
193 | { | ||
194 | return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable); | ||
195 | } | ||
196 | |||
197 | int s5p64x0_hclk1_ctrl(struct clk *clk, int enable) | ||
198 | { | ||
199 | return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable); | ||
200 | } | ||
201 | |||
202 | int s5p64x0_sclk_ctrl(struct clk *clk, int enable) | ||
203 | { | ||
204 | return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable); | ||
205 | } | ||
206 | |||
207 | int s5p64x0_sclk1_ctrl(struct clk *clk, int enable) | ||
208 | { | ||
209 | return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable); | ||
210 | } | ||
211 | |||
212 | int s5p64x0_mem_ctrl(struct clk *clk, int enable) | ||
213 | { | ||
214 | return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable); | ||
215 | } | ||
216 | |||
217 | int s5p64x0_clk48m_ctrl(struct clk *clk, int enable) | ||
218 | { | ||
219 | unsigned long flags; | ||
220 | u32 val; | ||
221 | |||
222 | /* can't rely on clock lock, this register has other usages */ | ||
223 | local_irq_save(flags); | ||
224 | |||
225 | val = __raw_readl(S5P64X0_OTHERS); | ||
226 | if (enable) | ||
227 | val |= S5P64X0_OTHERS_USB_SIG_MASK; | ||
228 | else | ||
229 | val &= ~S5P64X0_OTHERS_USB_SIG_MASK; | ||
230 | |||
231 | __raw_writel(val, S5P64X0_OTHERS); | ||
232 | |||
233 | local_irq_restore(flags); | ||
234 | |||
235 | return 0; | ||
236 | } | ||
diff --git a/arch/arm/mach-s5p64x0/clock.h b/arch/arm/mach-s5p64x0/clock.h deleted file mode 100644 index 28b8e3c6bd24..000000000000 --- a/arch/arm/mach-s5p64x0/clock.h +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * Header file for s5p64x0 clock support | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __MACH_S5P64X0_CLOCK_H | ||
13 | #define __MACH_S5P64X0_CLOCK_H __FILE__ | ||
14 | |||
15 | #include <linux/clk.h> | ||
16 | |||
17 | extern struct clksrc_clk clk_mout_apll; | ||
18 | extern struct clksrc_clk clk_mout_mpll; | ||
19 | extern struct clksrc_clk clk_mout_epll; | ||
20 | |||
21 | extern int s5p64x0_epll_enable(struct clk *clk, int enable); | ||
22 | extern unsigned long s5p64x0_epll_get_rate(struct clk *clk); | ||
23 | |||
24 | extern struct clksrc_clk clk_armclk; | ||
25 | extern struct clksrc_clk clk_dout_mpll; | ||
26 | |||
27 | extern struct clksrc_sources clkset_hclk_low; | ||
28 | |||
29 | extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable); | ||
30 | extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable); | ||
31 | extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable); | ||
32 | extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable); | ||
33 | extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable); | ||
34 | extern int s5p64x0_mem_ctrl(struct clk *clk, int enable); | ||
35 | |||
36 | extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable); | ||
37 | |||
38 | #endif /* __MACH_S5P64X0_CLOCK_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c deleted file mode 100644 index 9a43be002d78..000000000000 --- a/arch/arm/mach-s5p64x0/common.c +++ /dev/null | |||
@@ -1,490 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * Common Codes for S5P64X0 machines | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/types.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/list.h> | ||
16 | #include <linux/timer.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/io.h> | ||
20 | #include <linux/device.h> | ||
21 | #include <linux/serial_core.h> | ||
22 | #include <linux/serial_s3c.h> | ||
23 | #include <clocksource/samsung_pwm.h> | ||
24 | #include <linux/platform_device.h> | ||
25 | #include <linux/sched.h> | ||
26 | #include <linux/dma-mapping.h> | ||
27 | #include <linux/gpio.h> | ||
28 | #include <linux/irq.h> | ||
29 | #include <linux/reboot.h> | ||
30 | |||
31 | #include <asm/irq.h> | ||
32 | #include <asm/proc-fns.h> | ||
33 | #include <asm/system_misc.h> | ||
34 | #include <asm/mach/arch.h> | ||
35 | #include <asm/mach/map.h> | ||
36 | #include <asm/mach/irq.h> | ||
37 | |||
38 | #include <mach/map.h> | ||
39 | #include <mach/hardware.h> | ||
40 | #include <mach/regs-clock.h> | ||
41 | #include <mach/regs-gpio.h> | ||
42 | |||
43 | #include <plat/cpu.h> | ||
44 | #include <plat/clock.h> | ||
45 | #include <plat/devs.h> | ||
46 | #include <plat/pm.h> | ||
47 | #include <plat/sdhci.h> | ||
48 | #include <plat/adc-core.h> | ||
49 | #include <plat/fb-core.h> | ||
50 | #include <plat/spi-core.h> | ||
51 | #include <plat/gpio-cfg.h> | ||
52 | #include <plat/pwm-core.h> | ||
53 | #include <plat/regs-irqtype.h> | ||
54 | #include <plat/watchdog-reset.h> | ||
55 | |||
56 | #include "common.h" | ||
57 | |||
58 | static const char name_s5p6440[] = "S5P6440"; | ||
59 | static const char name_s5p6450[] = "S5P6450"; | ||
60 | |||
61 | static struct cpu_table cpu_ids[] __initdata = { | ||
62 | { | ||
63 | .idcode = S5P6440_CPU_ID, | ||
64 | .idmask = S5P64XX_CPU_MASK, | ||
65 | .map_io = s5p6440_map_io, | ||
66 | .init_clocks = s5p6440_init_clocks, | ||
67 | .init_uarts = s5p6440_init_uarts, | ||
68 | .init = s5p64x0_init, | ||
69 | .name = name_s5p6440, | ||
70 | }, { | ||
71 | .idcode = S5P6450_CPU_ID, | ||
72 | .idmask = S5P64XX_CPU_MASK, | ||
73 | .map_io = s5p6450_map_io, | ||
74 | .init_clocks = s5p6450_init_clocks, | ||
75 | .init_uarts = s5p6450_init_uarts, | ||
76 | .init = s5p64x0_init, | ||
77 | .name = name_s5p6450, | ||
78 | }, | ||
79 | }; | ||
80 | |||
81 | /* Initial IO mappings */ | ||
82 | |||
83 | static struct map_desc s5p64x0_iodesc[] __initdata = { | ||
84 | { | ||
85 | .virtual = (unsigned long)S5P_VA_CHIPID, | ||
86 | .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID), | ||
87 | .length = SZ_4K, | ||
88 | .type = MT_DEVICE, | ||
89 | }, { | ||
90 | .virtual = (unsigned long)S3C_VA_SYS, | ||
91 | .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON), | ||
92 | .length = SZ_64K, | ||
93 | .type = MT_DEVICE, | ||
94 | }, { | ||
95 | .virtual = (unsigned long)S3C_VA_TIMER, | ||
96 | .pfn = __phys_to_pfn(S5P64X0_PA_TIMER), | ||
97 | .length = SZ_16K, | ||
98 | .type = MT_DEVICE, | ||
99 | }, { | ||
100 | .virtual = (unsigned long)S3C_VA_WATCHDOG, | ||
101 | .pfn = __phys_to_pfn(S5P64X0_PA_WDT), | ||
102 | .length = SZ_4K, | ||
103 | .type = MT_DEVICE, | ||
104 | }, { | ||
105 | .virtual = (unsigned long)S5P_VA_SROMC, | ||
106 | .pfn = __phys_to_pfn(S5P64X0_PA_SROMC), | ||
107 | .length = SZ_4K, | ||
108 | .type = MT_DEVICE, | ||
109 | }, { | ||
110 | .virtual = (unsigned long)S5P_VA_GPIO, | ||
111 | .pfn = __phys_to_pfn(S5P64X0_PA_GPIO), | ||
112 | .length = SZ_4K, | ||
113 | .type = MT_DEVICE, | ||
114 | }, { | ||
115 | .virtual = (unsigned long)VA_VIC0, | ||
116 | .pfn = __phys_to_pfn(S5P64X0_PA_VIC0), | ||
117 | .length = SZ_16K, | ||
118 | .type = MT_DEVICE, | ||
119 | }, { | ||
120 | .virtual = (unsigned long)VA_VIC1, | ||
121 | .pfn = __phys_to_pfn(S5P64X0_PA_VIC1), | ||
122 | .length = SZ_16K, | ||
123 | .type = MT_DEVICE, | ||
124 | }, | ||
125 | }; | ||
126 | |||
127 | static struct map_desc s5p6440_iodesc[] __initdata = { | ||
128 | { | ||
129 | .virtual = (unsigned long)S3C_VA_UART, | ||
130 | .pfn = __phys_to_pfn(S5P6440_PA_UART(0)), | ||
131 | .length = SZ_4K, | ||
132 | .type = MT_DEVICE, | ||
133 | }, | ||
134 | }; | ||
135 | |||
136 | static struct map_desc s5p6450_iodesc[] __initdata = { | ||
137 | { | ||
138 | .virtual = (unsigned long)S3C_VA_UART, | ||
139 | .pfn = __phys_to_pfn(S5P6450_PA_UART(0)), | ||
140 | .length = SZ_512K, | ||
141 | .type = MT_DEVICE, | ||
142 | }, { | ||
143 | .virtual = (unsigned long)S3C_VA_UART + SZ_512K, | ||
144 | .pfn = __phys_to_pfn(S5P6450_PA_UART(5)), | ||
145 | .length = SZ_4K, | ||
146 | .type = MT_DEVICE, | ||
147 | }, | ||
148 | }; | ||
149 | |||
150 | static void s5p64x0_idle(void) | ||
151 | { | ||
152 | unsigned long val; | ||
153 | |||
154 | val = __raw_readl(S5P64X0_PWR_CFG); | ||
155 | val &= ~(0x3 << 5); | ||
156 | val |= (0x1 << 5); | ||
157 | __raw_writel(val, S5P64X0_PWR_CFG); | ||
158 | |||
159 | cpu_do_idle(); | ||
160 | } | ||
161 | |||
162 | static struct samsung_pwm_variant s5p64x0_pwm_variant = { | ||
163 | .bits = 32, | ||
164 | .div_base = 0, | ||
165 | .has_tint_cstat = true, | ||
166 | .tclk_mask = 0, | ||
167 | }; | ||
168 | |||
169 | void __init samsung_set_timer_source(unsigned int event, unsigned int source) | ||
170 | { | ||
171 | s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; | ||
172 | s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); | ||
173 | } | ||
174 | |||
175 | void __init samsung_timer_init(void) | ||
176 | { | ||
177 | unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { | ||
178 | IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, | ||
179 | IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, | ||
180 | }; | ||
181 | |||
182 | samsung_pwm_clocksource_init(S3C_VA_TIMER, | ||
183 | timer_irqs, &s5p64x0_pwm_variant); | ||
184 | } | ||
185 | |||
186 | /* | ||
187 | * s5p64x0_map_io | ||
188 | * | ||
189 | * register the standard CPU IO areas | ||
190 | */ | ||
191 | |||
192 | void __init s5p64x0_init_io(struct map_desc *mach_desc, int size) | ||
193 | { | ||
194 | /* initialize the io descriptors we need for initialization */ | ||
195 | iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc)); | ||
196 | if (mach_desc) | ||
197 | iotable_init(mach_desc, size); | ||
198 | |||
199 | /* detect cpu id and rev. */ | ||
200 | s5p_init_cpu(S5P64X0_SYS_ID); | ||
201 | |||
202 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); | ||
203 | samsung_wdt_reset_init(S3C_VA_WATCHDOG); | ||
204 | |||
205 | samsung_pwm_set_platdata(&s5p64x0_pwm_variant); | ||
206 | } | ||
207 | |||
208 | #ifdef CONFIG_CPU_S5P6440 | ||
209 | void __init s5p6440_map_io(void) | ||
210 | { | ||
211 | /* initialize any device information early */ | ||
212 | s3c_adc_setname("s3c64xx-adc"); | ||
213 | s3c_fb_setname("s5p64x0-fb"); | ||
214 | s3c64xx_spi_setname("s5p64x0-spi"); | ||
215 | |||
216 | s5p64x0_default_sdhci0(); | ||
217 | s5p64x0_default_sdhci1(); | ||
218 | s5p6440_default_sdhci2(); | ||
219 | |||
220 | iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc)); | ||
221 | } | ||
222 | #endif | ||
223 | |||
224 | #ifdef CONFIG_CPU_S5P6450 | ||
225 | void __init s5p6450_map_io(void) | ||
226 | { | ||
227 | /* initialize any device information early */ | ||
228 | s3c_adc_setname("s3c64xx-adc"); | ||
229 | s3c_fb_setname("s5p64x0-fb"); | ||
230 | s3c64xx_spi_setname("s5p64x0-spi"); | ||
231 | |||
232 | s5p64x0_default_sdhci0(); | ||
233 | s5p64x0_default_sdhci1(); | ||
234 | s5p6450_default_sdhci2(); | ||
235 | |||
236 | iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc)); | ||
237 | } | ||
238 | #endif | ||
239 | |||
240 | /* | ||
241 | * s5p64x0_init_clocks | ||
242 | * | ||
243 | * register and setup the CPU clocks | ||
244 | */ | ||
245 | #ifdef CONFIG_CPU_S5P6440 | ||
246 | void __init s5p6440_init_clocks(int xtal) | ||
247 | { | ||
248 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); | ||
249 | |||
250 | s3c24xx_register_baseclocks(xtal); | ||
251 | s5p_register_clocks(xtal); | ||
252 | s5p6440_register_clocks(); | ||
253 | s5p6440_setup_clocks(); | ||
254 | } | ||
255 | #endif | ||
256 | |||
257 | #ifdef CONFIG_CPU_S5P6450 | ||
258 | void __init s5p6450_init_clocks(int xtal) | ||
259 | { | ||
260 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); | ||
261 | |||
262 | s3c24xx_register_baseclocks(xtal); | ||
263 | s5p_register_clocks(xtal); | ||
264 | s5p6450_register_clocks(); | ||
265 | s5p6450_setup_clocks(); | ||
266 | } | ||
267 | #endif | ||
268 | |||
269 | /* | ||
270 | * s5p64x0_init_irq | ||
271 | * | ||
272 | * register the CPU interrupts | ||
273 | */ | ||
274 | #ifdef CONFIG_CPU_S5P6440 | ||
275 | void __init s5p6440_init_irq(void) | ||
276 | { | ||
277 | /* S5P6440 supports 2 VIC */ | ||
278 | u32 vic[2]; | ||
279 | |||
280 | /* | ||
281 | * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)] | ||
282 | * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22] | ||
283 | */ | ||
284 | vic[0] = 0xff800ae7; | ||
285 | vic[1] = 0xffbf23e5; | ||
286 | |||
287 | s5p_init_irq(vic, ARRAY_SIZE(vic)); | ||
288 | } | ||
289 | #endif | ||
290 | |||
291 | #ifdef CONFIG_CPU_S5P6450 | ||
292 | void __init s5p6450_init_irq(void) | ||
293 | { | ||
294 | /* S5P6450 supports only 2 VIC */ | ||
295 | u32 vic[2]; | ||
296 | |||
297 | /* | ||
298 | * VIC0 is missing IRQ_VIC0[(13-15), (21-22)] | ||
299 | * VIC1 is missing IRQ VIC1[12, 14, 23] | ||
300 | */ | ||
301 | vic[0] = 0xff9f1fff; | ||
302 | vic[1] = 0xff7fafff; | ||
303 | |||
304 | s5p_init_irq(vic, ARRAY_SIZE(vic)); | ||
305 | } | ||
306 | #endif | ||
307 | |||
308 | struct bus_type s5p64x0_subsys = { | ||
309 | .name = "s5p64x0-core", | ||
310 | .dev_name = "s5p64x0-core", | ||
311 | }; | ||
312 | |||
313 | static struct device s5p64x0_dev = { | ||
314 | .bus = &s5p64x0_subsys, | ||
315 | }; | ||
316 | |||
317 | static int __init s5p64x0_core_init(void) | ||
318 | { | ||
319 | return subsys_system_register(&s5p64x0_subsys, NULL); | ||
320 | } | ||
321 | core_initcall(s5p64x0_core_init); | ||
322 | |||
323 | int __init s5p64x0_init(void) | ||
324 | { | ||
325 | printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n"); | ||
326 | |||
327 | /* set idle function */ | ||
328 | arm_pm_idle = s5p64x0_idle; | ||
329 | |||
330 | return device_register(&s5p64x0_dev); | ||
331 | } | ||
332 | |||
333 | /* uart registration process */ | ||
334 | #ifdef CONFIG_CPU_S5P6440 | ||
335 | void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
336 | { | ||
337 | int uart; | ||
338 | |||
339 | for (uart = 0; uart < no; uart++) { | ||
340 | s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart); | ||
341 | s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART; | ||
342 | } | ||
343 | |||
344 | s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); | ||
345 | } | ||
346 | #endif | ||
347 | |||
348 | #ifdef CONFIG_CPU_S5P6450 | ||
349 | void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
350 | { | ||
351 | s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); | ||
352 | } | ||
353 | #endif | ||
354 | |||
355 | #define eint_offset(irq) ((irq) - IRQ_EINT(0)) | ||
356 | |||
357 | static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type) | ||
358 | { | ||
359 | int offs = eint_offset(data->irq); | ||
360 | int shift; | ||
361 | u32 ctrl, mask; | ||
362 | u32 newvalue = 0; | ||
363 | |||
364 | if (offs > 15) | ||
365 | return -EINVAL; | ||
366 | |||
367 | switch (type) { | ||
368 | case IRQ_TYPE_NONE: | ||
369 | printk(KERN_WARNING "No edge setting!\n"); | ||
370 | break; | ||
371 | case IRQ_TYPE_EDGE_RISING: | ||
372 | newvalue = S3C2410_EXTINT_RISEEDGE; | ||
373 | break; | ||
374 | case IRQ_TYPE_EDGE_FALLING: | ||
375 | newvalue = S3C2410_EXTINT_FALLEDGE; | ||
376 | break; | ||
377 | case IRQ_TYPE_EDGE_BOTH: | ||
378 | newvalue = S3C2410_EXTINT_BOTHEDGE; | ||
379 | break; | ||
380 | case IRQ_TYPE_LEVEL_LOW: | ||
381 | newvalue = S3C2410_EXTINT_LOWLEV; | ||
382 | break; | ||
383 | case IRQ_TYPE_LEVEL_HIGH: | ||
384 | newvalue = S3C2410_EXTINT_HILEV; | ||
385 | break; | ||
386 | default: | ||
387 | printk(KERN_ERR "No such irq type %d", type); | ||
388 | return -EINVAL; | ||
389 | } | ||
390 | |||
391 | shift = (offs / 2) * 4; | ||
392 | mask = 0x7 << shift; | ||
393 | |||
394 | ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask; | ||
395 | ctrl |= newvalue << shift; | ||
396 | __raw_writel(ctrl, S5P64X0_EINT0CON0); | ||
397 | |||
398 | /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */ | ||
399 | if (soc_is_s5p6450()) | ||
400 | s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2)); | ||
401 | else | ||
402 | s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2)); | ||
403 | |||
404 | return 0; | ||
405 | } | ||
406 | |||
407 | /* | ||
408 | * s5p64x0_irq_demux_eint | ||
409 | * | ||
410 | * This function demuxes the IRQ from the group0 external interrupts, | ||
411 | * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into | ||
412 | * the specific handlers s5p64x0_irq_demux_eintX_Y. | ||
413 | */ | ||
414 | static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end) | ||
415 | { | ||
416 | u32 status = __raw_readl(S5P64X0_EINT0PEND); | ||
417 | u32 mask = __raw_readl(S5P64X0_EINT0MASK); | ||
418 | unsigned int irq; | ||
419 | |||
420 | status &= ~mask; | ||
421 | status >>= start; | ||
422 | status &= (1 << (end - start + 1)) - 1; | ||
423 | |||
424 | for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) { | ||
425 | if (status & 1) | ||
426 | generic_handle_irq(irq); | ||
427 | status >>= 1; | ||
428 | } | ||
429 | } | ||
430 | |||
431 | static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc) | ||
432 | { | ||
433 | s5p64x0_irq_demux_eint(0, 3); | ||
434 | } | ||
435 | |||
436 | static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc) | ||
437 | { | ||
438 | s5p64x0_irq_demux_eint(4, 11); | ||
439 | } | ||
440 | |||
441 | static void s5p64x0_irq_demux_eint12_15(unsigned int irq, | ||
442 | struct irq_desc *desc) | ||
443 | { | ||
444 | s5p64x0_irq_demux_eint(12, 15); | ||
445 | } | ||
446 | |||
447 | static int s5p64x0_alloc_gc(void) | ||
448 | { | ||
449 | struct irq_chip_generic *gc; | ||
450 | struct irq_chip_type *ct; | ||
451 | |||
452 | gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE, | ||
453 | S5P_VA_GPIO, handle_level_irq); | ||
454 | if (!gc) { | ||
455 | printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0" | ||
456 | "external interrupts failed\n", __func__); | ||
457 | return -EINVAL; | ||
458 | } | ||
459 | |||
460 | ct = gc->chip_types; | ||
461 | ct->chip.irq_ack = irq_gc_ack_set_bit; | ||
462 | ct->chip.irq_mask = irq_gc_mask_set_bit; | ||
463 | ct->chip.irq_unmask = irq_gc_mask_clr_bit; | ||
464 | ct->chip.irq_set_type = s5p64x0_irq_eint_set_type; | ||
465 | ct->chip.irq_set_wake = s3c_irqext_wake; | ||
466 | ct->regs.ack = EINT0PEND_OFFSET; | ||
467 | ct->regs.mask = EINT0MASK_OFFSET; | ||
468 | irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE, | ||
469 | IRQ_NOREQUEST | IRQ_NOPROBE, 0); | ||
470 | return 0; | ||
471 | } | ||
472 | |||
473 | static int __init s5p64x0_init_irq_eint(void) | ||
474 | { | ||
475 | int ret = s5p64x0_alloc_gc(); | ||
476 | irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3); | ||
477 | irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11); | ||
478 | irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15); | ||
479 | |||
480 | return ret; | ||
481 | } | ||
482 | arch_initcall(s5p64x0_init_irq_eint); | ||
483 | |||
484 | void s5p64x0_restart(enum reboot_mode mode, const char *cmd) | ||
485 | { | ||
486 | if (mode != REBOOT_SOFT) | ||
487 | samsung_wdt_reset(); | ||
488 | |||
489 | soft_restart(0); | ||
490 | } | ||
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h deleted file mode 100644 index cbe7f3d731d0..000000000000 --- a/arch/arm/mach-s5p64x0/common.h +++ /dev/null | |||
@@ -1,56 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * Common Header for S5P64X0 machines | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H | ||
13 | #define __ARCH_ARM_MACH_S5P64X0_COMMON_H | ||
14 | |||
15 | #include <linux/reboot.h> | ||
16 | |||
17 | void s5p6440_init_irq(void); | ||
18 | void s5p6450_init_irq(void); | ||
19 | void s5p64x0_init_io(struct map_desc *mach_desc, int size); | ||
20 | |||
21 | void s5p6440_register_clocks(void); | ||
22 | void s5p6440_setup_clocks(void); | ||
23 | |||
24 | void s5p6450_register_clocks(void); | ||
25 | void s5p6450_setup_clocks(void); | ||
26 | |||
27 | void s5p64x0_restart(enum reboot_mode mode, const char *cmd); | ||
28 | extern int s5p64x0_init(void); | ||
29 | |||
30 | #ifdef CONFIG_CPU_S5P6440 | ||
31 | |||
32 | extern void s5p6440_map_io(void); | ||
33 | extern void s5p6440_init_clocks(int xtal); | ||
34 | |||
35 | extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
36 | |||
37 | #else | ||
38 | #define s5p6440_init_clocks NULL | ||
39 | #define s5p6440_init_uarts NULL | ||
40 | #define s5p6440_map_io NULL | ||
41 | #endif | ||
42 | |||
43 | #ifdef CONFIG_CPU_S5P6450 | ||
44 | |||
45 | extern void s5p6450_map_io(void); | ||
46 | extern void s5p6450_init_clocks(int xtal); | ||
47 | |||
48 | extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
49 | |||
50 | #else | ||
51 | #define s5p6450_init_clocks NULL | ||
52 | #define s5p6450_init_uarts NULL | ||
53 | #define s5p6450_map_io NULL | ||
54 | #endif | ||
55 | |||
56 | #endif /* __ARCH_ARM_MACH_S5P64X0_COMMON_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c deleted file mode 100644 index 723d4773c323..000000000000 --- a/arch/arm/mach-s5p64x0/dev-audio.c +++ /dev/null | |||
@@ -1,176 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/dev-audio.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co. Ltd | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/platform_device.h> | ||
12 | #include <linux/dma-mapping.h> | ||
13 | #include <linux/gpio.h> | ||
14 | |||
15 | #include <plat/gpio-cfg.h> | ||
16 | #include <linux/platform_data/asoc-s3c.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <mach/dma.h> | ||
20 | #include <mach/irqs.h> | ||
21 | |||
22 | static int s5p6440_cfg_i2s(struct platform_device *pdev) | ||
23 | { | ||
24 | switch (pdev->id) { | ||
25 | case 0: | ||
26 | s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5)); | ||
27 | s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5)); | ||
28 | s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5)); | ||
29 | break; | ||
30 | default: | ||
31 | printk(KERN_ERR "Invalid Device %d\n", pdev->id); | ||
32 | return -EINVAL; | ||
33 | } | ||
34 | |||
35 | return 0; | ||
36 | } | ||
37 | |||
38 | static struct s3c_audio_pdata s5p6440_i2s_pdata = { | ||
39 | .cfg_gpio = s5p6440_cfg_i2s, | ||
40 | .type = { | ||
41 | .i2s = { | ||
42 | .quirks = QUIRK_PRI_6CHAN, | ||
43 | }, | ||
44 | }, | ||
45 | }; | ||
46 | |||
47 | static struct resource s5p64x0_i2s0_resource[] = { | ||
48 | [0] = DEFINE_RES_MEM(S5P64X0_PA_I2S, SZ_256), | ||
49 | [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), | ||
50 | [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), | ||
51 | }; | ||
52 | |||
53 | struct platform_device s5p6440_device_iis = { | ||
54 | .name = "samsung-i2s", | ||
55 | .id = 0, | ||
56 | .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource), | ||
57 | .resource = s5p64x0_i2s0_resource, | ||
58 | .dev = { | ||
59 | .platform_data = &s5p6440_i2s_pdata, | ||
60 | }, | ||
61 | }; | ||
62 | |||
63 | static int s5p6450_cfg_i2s(struct platform_device *pdev) | ||
64 | { | ||
65 | switch (pdev->id) { | ||
66 | case 0: | ||
67 | s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5)); | ||
68 | s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5)); | ||
69 | break; | ||
70 | case 1: | ||
71 | s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5)); | ||
72 | s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5)); | ||
73 | break; | ||
74 | case 2: | ||
75 | s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5)); | ||
76 | break; | ||
77 | default: | ||
78 | printk(KERN_ERR "Invalid Device %d\n", pdev->id); | ||
79 | return -EINVAL; | ||
80 | } | ||
81 | |||
82 | return 0; | ||
83 | } | ||
84 | |||
85 | static struct s3c_audio_pdata s5p6450_i2s0_pdata = { | ||
86 | .cfg_gpio = s5p6450_cfg_i2s, | ||
87 | .type = { | ||
88 | .i2s = { | ||
89 | .quirks = QUIRK_PRI_6CHAN, | ||
90 | }, | ||
91 | }, | ||
92 | }; | ||
93 | |||
94 | struct platform_device s5p6450_device_iis0 = { | ||
95 | .name = "samsung-i2s", | ||
96 | .id = 0, | ||
97 | .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource), | ||
98 | .resource = s5p64x0_i2s0_resource, | ||
99 | .dev = { | ||
100 | .platform_data = &s5p6450_i2s0_pdata, | ||
101 | }, | ||
102 | }; | ||
103 | |||
104 | static struct s3c_audio_pdata s5p6450_i2s_pdata = { | ||
105 | .cfg_gpio = s5p6450_cfg_i2s, | ||
106 | }; | ||
107 | |||
108 | static struct resource s5p6450_i2s1_resource[] = { | ||
109 | [0] = DEFINE_RES_MEM(S5P6450_PA_I2S1, SZ_256), | ||
110 | [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), | ||
111 | [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), | ||
112 | }; | ||
113 | |||
114 | struct platform_device s5p6450_device_iis1 = { | ||
115 | .name = "samsung-i2s", | ||
116 | .id = 1, | ||
117 | .num_resources = ARRAY_SIZE(s5p6450_i2s1_resource), | ||
118 | .resource = s5p6450_i2s1_resource, | ||
119 | .dev = { | ||
120 | .platform_data = &s5p6450_i2s_pdata, | ||
121 | }, | ||
122 | }; | ||
123 | |||
124 | static struct resource s5p6450_i2s2_resource[] = { | ||
125 | [0] = DEFINE_RES_MEM(S5P6450_PA_I2S2, SZ_256), | ||
126 | [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), | ||
127 | [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), | ||
128 | }; | ||
129 | |||
130 | struct platform_device s5p6450_device_iis2 = { | ||
131 | .name = "samsung-i2s", | ||
132 | .id = 2, | ||
133 | .num_resources = ARRAY_SIZE(s5p6450_i2s2_resource), | ||
134 | .resource = s5p6450_i2s2_resource, | ||
135 | .dev = { | ||
136 | .platform_data = &s5p6450_i2s_pdata, | ||
137 | }, | ||
138 | }; | ||
139 | |||
140 | /* PCM Controller platform_devices */ | ||
141 | |||
142 | static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev) | ||
143 | { | ||
144 | switch (pdev->id) { | ||
145 | case 0: | ||
146 | s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2)); | ||
147 | s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2)); | ||
148 | break; | ||
149 | |||
150 | default: | ||
151 | printk(KERN_DEBUG "Invalid PCM Controller number!"); | ||
152 | return -EINVAL; | ||
153 | } | ||
154 | |||
155 | return 0; | ||
156 | } | ||
157 | |||
158 | static struct s3c_audio_pdata s5p6440_pcm_pdata = { | ||
159 | .cfg_gpio = s5p6440_pcm_cfg_gpio, | ||
160 | }; | ||
161 | |||
162 | static struct resource s5p6440_pcm0_resource[] = { | ||
163 | [0] = DEFINE_RES_MEM(S5P64X0_PA_PCM, SZ_256), | ||
164 | [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), | ||
165 | [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), | ||
166 | }; | ||
167 | |||
168 | struct platform_device s5p6440_device_pcm = { | ||
169 | .name = "samsung-pcm", | ||
170 | .id = 0, | ||
171 | .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource), | ||
172 | .resource = s5p6440_pcm0_resource, | ||
173 | .dev = { | ||
174 | .platform_data = &s5p6440_pcm_pdata, | ||
175 | }, | ||
176 | }; | ||
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c deleted file mode 100644 index 9c4ce085f585..000000000000 --- a/arch/arm/mach-s5p64x0/dma.c +++ /dev/null | |||
@@ -1,128 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/dma.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
7 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
22 | */ | ||
23 | |||
24 | #include <linux/dma-mapping.h> | ||
25 | #include <linux/amba/bus.h> | ||
26 | #include <linux/amba/pl330.h> | ||
27 | |||
28 | #include <asm/irq.h> | ||
29 | |||
30 | #include <mach/map.h> | ||
31 | #include <mach/irqs.h> | ||
32 | #include <mach/regs-clock.h> | ||
33 | #include <mach/dma.h> | ||
34 | |||
35 | #include <plat/cpu.h> | ||
36 | #include <plat/devs.h> | ||
37 | #include <plat/irqs.h> | ||
38 | |||
39 | static u8 s5p6440_pdma_peri[] = { | ||
40 | DMACH_UART0_RX, | ||
41 | DMACH_UART0_TX, | ||
42 | DMACH_UART1_RX, | ||
43 | DMACH_UART1_TX, | ||
44 | DMACH_UART2_RX, | ||
45 | DMACH_UART2_TX, | ||
46 | DMACH_UART3_RX, | ||
47 | DMACH_UART3_TX, | ||
48 | DMACH_MAX, | ||
49 | DMACH_MAX, | ||
50 | DMACH_PCM0_TX, | ||
51 | DMACH_PCM0_RX, | ||
52 | DMACH_I2S0_TX, | ||
53 | DMACH_I2S0_RX, | ||
54 | DMACH_SPI0_TX, | ||
55 | DMACH_SPI0_RX, | ||
56 | DMACH_MAX, | ||
57 | DMACH_MAX, | ||
58 | DMACH_MAX, | ||
59 | DMACH_MAX, | ||
60 | DMACH_SPI1_TX, | ||
61 | DMACH_SPI1_RX, | ||
62 | }; | ||
63 | |||
64 | static struct dma_pl330_platdata s5p6440_pdma_pdata = { | ||
65 | .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri), | ||
66 | .peri_id = s5p6440_pdma_peri, | ||
67 | }; | ||
68 | |||
69 | static u8 s5p6450_pdma_peri[] = { | ||
70 | DMACH_UART0_RX, | ||
71 | DMACH_UART0_TX, | ||
72 | DMACH_UART1_RX, | ||
73 | DMACH_UART1_TX, | ||
74 | DMACH_UART2_RX, | ||
75 | DMACH_UART2_TX, | ||
76 | DMACH_UART3_RX, | ||
77 | DMACH_UART3_TX, | ||
78 | DMACH_UART4_RX, | ||
79 | DMACH_UART4_TX, | ||
80 | DMACH_PCM0_TX, | ||
81 | DMACH_PCM0_RX, | ||
82 | DMACH_I2S0_TX, | ||
83 | DMACH_I2S0_RX, | ||
84 | DMACH_SPI0_TX, | ||
85 | DMACH_SPI0_RX, | ||
86 | DMACH_PCM1_TX, | ||
87 | DMACH_PCM1_RX, | ||
88 | DMACH_PCM2_TX, | ||
89 | DMACH_PCM2_RX, | ||
90 | DMACH_SPI1_TX, | ||
91 | DMACH_SPI1_RX, | ||
92 | DMACH_USI_TX, | ||
93 | DMACH_USI_RX, | ||
94 | DMACH_MAX, | ||
95 | DMACH_I2S1_TX, | ||
96 | DMACH_I2S1_RX, | ||
97 | DMACH_I2S2_TX, | ||
98 | DMACH_I2S2_RX, | ||
99 | DMACH_PWM, | ||
100 | DMACH_UART5_RX, | ||
101 | DMACH_UART5_TX, | ||
102 | }; | ||
103 | |||
104 | static struct dma_pl330_platdata s5p6450_pdma_pdata = { | ||
105 | .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri), | ||
106 | .peri_id = s5p6450_pdma_peri, | ||
107 | }; | ||
108 | |||
109 | static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330, | ||
110 | S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL); | ||
111 | |||
112 | static int __init s5p64x0_dma_init(void) | ||
113 | { | ||
114 | if (soc_is_s5p6450()) { | ||
115 | dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask); | ||
116 | dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask); | ||
117 | s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata; | ||
118 | } else { | ||
119 | dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask); | ||
120 | dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask); | ||
121 | s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata; | ||
122 | } | ||
123 | |||
124 | amba_device_register(&s5p64x0_pdma_device, &iomem_resource); | ||
125 | |||
126 | return 0; | ||
127 | } | ||
128 | arch_initcall(s5p64x0_dma_init); | ||
diff --git a/arch/arm/mach-s5p64x0/i2c.h b/arch/arm/mach-s5p64x0/i2c.h deleted file mode 100644 index 1e5bb4ea200d..000000000000 --- a/arch/arm/mach-s5p64x0/i2c.h +++ /dev/null | |||
@@ -1,16 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * S5P64X0 I2C configuration | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev); | ||
13 | extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev); | ||
14 | |||
15 | extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev); | ||
16 | extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev); | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S deleted file mode 100644 index 8759e7882bcb..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | /* pull in the relevant register and map files. */ | ||
12 | |||
13 | #include <linux/serial_s3c.h> | ||
14 | #include <plat/map-base.h> | ||
15 | #include <plat/map-s5p.h> | ||
16 | |||
17 | .macro addruart, rp, rv, tmp | ||
18 | mov \rp, #0xE0000000 | ||
19 | orr \rp, \rp, #0x00100000 | ||
20 | ldr \rp, [\rp, #0x118 ] | ||
21 | and \rp, \rp, #0xff000 | ||
22 | teq \rp, #0x50000 @@ S5P6450 | ||
23 | ldreq \rp, =0xEC800000 | ||
24 | movne \rp, #0xEC000000 @@ S5P6440 | ||
25 | ldrne \rv, = S3C_VA_UART | ||
26 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
27 | add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART) | ||
28 | add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART) | ||
29 | #endif | ||
30 | .endm | ||
31 | |||
32 | #include <debug/samsung.S> | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h deleted file mode 100644 index 5a622af461d7..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/dma.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __MACH_DMA_H | ||
21 | #define __MACH_DMA_H | ||
22 | |||
23 | /* This platform uses the common common DMA API driver for PL330 */ | ||
24 | #include <plat/dma-pl330.h> | ||
25 | |||
26 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h deleted file mode 100644 index 06cd3c9b16ac..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/gpio.h +++ /dev/null | |||
@@ -1,132 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - GPIO lib support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_GPIO_H | ||
14 | #define __ASM_ARCH_GPIO_H __FILE__ | ||
15 | |||
16 | /* GPIO bank sizes */ | ||
17 | |||
18 | #define S5P6440_GPIO_A_NR (6) | ||
19 | #define S5P6440_GPIO_B_NR (7) | ||
20 | #define S5P6440_GPIO_C_NR (8) | ||
21 | #define S5P6440_GPIO_F_NR (16) | ||
22 | #define S5P6440_GPIO_G_NR (7) | ||
23 | #define S5P6440_GPIO_H_NR (10) | ||
24 | #define S5P6440_GPIO_I_NR (16) | ||
25 | #define S5P6440_GPIO_J_NR (12) | ||
26 | #define S5P6440_GPIO_N_NR (16) | ||
27 | #define S5P6440_GPIO_P_NR (8) | ||
28 | #define S5P6440_GPIO_R_NR (15) | ||
29 | |||
30 | #define S5P6450_GPIO_A_NR (6) | ||
31 | #define S5P6450_GPIO_B_NR (7) | ||
32 | #define S5P6450_GPIO_C_NR (8) | ||
33 | #define S5P6450_GPIO_D_NR (8) | ||
34 | #define S5P6450_GPIO_F_NR (16) | ||
35 | #define S5P6450_GPIO_G_NR (14) | ||
36 | #define S5P6450_GPIO_H_NR (10) | ||
37 | #define S5P6450_GPIO_I_NR (16) | ||
38 | #define S5P6450_GPIO_J_NR (12) | ||
39 | #define S5P6450_GPIO_K_NR (5) | ||
40 | #define S5P6450_GPIO_N_NR (16) | ||
41 | #define S5P6450_GPIO_P_NR (11) | ||
42 | #define S5P6450_GPIO_Q_NR (14) | ||
43 | #define S5P6450_GPIO_R_NR (15) | ||
44 | #define S5P6450_GPIO_S_NR (8) | ||
45 | |||
46 | /* GPIO bank numbers */ | ||
47 | |||
48 | /* CONFIG_S3C_GPIO_SPACE allows the user to select extra | ||
49 | * space for debugging purposes so that any accidental | ||
50 | * change from one gpio bank to another can be caught. | ||
51 | */ | ||
52 | |||
53 | #define S5P64X0_GPIO_NEXT(__gpio) \ | ||
54 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) | ||
55 | |||
56 | enum s5p6440_gpio_number { | ||
57 | S5P6440_GPIO_A_START = 0, | ||
58 | S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A), | ||
59 | S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B), | ||
60 | S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C), | ||
61 | S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F), | ||
62 | S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G), | ||
63 | S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H), | ||
64 | S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I), | ||
65 | S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J), | ||
66 | S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N), | ||
67 | S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P), | ||
68 | }; | ||
69 | |||
70 | enum s5p6450_gpio_number { | ||
71 | S5P6450_GPIO_A_START = 0, | ||
72 | S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A), | ||
73 | S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B), | ||
74 | S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C), | ||
75 | S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D), | ||
76 | S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F), | ||
77 | S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G), | ||
78 | S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H), | ||
79 | S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I), | ||
80 | S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J), | ||
81 | S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K), | ||
82 | S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N), | ||
83 | S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P), | ||
84 | S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q), | ||
85 | S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R), | ||
86 | }; | ||
87 | |||
88 | /* GPIO number definitions */ | ||
89 | |||
90 | #define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr)) | ||
91 | #define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr)) | ||
92 | #define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr)) | ||
93 | #define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr)) | ||
94 | #define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr)) | ||
95 | #define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr)) | ||
96 | #define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr)) | ||
97 | #define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr)) | ||
98 | #define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr)) | ||
99 | #define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr)) | ||
100 | #define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr)) | ||
101 | |||
102 | #define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr)) | ||
103 | #define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr)) | ||
104 | #define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr)) | ||
105 | #define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr)) | ||
106 | #define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr)) | ||
107 | #define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr)) | ||
108 | #define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr)) | ||
109 | #define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr)) | ||
110 | #define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr)) | ||
111 | #define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr)) | ||
112 | #define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr)) | ||
113 | #define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr)) | ||
114 | #define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr)) | ||
115 | #define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr)) | ||
116 | #define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr)) | ||
117 | |||
118 | /* the end of the S5P64X0 specific gpios */ | ||
119 | |||
120 | #define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1) | ||
121 | #define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1) | ||
122 | |||
123 | #define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \ | ||
124 | S5P6440_GPIO_END : S5P6450_GPIO_END) | ||
125 | |||
126 | #define S3C_GPIO_END S5P64X0_GPIO_END | ||
127 | |||
128 | /* define the number of gpios we need to the one after the last GPIO range */ | ||
129 | |||
130 | #define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA) | ||
131 | |||
132 | #endif /* __ASM_ARCH_GPIO_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h deleted file mode 100644 index d3e87996dd9a..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/hardware.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - Hardware support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_HARDWARE_H | ||
14 | #define __ASM_ARCH_HARDWARE_H __FILE__ | ||
15 | |||
16 | /* currently nothing here, placeholder */ | ||
17 | |||
18 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h deleted file mode 100644 index 53982db9d259..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/irqs.h +++ /dev/null | |||
@@ -1,148 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - IRQ definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_IRQS_H | ||
14 | #define __ASM_ARCH_IRQS_H __FILE__ | ||
15 | |||
16 | #include <plat/irqs.h> | ||
17 | |||
18 | /* VIC0 */ | ||
19 | |||
20 | #define IRQ_EINT0_3 S5P_IRQ_VIC0(0) | ||
21 | #define IRQ_EINT4_11 S5P_IRQ_VIC0(1) | ||
22 | #define IRQ_RTC_TIC S5P_IRQ_VIC0(2) | ||
23 | #define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */ | ||
24 | #define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */ | ||
25 | #define IRQ_IIC1 S5P_IRQ_VIC0(5) | ||
26 | #define IRQ_I2SV40 S5P_IRQ_VIC0(6) | ||
27 | #define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */ | ||
28 | |||
29 | #define IRQ_2D S5P_IRQ_VIC0(11) | ||
30 | #define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23) | ||
31 | #define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24) | ||
32 | #define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25) | ||
33 | #define IRQ_WDT S5P_IRQ_VIC0(26) | ||
34 | #define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27) | ||
35 | #define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28) | ||
36 | #define IRQ_DISPCON0 S5P_IRQ_VIC0(29) | ||
37 | #define IRQ_DISPCON1 S5P_IRQ_VIC0(30) | ||
38 | #define IRQ_DISPCON2 S5P_IRQ_VIC0(31) | ||
39 | |||
40 | /* VIC1 */ | ||
41 | |||
42 | #define IRQ_EINT12_15 S5P_IRQ_VIC1(0) | ||
43 | #define IRQ_PCM0 S5P_IRQ_VIC1(2) | ||
44 | #define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */ | ||
45 | #define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */ | ||
46 | #define IRQ_UART0 S5P_IRQ_VIC1(5) | ||
47 | #define IRQ_UART1 S5P_IRQ_VIC1(6) | ||
48 | #define IRQ_UART2 S5P_IRQ_VIC1(7) | ||
49 | #define IRQ_UART3 S5P_IRQ_VIC1(8) | ||
50 | #define IRQ_DMA0 S5P_IRQ_VIC1(9) | ||
51 | #define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */ | ||
52 | #define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */ | ||
53 | #define IRQ_NFC S5P_IRQ_VIC1(13) | ||
54 | #define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */ | ||
55 | #define IRQ_SPI0 S5P_IRQ_VIC1(16) | ||
56 | #define IRQ_SPI1 S5P_IRQ_VIC1(17) | ||
57 | #define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */ | ||
58 | #define IRQ_IIC S5P_IRQ_VIC1(18) | ||
59 | #define IRQ_DISPCON3 S5P_IRQ_VIC1(19) | ||
60 | #define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21) | ||
61 | #define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */ | ||
62 | #define IRQ_HSMMC0 S5P_IRQ_VIC1(24) | ||
63 | #define IRQ_HSMMC1 S5P_IRQ_VIC1(25) | ||
64 | #define IRQ_OTG S5P_IRQ_VIC1(26) | ||
65 | #define IRQ_DSI S5P_IRQ_VIC1(27) | ||
66 | #define IRQ_RTC_ALARM S5P_IRQ_VIC1(28) | ||
67 | #define IRQ_TSI S5P_IRQ_VIC1(29) | ||
68 | #define IRQ_PENDN S5P_IRQ_VIC1(30) | ||
69 | #define IRQ_TC IRQ_PENDN | ||
70 | #define IRQ_ADC S5P_IRQ_VIC1(31) | ||
71 | |||
72 | /* UART interrupts, S5P6450 has 5 UARTs */ | ||
73 | #define IRQ_S5P_UART_BASE4 (96) | ||
74 | #define IRQ_S5P_UART_BASE5 (100) | ||
75 | |||
76 | #define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD) | ||
77 | #define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD) | ||
78 | #define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR) | ||
79 | |||
80 | #define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD) | ||
81 | #define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD) | ||
82 | #define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR) | ||
83 | |||
84 | /* S3C compatibilty defines */ | ||
85 | #define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4 | ||
86 | #define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5 | ||
87 | |||
88 | #define IRQ_I2S0 IRQ_I2SV40 | ||
89 | |||
90 | #define IRQ_LCD_FIFO IRQ_DISPCON0 | ||
91 | #define IRQ_LCD_VSYNC IRQ_DISPCON1 | ||
92 | #define IRQ_LCD_SYSTEM IRQ_DISPCON2 | ||
93 | |||
94 | /* S5P6450 EINT feature will be added */ | ||
95 | |||
96 | /* | ||
97 | * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined | ||
98 | * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place | ||
99 | * after the pair of VICs. | ||
100 | */ | ||
101 | |||
102 | #define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6) | ||
103 | |||
104 | #define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE) | ||
105 | |||
106 | #define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE) | ||
107 | /* | ||
108 | * S5P6440 has 0-15 external interrupts in group 0. Only these can be used | ||
109 | * to wake up from sleep. If request is beyond this range, by mistake, a large | ||
110 | * return value for an irq number should be indication of something amiss. | ||
111 | */ | ||
112 | #define S5P_EINT_BASE2 (0xf0000000) | ||
113 | |||
114 | /* | ||
115 | * Next the external interrupt groups. These are similar to the IRQ_EINT(x) | ||
116 | * that they are sourced from the GPIO pins but with a different scheme for | ||
117 | * priority and source indication. | ||
118 | * | ||
119 | * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO | ||
120 | * interrupts, but for historical reasons they are kept apart from these | ||
121 | * next interrupts. | ||
122 | * | ||
123 | * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the | ||
124 | * machine specific support files. | ||
125 | */ | ||
126 | |||
127 | /* Actually, #6 and #7 are missing in the EINT_GROUP1 */ | ||
128 | #define IRQ_EINT_GROUP1_NR (15) | ||
129 | #define IRQ_EINT_GROUP2_NR (8) | ||
130 | #define IRQ_EINT_GROUP5_NR (7) | ||
131 | #define IRQ_EINT_GROUP6_NR (10) | ||
132 | /* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */ | ||
133 | #define IRQ_EINT_GROUP8_NR (11) | ||
134 | |||
135 | #define IRQ_EINT_GROUP_BASE S5P_EINT(16) | ||
136 | #define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0) | ||
137 | #define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR) | ||
138 | #define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR) | ||
139 | #define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR) | ||
140 | #define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR) | ||
141 | |||
142 | #define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x)) | ||
143 | |||
144 | /* Set the default NR_IRQS */ | ||
145 | |||
146 | #define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1) | ||
147 | |||
148 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h deleted file mode 100644 index 50a6e96d6389..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/map.h +++ /dev/null | |||
@@ -1,96 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/map.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - Memory map definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_MAP_H | ||
14 | #define __ASM_ARCH_MAP_H __FILE__ | ||
15 | |||
16 | #include <plat/map-base.h> | ||
17 | #include <plat/map-s5p.h> | ||
18 | |||
19 | #define S5P64X0_PA_SDRAM 0x20000000 | ||
20 | |||
21 | #define S5P64X0_PA_CHIPID 0xE0000000 | ||
22 | |||
23 | #define S5P64X0_PA_SYSCON 0xE0100000 | ||
24 | |||
25 | #define S5P64X0_PA_GPIO 0xE0308000 | ||
26 | |||
27 | #define S5P64X0_PA_VIC0 0xE4000000 | ||
28 | #define S5P64X0_PA_VIC1 0xE4100000 | ||
29 | |||
30 | #define S5P64X0_PA_SROMC 0xE7000000 | ||
31 | |||
32 | #define S5P64X0_PA_PDMA 0xE9000000 | ||
33 | |||
34 | #define S5P64X0_PA_TIMER 0xEA000000 | ||
35 | #define S5P64X0_PA_RTC 0xEA100000 | ||
36 | #define S5P64X0_PA_WDT 0xEA200000 | ||
37 | |||
38 | #define S5P6440_PA_IIC0 0xEC104000 | ||
39 | #define S5P6440_PA_IIC1 0xEC20F000 | ||
40 | #define S5P6450_PA_IIC0 0xEC100000 | ||
41 | #define S5P6450_PA_IIC1 0xEC200000 | ||
42 | |||
43 | #define S5P64X0_PA_SPI0 0xEC400000 | ||
44 | #define S5P64X0_PA_SPI1 0xEC500000 | ||
45 | |||
46 | #define S5P64X0_PA_HSOTG 0xED100000 | ||
47 | |||
48 | #define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) | ||
49 | |||
50 | #define S5P64X0_PA_FB 0xEE000000 | ||
51 | |||
52 | #define S5P64X0_PA_I2S 0xF2000000 | ||
53 | #define S5P6450_PA_I2S1 0xF2800000 | ||
54 | #define S5P6450_PA_I2S2 0xF2900000 | ||
55 | |||
56 | #define S5P64X0_PA_PCM 0xF2100000 | ||
57 | |||
58 | #define S5P64X0_PA_ADC 0xF3000000 | ||
59 | |||
60 | /* Compatibiltiy Defines */ | ||
61 | |||
62 | #define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0) | ||
63 | #define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1) | ||
64 | #define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2) | ||
65 | #define S3C_PA_IIC S5P6440_PA_IIC0 | ||
66 | #define S3C_PA_IIC1 S5P6440_PA_IIC1 | ||
67 | #define S3C_PA_RTC S5P64X0_PA_RTC | ||
68 | #define S3C_PA_WDT S5P64X0_PA_WDT | ||
69 | #define S3C_PA_FB S5P64X0_PA_FB | ||
70 | #define S3C_PA_SPI0 S5P64X0_PA_SPI0 | ||
71 | #define S3C_PA_SPI1 S5P64X0_PA_SPI1 | ||
72 | |||
73 | #define S5P_PA_CHIPID S5P64X0_PA_CHIPID | ||
74 | #define S5P_PA_SROMC S5P64X0_PA_SROMC | ||
75 | #define S5P_PA_SYSCON S5P64X0_PA_SYSCON | ||
76 | #define S5P_PA_TIMER S5P64X0_PA_TIMER | ||
77 | |||
78 | #define SAMSUNG_PA_ADC S5P64X0_PA_ADC | ||
79 | #define SAMSUNG_PA_TIMER S5P64X0_PA_TIMER | ||
80 | |||
81 | /* UART */ | ||
82 | |||
83 | #define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET)) | ||
84 | #define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000)) | ||
85 | |||
86 | #define S5P_PA_UART0 S5P6450_PA_UART(0) | ||
87 | #define S5P_PA_UART1 S5P6450_PA_UART(1) | ||
88 | #define S5P_PA_UART2 S5P6450_PA_UART(2) | ||
89 | #define S5P_PA_UART3 S5P6450_PA_UART(3) | ||
90 | #define S5P_PA_UART4 S5P6450_PA_UART(4) | ||
91 | #define S5P_PA_UART5 S5P6450_PA_UART(5) | ||
92 | |||
93 | #define S5P_SZ_UART SZ_256 | ||
94 | #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) | ||
95 | |||
96 | #endif /* __ASM_ARCH_MAP_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h deleted file mode 100644 index 1e0eb65b2b82..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h +++ /dev/null | |||
@@ -1,119 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c | ||
7 | * | ||
8 | * Based on PM core support for S3C64XX by Ben Dooks | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/serial_s3c.h> | ||
16 | |||
17 | #include <mach/regs-gpio.h> | ||
18 | |||
19 | static inline void s3c_pm_debug_init_uart(void) | ||
20 | { | ||
21 | u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK); | ||
22 | |||
23 | /* | ||
24 | * As a note, since the S5P64X0 UARTs generally have multiple | ||
25 | * clock sources, we simply enable PCLK at the moment and hope | ||
26 | * that the resume settings for the UART are suitable for the | ||
27 | * use with PCLK. | ||
28 | */ | ||
29 | tmp |= S5P64X0_CLK_GATE_PCLK_UART0; | ||
30 | tmp |= S5P64X0_CLK_GATE_PCLK_UART1; | ||
31 | tmp |= S5P64X0_CLK_GATE_PCLK_UART2; | ||
32 | tmp |= S5P64X0_CLK_GATE_PCLK_UART3; | ||
33 | |||
34 | __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK); | ||
35 | udelay(10); | ||
36 | } | ||
37 | |||
38 | static inline void s3c_pm_arch_prepare_irqs(void) | ||
39 | { | ||
40 | /* VIC should have already been taken care of */ | ||
41 | |||
42 | /* clear any pending EINT0 interrupts */ | ||
43 | __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND); | ||
44 | } | ||
45 | |||
46 | static inline void s3c_pm_arch_stop_clocks(void) { } | ||
47 | static inline void s3c_pm_arch_show_resume_irqs(void) { } | ||
48 | |||
49 | /* | ||
50 | * make these defines, we currently do not have any need to change | ||
51 | * the IRQ wake controls depending on the CPU we are running on | ||
52 | */ | ||
53 | #define s3c_irqwake_eintallow ((1 << 16) - 1) | ||
54 | #define s3c_irqwake_intallow (~0) | ||
55 | |||
56 | static inline void s3c_pm_arch_update_uart(void __iomem *regs, | ||
57 | struct pm_uart_save *save) | ||
58 | { | ||
59 | u32 ucon = __raw_readl(regs + S3C2410_UCON); | ||
60 | u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK; | ||
61 | u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK; | ||
62 | u32 new_ucon; | ||
63 | u32 delta; | ||
64 | |||
65 | /* | ||
66 | * S5P64X0 UART blocks only support level interrupts, so ensure that | ||
67 | * when we restore unused UART blocks we force the level interrupt | ||
68 | * settings. | ||
69 | */ | ||
70 | save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL; | ||
71 | |||
72 | /* | ||
73 | * We have a constraint on changing the clock type of the UART | ||
74 | * between UCLKx and PCLK, so ensure that when we restore UCON | ||
75 | * that the CLK field is correctly modified if the bootloader | ||
76 | * has changed anything. | ||
77 | */ | ||
78 | if (ucon_clk != save_clk) { | ||
79 | new_ucon = save->ucon; | ||
80 | delta = ucon_clk ^ save_clk; | ||
81 | |||
82 | /* | ||
83 | * change from UCLKx => wrong PCLK, | ||
84 | * either UCLK can be tested for by a bit-test | ||
85 | * with UCLK0 | ||
86 | */ | ||
87 | if (ucon_clk & S3C6400_UCON_UCLK0 && | ||
88 | !(save_clk & S3C6400_UCON_UCLK0) && | ||
89 | delta & S3C6400_UCON_PCLK2) { | ||
90 | new_ucon &= ~S3C6400_UCON_UCLK0; | ||
91 | } else if (delta == S3C6400_UCON_PCLK2) { | ||
92 | /* | ||
93 | * as a precaution, don't change from | ||
94 | * PCLK2 => PCLK or vice-versa | ||
95 | */ | ||
96 | new_ucon ^= S3C6400_UCON_PCLK2; | ||
97 | } | ||
98 | |||
99 | S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n", | ||
100 | ucon, new_ucon, save->ucon); | ||
101 | save->ucon = new_ucon; | ||
102 | } | ||
103 | } | ||
104 | |||
105 | static inline void s3c_pm_restored_gpios(void) | ||
106 | { | ||
107 | /* ensure sleep mode has been cleared from the system */ | ||
108 | __raw_writel(0, S5P64X0_SLPEN); | ||
109 | } | ||
110 | |||
111 | static inline void samsung_pm_saved_gpios(void) | ||
112 | { | ||
113 | /* | ||
114 | * turn on the sleep mode and keep it there, as it seems that during | ||
115 | * suspend the xCON registers get re-set and thus you can end up with | ||
116 | * problems between going to sleep and resuming. | ||
117 | */ | ||
118 | __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN); | ||
119 | } | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h deleted file mode 100644 index bd91112c813c..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - Clock register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | ||
14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | ||
19 | |||
20 | #define S5P64X0_APLL_CON S5P_CLKREG(0x0C) | ||
21 | #define S5P64X0_MPLL_CON S5P_CLKREG(0x10) | ||
22 | #define S5P64X0_EPLL_CON S5P_CLKREG(0x14) | ||
23 | #define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18) | ||
24 | |||
25 | #define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C) | ||
26 | |||
27 | #define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20) | ||
28 | #define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24) | ||
29 | #define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28) | ||
30 | |||
31 | #define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30) | ||
32 | #define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34) | ||
33 | #define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38) | ||
34 | #define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C) | ||
35 | |||
36 | #define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40) | ||
37 | |||
38 | #define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44) | ||
39 | #define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48) | ||
40 | |||
41 | #define S5P6450_DPLL_CON S5P_CLKREG(0x50) | ||
42 | #define S5P6450_DPLL_CON_K S5P_CLKREG(0x54) | ||
43 | |||
44 | #define S5P64X0_AHB_CON0 S5P_CLKREG(0x100) | ||
45 | #define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C) | ||
46 | |||
47 | #define S5P64X0_SYS_ID S5P_CLKREG(0x118) | ||
48 | #define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C) | ||
49 | |||
50 | #define S5P64X0_PWR_CFG S5P_CLKREG(0x804) | ||
51 | #define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808) | ||
52 | #define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818) | ||
53 | #define S5P64X0_PWR_STABLE S5P_CLKREG(0x828) | ||
54 | |||
55 | #define S5P64X0_OTHERS S5P_CLKREG(0x900) | ||
56 | #define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908) | ||
57 | |||
58 | #define S5P64X0_INFORM0 S5P_CLKREG(0xA00) | ||
59 | |||
60 | #define S5P64X0_CLKDIV0_HCLK_SHIFT (8) | ||
61 | #define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT) | ||
62 | |||
63 | /* HCLK GATE Registers */ | ||
64 | #define S5P64X0_CLK_GATE_HCLK1_FIMGVG (1 << 2) | ||
65 | #define S5P64X0_CLK_GATE_SCLK1_FIMGVG (1 << 2) | ||
66 | |||
67 | /* PCLK GATE Registers */ | ||
68 | #define S5P64X0_CLK_GATE_PCLK_UART3 (1 << 4) | ||
69 | #define S5P64X0_CLK_GATE_PCLK_UART2 (1 << 3) | ||
70 | #define S5P64X0_CLK_GATE_PCLK_UART1 (1 << 2) | ||
71 | #define S5P64X0_CLK_GATE_PCLK_UART0 (1 << 1) | ||
72 | |||
73 | #define S5P64X0_PWR_CFG_MMC1_DISABLE (1 << 15) | ||
74 | #define S5P64X0_PWR_CFG_MMC0_DISABLE (1 << 14) | ||
75 | #define S5P64X0_PWR_CFG_RTC_TICK_DISABLE (1 << 11) | ||
76 | #define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE (1 << 10) | ||
77 | #define S5P64X0_PWR_CFG_WFI_MASK (3 << 5) | ||
78 | #define S5P64X0_PWR_CFG_WFI_SLEEP (3 << 5) | ||
79 | |||
80 | #define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0) | ||
81 | |||
82 | #define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0) | ||
83 | |||
84 | #define S5P6450_OTHERS_DISABLE_INT (1 << 31) | ||
85 | #define S5P64X0_OTHERS_RET_UART (1 << 26) | ||
86 | #define S5P64X0_OTHERS_RET_MMC1 (1 << 25) | ||
87 | #define S5P64X0_OTHERS_RET_MMC0 (1 << 24) | ||
88 | #define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16) | ||
89 | |||
90 | /* Compatibility defines */ | ||
91 | |||
92 | #define ARM_CLK_DIV S5P64X0_CLK_DIV0 | ||
93 | #define ARM_DIV_RATIO_SHIFT 0 | ||
94 | #define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT) | ||
95 | |||
96 | #define S5P_EPLL_CON S5P64X0_EPLL_CON | ||
97 | |||
98 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h deleted file mode 100644 index cfdfa4fdadf2..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h +++ /dev/null | |||
@@ -1,68 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - GPIO register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_GPIO_H | ||
14 | #define __ASM_ARCH_REGS_GPIO_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | /* Base addresses for each of the banks */ | ||
19 | |||
20 | #define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000) | ||
21 | #define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020) | ||
22 | #define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040) | ||
23 | #define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0) | ||
24 | #define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0) | ||
25 | #define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0) | ||
26 | #define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100) | ||
27 | #define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120) | ||
28 | #define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830) | ||
29 | #define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160) | ||
30 | #define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290) | ||
31 | |||
32 | #define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060) | ||
33 | #define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140) | ||
34 | #define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180) | ||
35 | #define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300) | ||
36 | |||
37 | #define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0) | ||
38 | #define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0) | ||
39 | #define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0) | ||
40 | #define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0) | ||
41 | |||
42 | #define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0) | ||
43 | #define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4) | ||
44 | #define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0) | ||
45 | #define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4) | ||
46 | |||
47 | #define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200) | ||
48 | #define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220) | ||
49 | #define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240) | ||
50 | |||
51 | /* External interrupt control registers for group0 */ | ||
52 | |||
53 | #define EINT0CON0_OFFSET (0x900) | ||
54 | #define EINT0FLTCON0_OFFSET (0x910) | ||
55 | #define EINT0FLTCON1_OFFSET (0x914) | ||
56 | #define EINT0MASK_OFFSET (0x920) | ||
57 | #define EINT0PEND_OFFSET (0x924) | ||
58 | |||
59 | #define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET) | ||
60 | #define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET) | ||
61 | #define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET) | ||
62 | #define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET) | ||
63 | #define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET) | ||
64 | |||
65 | #define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930) | ||
66 | #define S5P64X0_SLPEN_USE_xSLP (1 << 0) | ||
67 | |||
68 | #endif /* __ASM_ARCH_REGS_GPIO_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h deleted file mode 100644 index d60397d1ff40..000000000000 --- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - IRQ register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_IRQ_H | ||
14 | #define __ASM_ARCH_REGS_IRQ_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | #endif /* __ASM_ARCH_REGS_IRQ_H */ | ||
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c deleted file mode 100644 index 2ed921e095dc..000000000000 --- a/arch/arm/mach-s5p64x0/irq-pm.c +++ /dev/null | |||
@@ -1,98 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/irq-pm.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 - Interrupt handling Power Management | ||
7 | * | ||
8 | * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/syscore_ops.h> | ||
16 | #include <linux/serial_core.h> | ||
17 | #include <linux/serial_s3c.h> | ||
18 | #include <linux/io.h> | ||
19 | |||
20 | #include <plat/pm.h> | ||
21 | |||
22 | #include <mach/regs-gpio.h> | ||
23 | |||
24 | static struct sleep_save irq_save[] = { | ||
25 | SAVE_ITEM(S5P64X0_EINT0CON0), | ||
26 | SAVE_ITEM(S5P64X0_EINT0FLTCON0), | ||
27 | SAVE_ITEM(S5P64X0_EINT0FLTCON1), | ||
28 | SAVE_ITEM(S5P64X0_EINT0MASK), | ||
29 | }; | ||
30 | |||
31 | static struct irq_grp_save { | ||
32 | u32 con; | ||
33 | u32 fltcon; | ||
34 | u32 mask; | ||
35 | } eint_grp_save[4]; | ||
36 | |||
37 | #ifdef CONFIG_SERIAL_SAMSUNG | ||
38 | static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS]; | ||
39 | #endif | ||
40 | |||
41 | static int s5p64x0_irq_pm_suspend(void) | ||
42 | { | ||
43 | struct irq_grp_save *grp = eint_grp_save; | ||
44 | int i; | ||
45 | |||
46 | S3C_PMDBG("%s: suspending IRQs\n", __func__); | ||
47 | |||
48 | s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | ||
49 | |||
50 | #ifdef CONFIG_SERIAL_SAMSUNG | ||
51 | for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) | ||
52 | irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM); | ||
53 | #endif | ||
54 | |||
55 | for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { | ||
56 | grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4)); | ||
57 | grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4)); | ||
58 | grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4)); | ||
59 | } | ||
60 | |||
61 | return 0; | ||
62 | } | ||
63 | |||
64 | static void s5p64x0_irq_pm_resume(void) | ||
65 | { | ||
66 | struct irq_grp_save *grp = eint_grp_save; | ||
67 | int i; | ||
68 | |||
69 | S3C_PMDBG("%s: resuming IRQs\n", __func__); | ||
70 | |||
71 | s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | ||
72 | |||
73 | #ifdef CONFIG_SERIAL_SAMSUNG | ||
74 | for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++) | ||
75 | __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM); | ||
76 | #endif | ||
77 | |||
78 | for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) { | ||
79 | __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4)); | ||
80 | __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4)); | ||
81 | __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4)); | ||
82 | } | ||
83 | |||
84 | S3C_PMDBG("%s: IRQ configuration restored\n", __func__); | ||
85 | } | ||
86 | |||
87 | static struct syscore_ops s5p64x0_irq_syscore_ops = { | ||
88 | .suspend = s5p64x0_irq_pm_suspend, | ||
89 | .resume = s5p64x0_irq_pm_resume, | ||
90 | }; | ||
91 | |||
92 | static int __init s5p64x0_syscore_init(void) | ||
93 | { | ||
94 | register_syscore_ops(&s5p64x0_irq_syscore_ops); | ||
95 | |||
96 | return 0; | ||
97 | } | ||
98 | core_initcall(s5p64x0_syscore_init); | ||
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c deleted file mode 100644 index 6840e197cb2d..000000000000 --- a/arch/arm/mach-s5p64x0/mach-smdk6440.c +++ /dev/null | |||
@@ -1,280 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/types.h> | ||
13 | #include <linux/interrupt.h> | ||
14 | #include <linux/list.h> | ||
15 | #include <linux/timer.h> | ||
16 | #include <linux/delay.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/i2c.h> | ||
19 | #include <linux/serial_core.h> | ||
20 | #include <linux/serial_s3c.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/clk.h> | ||
25 | #include <linux/gpio.h> | ||
26 | #include <linux/pwm_backlight.h> | ||
27 | #include <linux/fb.h> | ||
28 | #include <linux/mmc/host.h> | ||
29 | |||
30 | #include <video/platform_lcd.h> | ||
31 | #include <video/samsung_fimd.h> | ||
32 | |||
33 | #include <asm/mach/arch.h> | ||
34 | #include <asm/mach/map.h> | ||
35 | #include <asm/irq.h> | ||
36 | #include <asm/mach-types.h> | ||
37 | |||
38 | #include <mach/hardware.h> | ||
39 | #include <mach/map.h> | ||
40 | #include <mach/regs-clock.h> | ||
41 | #include <mach/regs-gpio.h> | ||
42 | |||
43 | #include <plat/gpio-cfg.h> | ||
44 | #include <plat/clock.h> | ||
45 | #include <plat/devs.h> | ||
46 | #include <plat/cpu.h> | ||
47 | #include <linux/platform_data/i2c-s3c2410.h> | ||
48 | #include <plat/pll.h> | ||
49 | #include <plat/adc.h> | ||
50 | #include <linux/platform_data/touchscreen-s3c2410.h> | ||
51 | #include <plat/samsung-time.h> | ||
52 | #include <plat/backlight.h> | ||
53 | #include <plat/fb.h> | ||
54 | #include <plat/sdhci.h> | ||
55 | |||
56 | #include "common.h" | ||
57 | #include "i2c.h" | ||
58 | |||
59 | #define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | ||
60 | S3C2410_UCON_RXILEVEL | \ | ||
61 | S3C2410_UCON_TXIRQMODE | \ | ||
62 | S3C2410_UCON_RXIRQMODE | \ | ||
63 | S3C2410_UCON_RXFIFO_TOI | \ | ||
64 | S3C2443_UCON_RXERR_IRQEN) | ||
65 | |||
66 | #define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
67 | |||
68 | #define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
69 | S3C2440_UFCON_TXTRIG16 | \ | ||
70 | S3C2410_UFCON_RXTRIG8) | ||
71 | |||
72 | static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { | ||
73 | [0] = { | ||
74 | .hwport = 0, | ||
75 | .flags = 0, | ||
76 | .ucon = SMDK6440_UCON_DEFAULT, | ||
77 | .ulcon = SMDK6440_ULCON_DEFAULT, | ||
78 | .ufcon = SMDK6440_UFCON_DEFAULT, | ||
79 | }, | ||
80 | [1] = { | ||
81 | .hwport = 1, | ||
82 | .flags = 0, | ||
83 | .ucon = SMDK6440_UCON_DEFAULT, | ||
84 | .ulcon = SMDK6440_ULCON_DEFAULT, | ||
85 | .ufcon = SMDK6440_UFCON_DEFAULT, | ||
86 | }, | ||
87 | [2] = { | ||
88 | .hwport = 2, | ||
89 | .flags = 0, | ||
90 | .ucon = SMDK6440_UCON_DEFAULT, | ||
91 | .ulcon = SMDK6440_ULCON_DEFAULT, | ||
92 | .ufcon = SMDK6440_UFCON_DEFAULT, | ||
93 | }, | ||
94 | [3] = { | ||
95 | .hwport = 3, | ||
96 | .flags = 0, | ||
97 | .ucon = SMDK6440_UCON_DEFAULT, | ||
98 | .ulcon = SMDK6440_ULCON_DEFAULT, | ||
99 | .ufcon = SMDK6440_UFCON_DEFAULT, | ||
100 | }, | ||
101 | }; | ||
102 | |||
103 | /* Frame Buffer */ | ||
104 | static struct s3c_fb_pd_win smdk6440_fb_win0 = { | ||
105 | .max_bpp = 32, | ||
106 | .default_bpp = 24, | ||
107 | .xres = 800, | ||
108 | .yres = 480, | ||
109 | }; | ||
110 | |||
111 | static struct fb_videomode smdk6440_lcd_timing = { | ||
112 | .left_margin = 8, | ||
113 | .right_margin = 13, | ||
114 | .upper_margin = 7, | ||
115 | .lower_margin = 5, | ||
116 | .hsync_len = 3, | ||
117 | .vsync_len = 1, | ||
118 | .xres = 800, | ||
119 | .yres = 480, | ||
120 | }; | ||
121 | |||
122 | static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = { | ||
123 | .win[0] = &smdk6440_fb_win0, | ||
124 | .vtiming = &smdk6440_lcd_timing, | ||
125 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
126 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
127 | .setup_gpio = s5p64x0_fb_gpio_setup_24bpp, | ||
128 | }; | ||
129 | |||
130 | /* LCD power controller */ | ||
131 | static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd, | ||
132 | unsigned int power) | ||
133 | { | ||
134 | int err; | ||
135 | |||
136 | if (power) { | ||
137 | err = gpio_request(S5P6440_GPN(5), "GPN"); | ||
138 | if (err) { | ||
139 | printk(KERN_ERR "failed to request GPN for lcd reset\n"); | ||
140 | return; | ||
141 | } | ||
142 | |||
143 | gpio_direction_output(S5P6440_GPN(5), 1); | ||
144 | gpio_set_value(S5P6440_GPN(5), 0); | ||
145 | gpio_set_value(S5P6440_GPN(5), 1); | ||
146 | gpio_free(S5P6440_GPN(5)); | ||
147 | } | ||
148 | } | ||
149 | |||
150 | static struct plat_lcd_data smdk6440_lcd_power_data = { | ||
151 | .set_power = smdk6440_lte480_reset_power, | ||
152 | }; | ||
153 | |||
154 | static struct platform_device smdk6440_lcd_lte480wv = { | ||
155 | .name = "platform-lcd", | ||
156 | .dev.parent = &s3c_device_fb.dev, | ||
157 | .dev.platform_data = &smdk6440_lcd_power_data, | ||
158 | }; | ||
159 | |||
160 | static struct platform_device *smdk6440_devices[] __initdata = { | ||
161 | &s3c_device_adc, | ||
162 | &s3c_device_rtc, | ||
163 | &s3c_device_i2c0, | ||
164 | &s3c_device_i2c1, | ||
165 | &samsung_device_pwm, | ||
166 | &s3c_device_ts, | ||
167 | &s3c_device_wdt, | ||
168 | &s5p6440_device_iis, | ||
169 | &s3c_device_fb, | ||
170 | &smdk6440_lcd_lte480wv, | ||
171 | &s3c_device_hsmmc0, | ||
172 | &s3c_device_hsmmc1, | ||
173 | &s3c_device_hsmmc2, | ||
174 | }; | ||
175 | |||
176 | static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = { | ||
177 | .cd_type = S3C_SDHCI_CD_NONE, | ||
178 | }; | ||
179 | |||
180 | static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = { | ||
181 | .cd_type = S3C_SDHCI_CD_INTERNAL, | ||
182 | #if defined(CONFIG_S5P64X0_SD_CH1_8BIT) | ||
183 | .max_width = 8, | ||
184 | .host_caps = MMC_CAP_8_BIT_DATA, | ||
185 | #endif | ||
186 | }; | ||
187 | |||
188 | static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = { | ||
189 | .cd_type = S3C_SDHCI_CD_NONE, | ||
190 | }; | ||
191 | |||
192 | static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = { | ||
193 | .flags = 0, | ||
194 | .slave_addr = 0x10, | ||
195 | .frequency = 100*1000, | ||
196 | .sda_delay = 100, | ||
197 | .cfg_gpio = s5p6440_i2c0_cfg_gpio, | ||
198 | }; | ||
199 | |||
200 | static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = { | ||
201 | .flags = 0, | ||
202 | .bus_num = 1, | ||
203 | .slave_addr = 0x10, | ||
204 | .frequency = 100*1000, | ||
205 | .sda_delay = 100, | ||
206 | .cfg_gpio = s5p6440_i2c1_cfg_gpio, | ||
207 | }; | ||
208 | |||
209 | static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = { | ||
210 | { I2C_BOARD_INFO("24c08", 0x50), }, | ||
211 | { I2C_BOARD_INFO("wm8580", 0x1b), }, | ||
212 | }; | ||
213 | |||
214 | static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = { | ||
215 | /* To be populated */ | ||
216 | }; | ||
217 | |||
218 | /* LCD Backlight data */ | ||
219 | static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = { | ||
220 | .no = S5P6440_GPF(15), | ||
221 | .func = S3C_GPIO_SFN(2), | ||
222 | }; | ||
223 | |||
224 | static struct platform_pwm_backlight_data smdk6440_bl_data = { | ||
225 | .pwm_id = 1, | ||
226 | .enable_gpio = -1, | ||
227 | }; | ||
228 | |||
229 | static void __init smdk6440_map_io(void) | ||
230 | { | ||
231 | s5p64x0_init_io(NULL, 0); | ||
232 | s3c24xx_init_clocks(12000000); | ||
233 | s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs)); | ||
234 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | ||
235 | } | ||
236 | |||
237 | static void s5p6440_set_lcd_interface(void) | ||
238 | { | ||
239 | unsigned int cfg; | ||
240 | |||
241 | /* select TFT LCD type (RGB I/F) */ | ||
242 | cfg = __raw_readl(S5P64X0_SPCON0); | ||
243 | cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK; | ||
244 | cfg |= S5P64X0_SPCON0_LCD_SEL_RGB; | ||
245 | __raw_writel(cfg, S5P64X0_SPCON0); | ||
246 | } | ||
247 | |||
248 | static void __init smdk6440_machine_init(void) | ||
249 | { | ||
250 | s3c24xx_ts_set_platdata(NULL); | ||
251 | |||
252 | s3c_i2c0_set_platdata(&s5p6440_i2c0_data); | ||
253 | s3c_i2c1_set_platdata(&s5p6440_i2c1_data); | ||
254 | i2c_register_board_info(0, smdk6440_i2c_devs0, | ||
255 | ARRAY_SIZE(smdk6440_i2c_devs0)); | ||
256 | i2c_register_board_info(1, smdk6440_i2c_devs1, | ||
257 | ARRAY_SIZE(smdk6440_i2c_devs1)); | ||
258 | |||
259 | s5p6440_set_lcd_interface(); | ||
260 | s3c_fb_set_platdata(&smdk6440_lcd_pdata); | ||
261 | |||
262 | s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata); | ||
263 | s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata); | ||
264 | s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata); | ||
265 | |||
266 | platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices)); | ||
267 | |||
268 | samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data); | ||
269 | } | ||
270 | |||
271 | MACHINE_START(SMDK6440, "SMDK6440") | ||
272 | /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ | ||
273 | .atag_offset = 0x100, | ||
274 | |||
275 | .init_irq = s5p6440_init_irq, | ||
276 | .map_io = smdk6440_map_io, | ||
277 | .init_machine = smdk6440_machine_init, | ||
278 | .init_time = samsung_timer_init, | ||
279 | .restart = s5p64x0_restart, | ||
280 | MACHINE_END | ||
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c deleted file mode 100644 index fa1341c074ca..000000000000 --- a/arch/arm/mach-s5p64x0/mach-smdk6450.c +++ /dev/null | |||
@@ -1,299 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/kernel.h> | ||
12 | #include <linux/types.h> | ||
13 | #include <linux/interrupt.h> | ||
14 | #include <linux/list.h> | ||
15 | #include <linux/timer.h> | ||
16 | #include <linux/delay.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/i2c.h> | ||
19 | #include <linux/serial_core.h> | ||
20 | #include <linux/serial_s3c.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/module.h> | ||
24 | #include <linux/clk.h> | ||
25 | #include <linux/gpio.h> | ||
26 | #include <linux/pwm_backlight.h> | ||
27 | #include <linux/fb.h> | ||
28 | #include <linux/mmc/host.h> | ||
29 | |||
30 | #include <video/platform_lcd.h> | ||
31 | #include <video/samsung_fimd.h> | ||
32 | |||
33 | #include <asm/mach/arch.h> | ||
34 | #include <asm/mach/map.h> | ||
35 | #include <asm/irq.h> | ||
36 | #include <asm/mach-types.h> | ||
37 | |||
38 | #include <mach/hardware.h> | ||
39 | #include <mach/map.h> | ||
40 | #include <mach/regs-clock.h> | ||
41 | #include <mach/regs-gpio.h> | ||
42 | |||
43 | #include <plat/gpio-cfg.h> | ||
44 | #include <plat/clock.h> | ||
45 | #include <plat/devs.h> | ||
46 | #include <plat/cpu.h> | ||
47 | #include <linux/platform_data/i2c-s3c2410.h> | ||
48 | #include <plat/pll.h> | ||
49 | #include <plat/adc.h> | ||
50 | #include <linux/platform_data/touchscreen-s3c2410.h> | ||
51 | #include <plat/samsung-time.h> | ||
52 | #include <plat/backlight.h> | ||
53 | #include <plat/fb.h> | ||
54 | #include <plat/sdhci.h> | ||
55 | |||
56 | #include "common.h" | ||
57 | #include "i2c.h" | ||
58 | |||
59 | #define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | ||
60 | S3C2410_UCON_RXILEVEL | \ | ||
61 | S3C2410_UCON_TXIRQMODE | \ | ||
62 | S3C2410_UCON_RXIRQMODE | \ | ||
63 | S3C2410_UCON_RXFIFO_TOI | \ | ||
64 | S3C2443_UCON_RXERR_IRQEN) | ||
65 | |||
66 | #define SMDK6450_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
67 | |||
68 | #define SMDK6450_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
69 | S3C2440_UFCON_TXTRIG16 | \ | ||
70 | S3C2410_UFCON_RXTRIG8) | ||
71 | |||
72 | static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = { | ||
73 | [0] = { | ||
74 | .hwport = 0, | ||
75 | .flags = 0, | ||
76 | .ucon = SMDK6450_UCON_DEFAULT, | ||
77 | .ulcon = SMDK6450_ULCON_DEFAULT, | ||
78 | .ufcon = SMDK6450_UFCON_DEFAULT, | ||
79 | }, | ||
80 | [1] = { | ||
81 | .hwport = 1, | ||
82 | .flags = 0, | ||
83 | .ucon = SMDK6450_UCON_DEFAULT, | ||
84 | .ulcon = SMDK6450_ULCON_DEFAULT, | ||
85 | .ufcon = SMDK6450_UFCON_DEFAULT, | ||
86 | }, | ||
87 | [2] = { | ||
88 | .hwport = 2, | ||
89 | .flags = 0, | ||
90 | .ucon = SMDK6450_UCON_DEFAULT, | ||
91 | .ulcon = SMDK6450_ULCON_DEFAULT, | ||
92 | .ufcon = SMDK6450_UFCON_DEFAULT, | ||
93 | }, | ||
94 | [3] = { | ||
95 | .hwport = 3, | ||
96 | .flags = 0, | ||
97 | .ucon = SMDK6450_UCON_DEFAULT, | ||
98 | .ulcon = SMDK6450_ULCON_DEFAULT, | ||
99 | .ufcon = SMDK6450_UFCON_DEFAULT, | ||
100 | }, | ||
101 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 4 | ||
102 | [4] = { | ||
103 | .hwport = 4, | ||
104 | .flags = 0, | ||
105 | .ucon = SMDK6450_UCON_DEFAULT, | ||
106 | .ulcon = SMDK6450_ULCON_DEFAULT, | ||
107 | .ufcon = SMDK6450_UFCON_DEFAULT, | ||
108 | }, | ||
109 | #endif | ||
110 | #if CONFIG_SERIAL_SAMSUNG_UARTS > 5 | ||
111 | [5] = { | ||
112 | .hwport = 5, | ||
113 | .flags = 0, | ||
114 | .ucon = SMDK6450_UCON_DEFAULT, | ||
115 | .ulcon = SMDK6450_ULCON_DEFAULT, | ||
116 | .ufcon = SMDK6450_UFCON_DEFAULT, | ||
117 | }, | ||
118 | #endif | ||
119 | }; | ||
120 | |||
121 | /* Frame Buffer */ | ||
122 | static struct s3c_fb_pd_win smdk6450_fb_win0 = { | ||
123 | .max_bpp = 32, | ||
124 | .default_bpp = 24, | ||
125 | .xres = 800, | ||
126 | .yres = 480, | ||
127 | }; | ||
128 | |||
129 | static struct fb_videomode smdk6450_lcd_timing = { | ||
130 | .left_margin = 8, | ||
131 | .right_margin = 13, | ||
132 | .upper_margin = 7, | ||
133 | .lower_margin = 5, | ||
134 | .hsync_len = 3, | ||
135 | .vsync_len = 1, | ||
136 | .xres = 800, | ||
137 | .yres = 480, | ||
138 | }; | ||
139 | |||
140 | static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = { | ||
141 | .win[0] = &smdk6450_fb_win0, | ||
142 | .vtiming = &smdk6450_lcd_timing, | ||
143 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
144 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
145 | .setup_gpio = s5p64x0_fb_gpio_setup_24bpp, | ||
146 | }; | ||
147 | |||
148 | /* LCD power controller */ | ||
149 | static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd, | ||
150 | unsigned int power) | ||
151 | { | ||
152 | int err; | ||
153 | |||
154 | if (power) { | ||
155 | err = gpio_request(S5P6450_GPN(5), "GPN"); | ||
156 | if (err) { | ||
157 | printk(KERN_ERR "failed to request GPN for lcd reset\n"); | ||
158 | return; | ||
159 | } | ||
160 | |||
161 | gpio_direction_output(S5P6450_GPN(5), 1); | ||
162 | gpio_set_value(S5P6450_GPN(5), 0); | ||
163 | gpio_set_value(S5P6450_GPN(5), 1); | ||
164 | gpio_free(S5P6450_GPN(5)); | ||
165 | } | ||
166 | } | ||
167 | |||
168 | static struct plat_lcd_data smdk6450_lcd_power_data = { | ||
169 | .set_power = smdk6450_lte480_reset_power, | ||
170 | }; | ||
171 | |||
172 | static struct platform_device smdk6450_lcd_lte480wv = { | ||
173 | .name = "platform-lcd", | ||
174 | .dev.parent = &s3c_device_fb.dev, | ||
175 | .dev.platform_data = &smdk6450_lcd_power_data, | ||
176 | }; | ||
177 | |||
178 | static struct platform_device *smdk6450_devices[] __initdata = { | ||
179 | &s3c_device_adc, | ||
180 | &s3c_device_rtc, | ||
181 | &s3c_device_i2c0, | ||
182 | &s3c_device_i2c1, | ||
183 | &samsung_device_pwm, | ||
184 | &s3c_device_ts, | ||
185 | &s3c_device_wdt, | ||
186 | &s5p6450_device_iis0, | ||
187 | &s3c_device_fb, | ||
188 | &smdk6450_lcd_lte480wv, | ||
189 | &s3c_device_hsmmc0, | ||
190 | &s3c_device_hsmmc1, | ||
191 | &s3c_device_hsmmc2, | ||
192 | /* s5p6450_device_spi0 will be added */ | ||
193 | }; | ||
194 | |||
195 | static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = { | ||
196 | .cd_type = S3C_SDHCI_CD_NONE, | ||
197 | }; | ||
198 | |||
199 | static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = { | ||
200 | .cd_type = S3C_SDHCI_CD_NONE, | ||
201 | #if defined(CONFIG_S5P64X0_SD_CH1_8BIT) | ||
202 | .max_width = 8, | ||
203 | .host_caps = MMC_CAP_8_BIT_DATA, | ||
204 | #endif | ||
205 | }; | ||
206 | |||
207 | static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = { | ||
208 | .cd_type = S3C_SDHCI_CD_NONE, | ||
209 | }; | ||
210 | |||
211 | static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = { | ||
212 | .flags = 0, | ||
213 | .slave_addr = 0x10, | ||
214 | .frequency = 100*1000, | ||
215 | .sda_delay = 100, | ||
216 | .cfg_gpio = s5p6450_i2c0_cfg_gpio, | ||
217 | }; | ||
218 | |||
219 | static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = { | ||
220 | .flags = 0, | ||
221 | .bus_num = 1, | ||
222 | .slave_addr = 0x10, | ||
223 | .frequency = 100*1000, | ||
224 | .sda_delay = 100, | ||
225 | .cfg_gpio = s5p6450_i2c1_cfg_gpio, | ||
226 | }; | ||
227 | |||
228 | static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = { | ||
229 | { I2C_BOARD_INFO("wm8580", 0x1b), }, | ||
230 | { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */ | ||
231 | }; | ||
232 | |||
233 | static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = { | ||
234 | { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */ | ||
235 | }; | ||
236 | |||
237 | /* LCD Backlight data */ | ||
238 | static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = { | ||
239 | .no = S5P6450_GPF(15), | ||
240 | .func = S3C_GPIO_SFN(2), | ||
241 | }; | ||
242 | |||
243 | static struct platform_pwm_backlight_data smdk6450_bl_data = { | ||
244 | .pwm_id = 1, | ||
245 | .enable_gpio = -1, | ||
246 | }; | ||
247 | |||
248 | static void __init smdk6450_map_io(void) | ||
249 | { | ||
250 | s5p64x0_init_io(NULL, 0); | ||
251 | s3c24xx_init_clocks(19200000); | ||
252 | s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs)); | ||
253 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | ||
254 | } | ||
255 | |||
256 | static void s5p6450_set_lcd_interface(void) | ||
257 | { | ||
258 | unsigned int cfg; | ||
259 | |||
260 | /* select TFT LCD type (RGB I/F) */ | ||
261 | cfg = __raw_readl(S5P64X0_SPCON0); | ||
262 | cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK; | ||
263 | cfg |= S5P64X0_SPCON0_LCD_SEL_RGB; | ||
264 | __raw_writel(cfg, S5P64X0_SPCON0); | ||
265 | } | ||
266 | |||
267 | static void __init smdk6450_machine_init(void) | ||
268 | { | ||
269 | s3c24xx_ts_set_platdata(NULL); | ||
270 | |||
271 | s3c_i2c0_set_platdata(&s5p6450_i2c0_data); | ||
272 | s3c_i2c1_set_platdata(&s5p6450_i2c1_data); | ||
273 | i2c_register_board_info(0, smdk6450_i2c_devs0, | ||
274 | ARRAY_SIZE(smdk6450_i2c_devs0)); | ||
275 | i2c_register_board_info(1, smdk6450_i2c_devs1, | ||
276 | ARRAY_SIZE(smdk6450_i2c_devs1)); | ||
277 | |||
278 | s5p6450_set_lcd_interface(); | ||
279 | s3c_fb_set_platdata(&smdk6450_lcd_pdata); | ||
280 | |||
281 | s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata); | ||
282 | s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata); | ||
283 | s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata); | ||
284 | |||
285 | platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices)); | ||
286 | |||
287 | samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data); | ||
288 | } | ||
289 | |||
290 | MACHINE_START(SMDK6450, "SMDK6450") | ||
291 | /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */ | ||
292 | .atag_offset = 0x100, | ||
293 | |||
294 | .init_irq = s5p6450_init_irq, | ||
295 | .map_io = smdk6450_map_io, | ||
296 | .init_machine = smdk6450_machine_init, | ||
297 | .init_time = samsung_timer_init, | ||
298 | .restart = s5p64x0_restart, | ||
299 | MACHINE_END | ||
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c deleted file mode 100644 index ec8229cee716..000000000000 --- a/arch/arm/mach-s5p64x0/pm.c +++ /dev/null | |||
@@ -1,202 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/pm.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5P64X0 Power Management Support | ||
7 | * | ||
8 | * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/suspend.h> | ||
16 | #include <linux/syscore_ops.h> | ||
17 | #include <linux/io.h> | ||
18 | |||
19 | #include <plat/cpu.h> | ||
20 | #include <plat/pm.h> | ||
21 | #include <plat/wakeup-mask.h> | ||
22 | |||
23 | #include <mach/regs-clock.h> | ||
24 | #include <mach/regs-gpio.h> | ||
25 | |||
26 | static struct sleep_save s5p64x0_core_save[] = { | ||
27 | SAVE_ITEM(S5P64X0_APLL_CON), | ||
28 | SAVE_ITEM(S5P64X0_MPLL_CON), | ||
29 | SAVE_ITEM(S5P64X0_EPLL_CON), | ||
30 | SAVE_ITEM(S5P64X0_EPLL_CON_K), | ||
31 | SAVE_ITEM(S5P64X0_CLK_SRC0), | ||
32 | SAVE_ITEM(S5P64X0_CLK_SRC1), | ||
33 | SAVE_ITEM(S5P64X0_CLK_DIV0), | ||
34 | SAVE_ITEM(S5P64X0_CLK_DIV1), | ||
35 | SAVE_ITEM(S5P64X0_CLK_DIV2), | ||
36 | SAVE_ITEM(S5P64X0_CLK_DIV3), | ||
37 | SAVE_ITEM(S5P64X0_CLK_GATE_MEM0), | ||
38 | SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1), | ||
39 | SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1), | ||
40 | }; | ||
41 | |||
42 | static struct sleep_save s5p64x0_misc_save[] = { | ||
43 | SAVE_ITEM(S5P64X0_AHB_CON0), | ||
44 | SAVE_ITEM(S5P64X0_SPCON0), | ||
45 | SAVE_ITEM(S5P64X0_SPCON1), | ||
46 | SAVE_ITEM(S5P64X0_MEM0CONSLP0), | ||
47 | SAVE_ITEM(S5P64X0_MEM0CONSLP1), | ||
48 | SAVE_ITEM(S5P64X0_MEM0DRVCON), | ||
49 | SAVE_ITEM(S5P64X0_MEM1DRVCON), | ||
50 | }; | ||
51 | |||
52 | /* DPLL is present only in S5P6450 */ | ||
53 | static struct sleep_save s5p6450_core_save[] = { | ||
54 | SAVE_ITEM(S5P6450_DPLL_CON), | ||
55 | SAVE_ITEM(S5P6450_DPLL_CON_K), | ||
56 | }; | ||
57 | |||
58 | void s3c_pm_configure_extint(void) | ||
59 | { | ||
60 | __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK); | ||
61 | } | ||
62 | |||
63 | void s3c_pm_restore_core(void) | ||
64 | { | ||
65 | __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK); | ||
66 | |||
67 | s3c_pm_do_restore_core(s5p64x0_core_save, | ||
68 | ARRAY_SIZE(s5p64x0_core_save)); | ||
69 | |||
70 | if (soc_is_s5p6450()) | ||
71 | s3c_pm_do_restore_core(s5p6450_core_save, | ||
72 | ARRAY_SIZE(s5p6450_core_save)); | ||
73 | |||
74 | s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save)); | ||
75 | } | ||
76 | |||
77 | void s3c_pm_save_core(void) | ||
78 | { | ||
79 | s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save)); | ||
80 | |||
81 | if (soc_is_s5p6450()) | ||
82 | s3c_pm_do_save(s5p6450_core_save, | ||
83 | ARRAY_SIZE(s5p6450_core_save)); | ||
84 | |||
85 | s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save)); | ||
86 | } | ||
87 | |||
88 | static int s5p64x0_cpu_suspend(unsigned long arg) | ||
89 | { | ||
90 | unsigned long tmp = 0; | ||
91 | |||
92 | /* | ||
93 | * Issue the standby signal into the pm unit. Note, we | ||
94 | * issue a write-buffer drain just in case. | ||
95 | */ | ||
96 | asm("b 1f\n\t" | ||
97 | ".align 5\n\t" | ||
98 | "1:\n\t" | ||
99 | "mcr p15, 0, %0, c7, c10, 5\n\t" | ||
100 | "mcr p15, 0, %0, c7, c10, 4\n\t" | ||
101 | "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp)); | ||
102 | |||
103 | pr_info("Failed to suspend the system\n"); | ||
104 | return 1; /* Aborting suspend */ | ||
105 | } | ||
106 | |||
107 | /* mapping of interrupts to parts of the wakeup mask */ | ||
108 | static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = { | ||
109 | { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, }, | ||
110 | { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, }, | ||
111 | { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, }, | ||
112 | { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, }, | ||
113 | }; | ||
114 | |||
115 | static void s5p64x0_pm_prepare(void) | ||
116 | { | ||
117 | u32 tmp; | ||
118 | |||
119 | samsung_sync_wakemask(S5P64X0_PWR_CFG, | ||
120 | s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs)); | ||
121 | |||
122 | /* store the resume address in INFORM0 register */ | ||
123 | __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0); | ||
124 | |||
125 | /* setup clock gating for FIMGVG block */ | ||
126 | __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \ | ||
127 | (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1); | ||
128 | __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \ | ||
129 | (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1); | ||
130 | |||
131 | /* Configure the stabilization counter with wait time required */ | ||
132 | __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE); | ||
133 | |||
134 | /* set WFI to SLEEP mode configuration */ | ||
135 | tmp = __raw_readl(S5P64X0_SLEEP_CFG); | ||
136 | tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN); | ||
137 | __raw_writel(tmp, S5P64X0_SLEEP_CFG); | ||
138 | |||
139 | tmp = __raw_readl(S5P64X0_PWR_CFG); | ||
140 | tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK); | ||
141 | tmp |= S5P64X0_PWR_CFG_WFI_SLEEP; | ||
142 | __raw_writel(tmp, S5P64X0_PWR_CFG); | ||
143 | |||
144 | /* | ||
145 | * set OTHERS register to disable interrupt before going to | ||
146 | * sleep. This bit is present only in S5P6450, it is reserved | ||
147 | * in S5P6440. | ||
148 | */ | ||
149 | if (soc_is_s5p6450()) { | ||
150 | tmp = __raw_readl(S5P64X0_OTHERS); | ||
151 | tmp |= S5P6450_OTHERS_DISABLE_INT; | ||
152 | __raw_writel(tmp, S5P64X0_OTHERS); | ||
153 | } | ||
154 | |||
155 | /* ensure previous wakeup state is cleared before sleeping */ | ||
156 | __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT); | ||
157 | |||
158 | } | ||
159 | |||
160 | static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif) | ||
161 | { | ||
162 | pm_cpu_prep = s5p64x0_pm_prepare; | ||
163 | pm_cpu_sleep = s5p64x0_cpu_suspend; | ||
164 | |||
165 | return 0; | ||
166 | } | ||
167 | |||
168 | static struct subsys_interface s5p64x0_pm_interface = { | ||
169 | .name = "s5p64x0_pm", | ||
170 | .subsys = &s5p64x0_subsys, | ||
171 | .add_dev = s5p64x0_pm_add, | ||
172 | }; | ||
173 | |||
174 | static __init int s5p64x0_pm_drvinit(void) | ||
175 | { | ||
176 | s3c_pm_init(); | ||
177 | |||
178 | return subsys_interface_register(&s5p64x0_pm_interface); | ||
179 | } | ||
180 | arch_initcall(s5p64x0_pm_drvinit); | ||
181 | |||
182 | static void s5p64x0_pm_resume(void) | ||
183 | { | ||
184 | u32 tmp; | ||
185 | |||
186 | tmp = __raw_readl(S5P64X0_OTHERS); | ||
187 | tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \ | ||
188 | S5P64X0_OTHERS_RET_UART); | ||
189 | __raw_writel(tmp , S5P64X0_OTHERS); | ||
190 | } | ||
191 | |||
192 | static struct syscore_ops s5p64x0_pm_syscore_ops = { | ||
193 | .resume = s5p64x0_pm_resume, | ||
194 | }; | ||
195 | |||
196 | static __init int s5p64x0_pm_syscore_init(void) | ||
197 | { | ||
198 | register_syscore_ops(&s5p64x0_pm_syscore_ops); | ||
199 | |||
200 | return 0; | ||
201 | } | ||
202 | arch_initcall(s5p64x0_pm_syscore_init); | ||
diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c deleted file mode 100644 index f346ee4af54d..000000000000 --- a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Base S5P64X0 GPIO setup information for LCD framebuffer | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/fb.h> | ||
14 | #include <linux/gpio.h> | ||
15 | |||
16 | #include <plat/cpu.h> | ||
17 | #include <plat/fb.h> | ||
18 | #include <plat/gpio-cfg.h> | ||
19 | |||
20 | void s5p64x0_fb_gpio_setup_24bpp(void) | ||
21 | { | ||
22 | if (soc_is_s5p6440()) { | ||
23 | s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2)); | ||
24 | s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2)); | ||
25 | } else if (soc_is_s5p6450()) { | ||
26 | s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2)); | ||
27 | s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2)); | ||
28 | } | ||
29 | } | ||
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c deleted file mode 100644 index 569b76ac98cb..000000000000 --- a/arch/arm/mach-s5p64x0/setup-i2c0.c +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/setup-i2c0.c | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * I2C0 GPIO configuration. | ||
7 | * | ||
8 | * Based on plat-s3c64x0/setup-i2c0.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/gpio.h> | ||
18 | |||
19 | struct platform_device; /* don't need the contents */ | ||
20 | |||
21 | #include <plat/gpio-cfg.h> | ||
22 | #include <linux/platform_data/i2c-s3c2410.h> | ||
23 | |||
24 | #include "i2c.h" | ||
25 | |||
26 | void s5p6440_i2c0_cfg_gpio(struct platform_device *dev) | ||
27 | { | ||
28 | s3c_gpio_cfgall_range(S5P6440_GPB(5), 2, | ||
29 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
30 | } | ||
31 | |||
32 | void s5p6450_i2c0_cfg_gpio(struct platform_device *dev) | ||
33 | { | ||
34 | s3c_gpio_cfgall_range(S5P6450_GPB(5), 2, | ||
35 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
36 | } | ||
37 | |||
38 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) { } | ||
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c deleted file mode 100644 index 867374e6d0bc..000000000000 --- a/arch/arm/mach-s5p64x0/setup-i2c1.c +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64xx/setup-i2c1.c | ||
2 | * | ||
3 | * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * I2C1 GPIO configuration. | ||
7 | * | ||
8 | * Based on plat-s3c64xx/setup-i2c0.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/gpio.h> | ||
18 | |||
19 | struct platform_device; /* don't need the contents */ | ||
20 | |||
21 | #include <plat/gpio-cfg.h> | ||
22 | #include <linux/platform_data/i2c-s3c2410.h> | ||
23 | |||
24 | #include "i2c.h" | ||
25 | |||
26 | void s5p6440_i2c1_cfg_gpio(struct platform_device *dev) | ||
27 | { | ||
28 | s3c_gpio_cfgall_range(S5P6440_GPR(9), 2, | ||
29 | S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP); | ||
30 | } | ||
31 | |||
32 | void s5p6450_i2c1_cfg_gpio(struct platform_device *dev) | ||
33 | { | ||
34 | s3c_gpio_cfgall_range(S5P6450_GPR(9), 2, | ||
35 | S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP); | ||
36 | } | ||
37 | |||
38 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) { } | ||
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c deleted file mode 100644 index 8410af0d12bf..000000000000 --- a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c +++ /dev/null | |||
@@ -1,104 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/platform_device.h> | ||
14 | #include <linux/io.h> | ||
15 | #include <linux/gpio.h> | ||
16 | |||
17 | #include <mach/regs-gpio.h> | ||
18 | #include <mach/regs-clock.h> | ||
19 | |||
20 | #include <plat/gpio-cfg.h> | ||
21 | #include <plat/sdhci.h> | ||
22 | #include <plat/cpu.h> | ||
23 | |||
24 | void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | ||
25 | { | ||
26 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; | ||
27 | |||
28 | /* Set all the necessary GPG pins to special-function 2 */ | ||
29 | if (soc_is_s5p6450()) | ||
30 | s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width, | ||
31 | S3C_GPIO_SFN(2)); | ||
32 | else | ||
33 | s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width, | ||
34 | S3C_GPIO_SFN(2)); | ||
35 | |||
36 | /* Set GPG[6] pin to special-function 2 - MMC0 CDn */ | ||
37 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | ||
38 | if (soc_is_s5p6450()) { | ||
39 | s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP); | ||
40 | s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2)); | ||
41 | } else { | ||
42 | s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP); | ||
43 | s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2)); | ||
44 | } | ||
45 | } | ||
46 | } | ||
47 | |||
48 | void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | ||
49 | { | ||
50 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; | ||
51 | |||
52 | /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */ | ||
53 | if (soc_is_s5p6450()) | ||
54 | s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2)); | ||
55 | else | ||
56 | s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2)); | ||
57 | |||
58 | switch (width) { | ||
59 | case 8: | ||
60 | /* Set data pins GPH[6:9] special-function 2 */ | ||
61 | if (soc_is_s5p6450()) | ||
62 | s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4, | ||
63 | S3C_GPIO_SFN(2)); | ||
64 | else | ||
65 | s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, | ||
66 | S3C_GPIO_SFN(2)); | ||
67 | case 4: | ||
68 | /* set data pins GPH[2:5] special-function 2 */ | ||
69 | if (soc_is_s5p6450()) | ||
70 | s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4, | ||
71 | S3C_GPIO_SFN(2)); | ||
72 | else | ||
73 | s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4, | ||
74 | S3C_GPIO_SFN(2)); | ||
75 | default: | ||
76 | break; | ||
77 | } | ||
78 | |||
79 | /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */ | ||
80 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | ||
81 | if (soc_is_s5p6450()) { | ||
82 | s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP); | ||
83 | s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3)); | ||
84 | } else { | ||
85 | s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP); | ||
86 | s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3)); | ||
87 | } | ||
88 | } | ||
89 | } | ||
90 | |||
91 | void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) | ||
92 | { | ||
93 | /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */ | ||
94 | s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3)); | ||
95 | |||
96 | /* Set data pins GPH[6:9] pins to special-function 3 */ | ||
97 | s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3)); | ||
98 | } | ||
99 | |||
100 | void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) | ||
101 | { | ||
102 | /* Set all the necessary GPG pins to special-function 3 */ | ||
103 | s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3)); | ||
104 | } | ||
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c deleted file mode 100644 index 7664356720ca..000000000000 --- a/arch/arm/mach-s5p64x0/setup-spi.c +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5p64x0/setup-spi.c | ||
2 | * | ||
3 | * Copyright (C) 2011 Samsung Electronics Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/gpio.h> | ||
12 | #include <plat/gpio-cfg.h> | ||
13 | |||
14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | ||
15 | int s3c64xx_spi0_cfg_gpio(void) | ||
16 | { | ||
17 | if (soc_is_s5p6450()) | ||
18 | s3c_gpio_cfgall_range(S5P6450_GPC(0), 3, | ||
19 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
20 | else | ||
21 | s3c_gpio_cfgall_range(S5P6440_GPC(0), 3, | ||
22 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
23 | return 0; | ||
24 | } | ||
25 | #endif | ||
26 | |||
27 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | ||
28 | int s3c64xx_spi1_cfg_gpio(void) | ||
29 | { | ||
30 | if (soc_is_s5p6450()) | ||
31 | s3c_gpio_cfgall_range(S5P6450_GPC(4), 3, | ||
32 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
33 | else | ||
34 | s3c_gpio_cfgall_range(S5P6440_GPC(4), 3, | ||
35 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
36 | return 0; | ||
37 | } | ||
38 | #endif | ||
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig deleted file mode 100644 index c5e3a969b063..000000000000 --- a/arch/arm/mach-s5pc100/Kconfig +++ /dev/null | |||
@@ -1,81 +0,0 @@ | |||
1 | # Copyright 2009 Samsung Electronics Co. | ||
2 | # Byungho Min <bhmin@samsung.com> | ||
3 | # | ||
4 | # Licensed under GPLv2 | ||
5 | |||
6 | # Configuration options for the S5PC100 CPU | ||
7 | |||
8 | if ARCH_S5PC100 | ||
9 | |||
10 | config CPU_S5PC100 | ||
11 | bool | ||
12 | select ARM_AMBA | ||
13 | select PL330_DMA if DMADEVICES | ||
14 | select S5P_EXT_INT | ||
15 | help | ||
16 | Enable S5PC100 CPU support | ||
17 | |||
18 | config S5PC100_SETUP_FB_24BPP | ||
19 | bool | ||
20 | help | ||
21 | Common setup code for S5PC1XX with an 24bpp RGB display helper. | ||
22 | |||
23 | config S5PC100_SETUP_I2C1 | ||
24 | bool | ||
25 | help | ||
26 | Common setup code for i2c bus 1. | ||
27 | |||
28 | config S5PC100_SETUP_IDE | ||
29 | bool | ||
30 | help | ||
31 | Common setup code for S5PC100 IDE GPIO configurations | ||
32 | |||
33 | config S5PC100_SETUP_KEYPAD | ||
34 | bool | ||
35 | help | ||
36 | Common setup code for KEYPAD GPIO configurations. | ||
37 | |||
38 | config S5PC100_SETUP_SDHCI | ||
39 | bool | ||
40 | select S5PC100_SETUP_SDHCI_GPIO | ||
41 | help | ||
42 | Internal helper functions for S5PC100 based SDHCI systems | ||
43 | |||
44 | config S5PC100_SETUP_SDHCI_GPIO | ||
45 | bool | ||
46 | help | ||
47 | Common setup code for SDHCI gpio. | ||
48 | |||
49 | config S5PC100_SETUP_SPI | ||
50 | bool | ||
51 | help | ||
52 | Common setup code for SPI GPIO configurations. | ||
53 | |||
54 | config MACH_SMDKC100 | ||
55 | bool "SMDKC100" | ||
56 | select CPU_S5PC100 | ||
57 | select S3C_DEV_FB | ||
58 | select S3C_DEV_HSMMC | ||
59 | select S3C_DEV_HSMMC1 | ||
60 | select S3C_DEV_HSMMC2 | ||
61 | select S3C_DEV_I2C1 | ||
62 | select S3C_DEV_RTC | ||
63 | select S3C_DEV_WDT | ||
64 | select S5PC100_SETUP_FB_24BPP | ||
65 | select S5PC100_SETUP_I2C1 | ||
66 | select S5PC100_SETUP_IDE | ||
67 | select S5PC100_SETUP_KEYPAD | ||
68 | select S5PC100_SETUP_SDHCI | ||
69 | select S5P_DEV_FIMC0 | ||
70 | select S5P_DEV_FIMC1 | ||
71 | select S5P_DEV_FIMC2 | ||
72 | select SAMSUNG_DEV_ADC | ||
73 | select SAMSUNG_DEV_BACKLIGHT | ||
74 | select SAMSUNG_DEV_IDE | ||
75 | select SAMSUNG_DEV_KEYPAD | ||
76 | select SAMSUNG_DEV_PWM | ||
77 | select SAMSUNG_DEV_TS | ||
78 | help | ||
79 | Machine support for the Samsung SMDKC100 | ||
80 | |||
81 | endif | ||
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile deleted file mode 100644 index 118c711f74e8..000000000000 --- a/arch/arm/mach-s5pc100/Makefile +++ /dev/null | |||
@@ -1,32 +0,0 @@ | |||
1 | # arch/arm/mach-s5pc100/Makefile | ||
2 | # | ||
3 | # Copyright 2009 Samsung Electronics Co. | ||
4 | # | ||
5 | # Licensed under GPLv2 | ||
6 | |||
7 | obj-y := | ||
8 | obj-m := | ||
9 | obj-n := | ||
10 | obj- := | ||
11 | |||
12 | # Core | ||
13 | |||
14 | obj-y += common.o clock.o | ||
15 | |||
16 | obj-y += dma.o | ||
17 | |||
18 | # machine support | ||
19 | |||
20 | obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o | ||
21 | |||
22 | # device support | ||
23 | |||
24 | obj-y += dev-audio.o | ||
25 | |||
26 | obj-y += setup-i2c0.o | ||
27 | obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o | ||
28 | obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o | ||
29 | obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o | ||
30 | obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o | ||
31 | obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o | ||
32 | obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o | ||
diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot deleted file mode 100644 index 79ece4055b02..000000000000 --- a/arch/arm/mach-s5pc100/Makefile.boot +++ /dev/null | |||
@@ -1,2 +0,0 @@ | |||
1 | zreladdr-y += 0x20008000 | ||
2 | params_phys-y := 0x20000100 | ||
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c deleted file mode 100644 index d0dc10ee7729..000000000000 --- a/arch/arm/mach-s5pc100/clock.c +++ /dev/null | |||
@@ -1,1361 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/clock.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5PC100 - Clock support | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/list.h> | ||
17 | #include <linux/err.h> | ||
18 | #include <linux/clk.h> | ||
19 | #include <linux/io.h> | ||
20 | |||
21 | #include <mach/map.h> | ||
22 | |||
23 | #include <plat/cpu-freq.h> | ||
24 | #include <mach/regs-clock.h> | ||
25 | #include <plat/clock.h> | ||
26 | #include <plat/cpu.h> | ||
27 | #include <plat/pll.h> | ||
28 | #include <plat/s5p-clock.h> | ||
29 | #include <plat/clock-clksrc.h> | ||
30 | |||
31 | #include "common.h" | ||
32 | |||
33 | static struct clk s5p_clk_otgphy = { | ||
34 | .name = "otg_phy", | ||
35 | }; | ||
36 | |||
37 | static struct clk dummy_apb_pclk = { | ||
38 | .name = "apb_pclk", | ||
39 | .id = -1, | ||
40 | }; | ||
41 | |||
42 | static struct clk *clk_src_mout_href_list[] = { | ||
43 | [0] = &s5p_clk_27m, | ||
44 | [1] = &clk_fin_hpll, | ||
45 | }; | ||
46 | |||
47 | static struct clksrc_sources clk_src_mout_href = { | ||
48 | .sources = clk_src_mout_href_list, | ||
49 | .nr_sources = ARRAY_SIZE(clk_src_mout_href_list), | ||
50 | }; | ||
51 | |||
52 | static struct clksrc_clk clk_mout_href = { | ||
53 | .clk = { | ||
54 | .name = "mout_href", | ||
55 | }, | ||
56 | .sources = &clk_src_mout_href, | ||
57 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 }, | ||
58 | }; | ||
59 | |||
60 | static struct clk *clk_src_mout_48m_list[] = { | ||
61 | [0] = &clk_xusbxti, | ||
62 | [1] = &s5p_clk_otgphy, | ||
63 | }; | ||
64 | |||
65 | static struct clksrc_sources clk_src_mout_48m = { | ||
66 | .sources = clk_src_mout_48m_list, | ||
67 | .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list), | ||
68 | }; | ||
69 | |||
70 | static struct clksrc_clk clk_mout_48m = { | ||
71 | .clk = { | ||
72 | .name = "mout_48m", | ||
73 | }, | ||
74 | .sources = &clk_src_mout_48m, | ||
75 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 }, | ||
76 | }; | ||
77 | |||
78 | static struct clksrc_clk clk_mout_mpll = { | ||
79 | .clk = { | ||
80 | .name = "mout_mpll", | ||
81 | }, | ||
82 | .sources = &clk_src_mpll, | ||
83 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 }, | ||
84 | }; | ||
85 | |||
86 | |||
87 | static struct clksrc_clk clk_mout_apll = { | ||
88 | .clk = { | ||
89 | .name = "mout_apll", | ||
90 | }, | ||
91 | .sources = &clk_src_apll, | ||
92 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 }, | ||
93 | }; | ||
94 | |||
95 | static struct clksrc_clk clk_mout_epll = { | ||
96 | .clk = { | ||
97 | .name = "mout_epll", | ||
98 | }, | ||
99 | .sources = &clk_src_epll, | ||
100 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 }, | ||
101 | }; | ||
102 | |||
103 | static struct clk *clk_src_mout_hpll_list[] = { | ||
104 | [0] = &s5p_clk_27m, | ||
105 | }; | ||
106 | |||
107 | static struct clksrc_sources clk_src_mout_hpll = { | ||
108 | .sources = clk_src_mout_hpll_list, | ||
109 | .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list), | ||
110 | }; | ||
111 | |||
112 | static struct clksrc_clk clk_mout_hpll = { | ||
113 | .clk = { | ||
114 | .name = "mout_hpll", | ||
115 | }, | ||
116 | .sources = &clk_src_mout_hpll, | ||
117 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 }, | ||
118 | }; | ||
119 | |||
120 | static struct clksrc_clk clk_div_apll = { | ||
121 | .clk = { | ||
122 | .name = "div_apll", | ||
123 | .parent = &clk_mout_apll.clk, | ||
124 | }, | ||
125 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 }, | ||
126 | }; | ||
127 | |||
128 | static struct clksrc_clk clk_div_arm = { | ||
129 | .clk = { | ||
130 | .name = "div_arm", | ||
131 | .parent = &clk_div_apll.clk, | ||
132 | }, | ||
133 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 }, | ||
134 | }; | ||
135 | |||
136 | static struct clksrc_clk clk_div_d0_bus = { | ||
137 | .clk = { | ||
138 | .name = "div_d0_bus", | ||
139 | .parent = &clk_div_arm.clk, | ||
140 | }, | ||
141 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 }, | ||
142 | }; | ||
143 | |||
144 | static struct clksrc_clk clk_div_pclkd0 = { | ||
145 | .clk = { | ||
146 | .name = "div_pclkd0", | ||
147 | .parent = &clk_div_d0_bus.clk, | ||
148 | }, | ||
149 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 }, | ||
150 | }; | ||
151 | |||
152 | static struct clksrc_clk clk_div_secss = { | ||
153 | .clk = { | ||
154 | .name = "div_secss", | ||
155 | .parent = &clk_div_d0_bus.clk, | ||
156 | }, | ||
157 | .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 }, | ||
158 | }; | ||
159 | |||
160 | static struct clksrc_clk clk_div_apll2 = { | ||
161 | .clk = { | ||
162 | .name = "div_apll2", | ||
163 | .parent = &clk_mout_apll.clk, | ||
164 | }, | ||
165 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 }, | ||
166 | }; | ||
167 | |||
168 | static struct clk *clk_src_mout_am_list[] = { | ||
169 | [0] = &clk_mout_mpll.clk, | ||
170 | [1] = &clk_div_apll2.clk, | ||
171 | }; | ||
172 | |||
173 | static struct clksrc_sources clk_src_mout_am = { | ||
174 | .sources = clk_src_mout_am_list, | ||
175 | .nr_sources = ARRAY_SIZE(clk_src_mout_am_list), | ||
176 | }; | ||
177 | |||
178 | static struct clksrc_clk clk_mout_am = { | ||
179 | .clk = { | ||
180 | .name = "mout_am", | ||
181 | }, | ||
182 | .sources = &clk_src_mout_am, | ||
183 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 }, | ||
184 | }; | ||
185 | |||
186 | static struct clksrc_clk clk_div_d1_bus = { | ||
187 | .clk = { | ||
188 | .name = "div_d1_bus", | ||
189 | .parent = &clk_mout_am.clk, | ||
190 | }, | ||
191 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 }, | ||
192 | }; | ||
193 | |||
194 | static struct clksrc_clk clk_div_mpll2 = { | ||
195 | .clk = { | ||
196 | .name = "div_mpll2", | ||
197 | .parent = &clk_mout_am.clk, | ||
198 | }, | ||
199 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 }, | ||
200 | }; | ||
201 | |||
202 | static struct clksrc_clk clk_div_mpll = { | ||
203 | .clk = { | ||
204 | .name = "div_mpll", | ||
205 | .parent = &clk_mout_am.clk, | ||
206 | }, | ||
207 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 }, | ||
208 | }; | ||
209 | |||
210 | static struct clk *clk_src_mout_onenand_list[] = { | ||
211 | [0] = &clk_div_d0_bus.clk, | ||
212 | [1] = &clk_div_d1_bus.clk, | ||
213 | }; | ||
214 | |||
215 | static struct clksrc_sources clk_src_mout_onenand = { | ||
216 | .sources = clk_src_mout_onenand_list, | ||
217 | .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list), | ||
218 | }; | ||
219 | |||
220 | static struct clksrc_clk clk_mout_onenand = { | ||
221 | .clk = { | ||
222 | .name = "mout_onenand", | ||
223 | }, | ||
224 | .sources = &clk_src_mout_onenand, | ||
225 | .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 }, | ||
226 | }; | ||
227 | |||
228 | static struct clksrc_clk clk_div_onenand = { | ||
229 | .clk = { | ||
230 | .name = "div_onenand", | ||
231 | .parent = &clk_mout_onenand.clk, | ||
232 | }, | ||
233 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 }, | ||
234 | }; | ||
235 | |||
236 | static struct clksrc_clk clk_div_pclkd1 = { | ||
237 | .clk = { | ||
238 | .name = "div_pclkd1", | ||
239 | .parent = &clk_div_d1_bus.clk, | ||
240 | }, | ||
241 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 }, | ||
242 | }; | ||
243 | |||
244 | static struct clksrc_clk clk_div_cam = { | ||
245 | .clk = { | ||
246 | .name = "div_cam", | ||
247 | .parent = &clk_div_mpll2.clk, | ||
248 | }, | ||
249 | .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 }, | ||
250 | }; | ||
251 | |||
252 | static struct clksrc_clk clk_div_hdmi = { | ||
253 | .clk = { | ||
254 | .name = "div_hdmi", | ||
255 | .parent = &clk_mout_hpll.clk, | ||
256 | }, | ||
257 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 }, | ||
258 | }; | ||
259 | |||
260 | static u32 epll_div[][4] = { | ||
261 | { 32750000, 131, 3, 4 }, | ||
262 | { 32768000, 131, 3, 4 }, | ||
263 | { 36000000, 72, 3, 3 }, | ||
264 | { 45000000, 90, 3, 3 }, | ||
265 | { 45158000, 90, 3, 3 }, | ||
266 | { 45158400, 90, 3, 3 }, | ||
267 | { 48000000, 96, 3, 3 }, | ||
268 | { 49125000, 131, 4, 3 }, | ||
269 | { 49152000, 131, 4, 3 }, | ||
270 | { 60000000, 120, 3, 3 }, | ||
271 | { 67737600, 226, 5, 3 }, | ||
272 | { 67738000, 226, 5, 3 }, | ||
273 | { 73800000, 246, 5, 3 }, | ||
274 | { 73728000, 246, 5, 3 }, | ||
275 | { 72000000, 144, 3, 3 }, | ||
276 | { 84000000, 168, 3, 3 }, | ||
277 | { 96000000, 96, 3, 2 }, | ||
278 | { 144000000, 144, 3, 2 }, | ||
279 | { 192000000, 96, 3, 1 } | ||
280 | }; | ||
281 | |||
282 | static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate) | ||
283 | { | ||
284 | unsigned int epll_con; | ||
285 | unsigned int i; | ||
286 | |||
287 | if (clk->rate == rate) /* Return if nothing changed */ | ||
288 | return 0; | ||
289 | |||
290 | epll_con = __raw_readl(S5P_EPLL_CON); | ||
291 | |||
292 | epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK); | ||
293 | |||
294 | for (i = 0; i < ARRAY_SIZE(epll_div); i++) { | ||
295 | if (epll_div[i][0] == rate) { | ||
296 | epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) | | ||
297 | (epll_div[i][2] << PLL65XX_PDIV_SHIFT) | | ||
298 | (epll_div[i][3] << PLL65XX_SDIV_SHIFT); | ||
299 | break; | ||
300 | } | ||
301 | } | ||
302 | |||
303 | if (i == ARRAY_SIZE(epll_div)) { | ||
304 | printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__); | ||
305 | return -EINVAL; | ||
306 | } | ||
307 | |||
308 | __raw_writel(epll_con, S5P_EPLL_CON); | ||
309 | |||
310 | printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n", | ||
311 | clk->rate, rate); | ||
312 | |||
313 | clk->rate = rate; | ||
314 | |||
315 | return 0; | ||
316 | } | ||
317 | |||
318 | static struct clk_ops s5pc100_epll_ops = { | ||
319 | .get_rate = s5p_epll_get_rate, | ||
320 | .set_rate = s5pc100_epll_set_rate, | ||
321 | }; | ||
322 | |||
323 | static int s5pc100_d0_0_ctrl(struct clk *clk, int enable) | ||
324 | { | ||
325 | return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable); | ||
326 | } | ||
327 | |||
328 | static int s5pc100_d0_1_ctrl(struct clk *clk, int enable) | ||
329 | { | ||
330 | return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable); | ||
331 | } | ||
332 | |||
333 | static int s5pc100_d0_2_ctrl(struct clk *clk, int enable) | ||
334 | { | ||
335 | return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable); | ||
336 | } | ||
337 | |||
338 | static int s5pc100_d1_0_ctrl(struct clk *clk, int enable) | ||
339 | { | ||
340 | return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable); | ||
341 | } | ||
342 | |||
343 | static int s5pc100_d1_1_ctrl(struct clk *clk, int enable) | ||
344 | { | ||
345 | return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable); | ||
346 | } | ||
347 | |||
348 | static int s5pc100_d1_2_ctrl(struct clk *clk, int enable) | ||
349 | { | ||
350 | return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable); | ||
351 | } | ||
352 | |||
353 | static int s5pc100_d1_3_ctrl(struct clk *clk, int enable) | ||
354 | { | ||
355 | return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable); | ||
356 | } | ||
357 | |||
358 | static int s5pc100_d1_4_ctrl(struct clk *clk, int enable) | ||
359 | { | ||
360 | return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable); | ||
361 | } | ||
362 | |||
363 | static int s5pc100_d1_5_ctrl(struct clk *clk, int enable) | ||
364 | { | ||
365 | return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable); | ||
366 | } | ||
367 | |||
368 | static int s5pc100_sclk0_ctrl(struct clk *clk, int enable) | ||
369 | { | ||
370 | return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable); | ||
371 | } | ||
372 | |||
373 | static int s5pc100_sclk1_ctrl(struct clk *clk, int enable) | ||
374 | { | ||
375 | return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable); | ||
376 | } | ||
377 | |||
378 | /* | ||
379 | * The following clocks will be disabled during clock initialization. It is | ||
380 | * recommended to keep the following clocks disabled until the driver requests | ||
381 | * for enabling the clock. | ||
382 | */ | ||
383 | static struct clk init_clocks_off[] = { | ||
384 | { | ||
385 | .name = "cssys", | ||
386 | .parent = &clk_div_d0_bus.clk, | ||
387 | .enable = s5pc100_d0_0_ctrl, | ||
388 | .ctrlbit = (1 << 6), | ||
389 | }, { | ||
390 | .name = "secss", | ||
391 | .parent = &clk_div_d0_bus.clk, | ||
392 | .enable = s5pc100_d0_0_ctrl, | ||
393 | .ctrlbit = (1 << 5), | ||
394 | }, { | ||
395 | .name = "g2d", | ||
396 | .parent = &clk_div_d0_bus.clk, | ||
397 | .enable = s5pc100_d0_0_ctrl, | ||
398 | .ctrlbit = (1 << 4), | ||
399 | }, { | ||
400 | .name = "mdma", | ||
401 | .parent = &clk_div_d0_bus.clk, | ||
402 | .enable = s5pc100_d0_0_ctrl, | ||
403 | .ctrlbit = (1 << 3), | ||
404 | }, { | ||
405 | .name = "cfcon", | ||
406 | .parent = &clk_div_d0_bus.clk, | ||
407 | .enable = s5pc100_d0_0_ctrl, | ||
408 | .ctrlbit = (1 << 2), | ||
409 | }, { | ||
410 | .name = "nfcon", | ||
411 | .parent = &clk_div_d0_bus.clk, | ||
412 | .enable = s5pc100_d0_1_ctrl, | ||
413 | .ctrlbit = (1 << 3), | ||
414 | }, { | ||
415 | .name = "onenandc", | ||
416 | .parent = &clk_div_d0_bus.clk, | ||
417 | .enable = s5pc100_d0_1_ctrl, | ||
418 | .ctrlbit = (1 << 2), | ||
419 | }, { | ||
420 | .name = "sdm", | ||
421 | .parent = &clk_div_d0_bus.clk, | ||
422 | .enable = s5pc100_d0_2_ctrl, | ||
423 | .ctrlbit = (1 << 2), | ||
424 | }, { | ||
425 | .name = "seckey", | ||
426 | .parent = &clk_div_d0_bus.clk, | ||
427 | .enable = s5pc100_d0_2_ctrl, | ||
428 | .ctrlbit = (1 << 1), | ||
429 | }, { | ||
430 | .name = "modemif", | ||
431 | .parent = &clk_div_d1_bus.clk, | ||
432 | .enable = s5pc100_d1_0_ctrl, | ||
433 | .ctrlbit = (1 << 4), | ||
434 | }, { | ||
435 | .name = "otg", | ||
436 | .parent = &clk_div_d1_bus.clk, | ||
437 | .enable = s5pc100_d1_0_ctrl, | ||
438 | .ctrlbit = (1 << 3), | ||
439 | }, { | ||
440 | .name = "usbhost", | ||
441 | .parent = &clk_div_d1_bus.clk, | ||
442 | .enable = s5pc100_d1_0_ctrl, | ||
443 | .ctrlbit = (1 << 2), | ||
444 | }, { | ||
445 | .name = "dma", | ||
446 | .devname = "dma-pl330.1", | ||
447 | .parent = &clk_div_d1_bus.clk, | ||
448 | .enable = s5pc100_d1_0_ctrl, | ||
449 | .ctrlbit = (1 << 1), | ||
450 | }, { | ||
451 | .name = "dma", | ||
452 | .devname = "dma-pl330.0", | ||
453 | .parent = &clk_div_d1_bus.clk, | ||
454 | .enable = s5pc100_d1_0_ctrl, | ||
455 | .ctrlbit = (1 << 0), | ||
456 | }, { | ||
457 | .name = "lcd", | ||
458 | .parent = &clk_div_d1_bus.clk, | ||
459 | .enable = s5pc100_d1_1_ctrl, | ||
460 | .ctrlbit = (1 << 0), | ||
461 | }, { | ||
462 | .name = "rotator", | ||
463 | .parent = &clk_div_d1_bus.clk, | ||
464 | .enable = s5pc100_d1_1_ctrl, | ||
465 | .ctrlbit = (1 << 1), | ||
466 | }, { | ||
467 | .name = "fimc", | ||
468 | .devname = "s5p-fimc.0", | ||
469 | .parent = &clk_div_d1_bus.clk, | ||
470 | .enable = s5pc100_d1_1_ctrl, | ||
471 | .ctrlbit = (1 << 2), | ||
472 | }, { | ||
473 | .name = "fimc", | ||
474 | .devname = "s5p-fimc.1", | ||
475 | .parent = &clk_div_d1_bus.clk, | ||
476 | .enable = s5pc100_d1_1_ctrl, | ||
477 | .ctrlbit = (1 << 3), | ||
478 | }, { | ||
479 | .name = "fimc", | ||
480 | .devname = "s5p-fimc.2", | ||
481 | .enable = s5pc100_d1_1_ctrl, | ||
482 | .ctrlbit = (1 << 4), | ||
483 | }, { | ||
484 | .name = "jpeg", | ||
485 | .parent = &clk_div_d1_bus.clk, | ||
486 | .enable = s5pc100_d1_1_ctrl, | ||
487 | .ctrlbit = (1 << 5), | ||
488 | }, { | ||
489 | .name = "mipi-dsim", | ||
490 | .parent = &clk_div_d1_bus.clk, | ||
491 | .enable = s5pc100_d1_1_ctrl, | ||
492 | .ctrlbit = (1 << 6), | ||
493 | }, { | ||
494 | .name = "mipi-csis", | ||
495 | .parent = &clk_div_d1_bus.clk, | ||
496 | .enable = s5pc100_d1_1_ctrl, | ||
497 | .ctrlbit = (1 << 7), | ||
498 | }, { | ||
499 | .name = "g3d", | ||
500 | .parent = &clk_div_d1_bus.clk, | ||
501 | .enable = s5pc100_d1_0_ctrl, | ||
502 | .ctrlbit = (1 << 8), | ||
503 | }, { | ||
504 | .name = "tv", | ||
505 | .parent = &clk_div_d1_bus.clk, | ||
506 | .enable = s5pc100_d1_2_ctrl, | ||
507 | .ctrlbit = (1 << 0), | ||
508 | }, { | ||
509 | .name = "vp", | ||
510 | .parent = &clk_div_d1_bus.clk, | ||
511 | .enable = s5pc100_d1_2_ctrl, | ||
512 | .ctrlbit = (1 << 1), | ||
513 | }, { | ||
514 | .name = "mixer", | ||
515 | .parent = &clk_div_d1_bus.clk, | ||
516 | .enable = s5pc100_d1_2_ctrl, | ||
517 | .ctrlbit = (1 << 2), | ||
518 | }, { | ||
519 | .name = "hdmi", | ||
520 | .parent = &clk_div_d1_bus.clk, | ||
521 | .enable = s5pc100_d1_2_ctrl, | ||
522 | .ctrlbit = (1 << 3), | ||
523 | }, { | ||
524 | .name = "mfc", | ||
525 | .parent = &clk_div_d1_bus.clk, | ||
526 | .enable = s5pc100_d1_2_ctrl, | ||
527 | .ctrlbit = (1 << 4), | ||
528 | }, { | ||
529 | .name = "apc", | ||
530 | .parent = &clk_div_d1_bus.clk, | ||
531 | .enable = s5pc100_d1_3_ctrl, | ||
532 | .ctrlbit = (1 << 2), | ||
533 | }, { | ||
534 | .name = "iec", | ||
535 | .parent = &clk_div_d1_bus.clk, | ||
536 | .enable = s5pc100_d1_3_ctrl, | ||
537 | .ctrlbit = (1 << 3), | ||
538 | }, { | ||
539 | .name = "systimer", | ||
540 | .parent = &clk_div_d1_bus.clk, | ||
541 | .enable = s5pc100_d1_3_ctrl, | ||
542 | .ctrlbit = (1 << 7), | ||
543 | }, { | ||
544 | .name = "watchdog", | ||
545 | .parent = &clk_div_d1_bus.clk, | ||
546 | .enable = s5pc100_d1_3_ctrl, | ||
547 | .ctrlbit = (1 << 8), | ||
548 | }, { | ||
549 | .name = "rtc", | ||
550 | .parent = &clk_div_d1_bus.clk, | ||
551 | .enable = s5pc100_d1_3_ctrl, | ||
552 | .ctrlbit = (1 << 9), | ||
553 | }, { | ||
554 | .name = "i2c", | ||
555 | .devname = "s3c2440-i2c.0", | ||
556 | .parent = &clk_div_d1_bus.clk, | ||
557 | .enable = s5pc100_d1_4_ctrl, | ||
558 | .ctrlbit = (1 << 4), | ||
559 | }, { | ||
560 | .name = "i2c", | ||
561 | .devname = "s3c2440-i2c.1", | ||
562 | .parent = &clk_div_d1_bus.clk, | ||
563 | .enable = s5pc100_d1_4_ctrl, | ||
564 | .ctrlbit = (1 << 5), | ||
565 | }, { | ||
566 | .name = "spi", | ||
567 | .devname = "s5pc100-spi.0", | ||
568 | .parent = &clk_div_d1_bus.clk, | ||
569 | .enable = s5pc100_d1_4_ctrl, | ||
570 | .ctrlbit = (1 << 6), | ||
571 | }, { | ||
572 | .name = "spi", | ||
573 | .devname = "s5pc100-spi.1", | ||
574 | .parent = &clk_div_d1_bus.clk, | ||
575 | .enable = s5pc100_d1_4_ctrl, | ||
576 | .ctrlbit = (1 << 7), | ||
577 | }, { | ||
578 | .name = "spi", | ||
579 | .devname = "s5pc100-spi.2", | ||
580 | .parent = &clk_div_d1_bus.clk, | ||
581 | .enable = s5pc100_d1_4_ctrl, | ||
582 | .ctrlbit = (1 << 8), | ||
583 | }, { | ||
584 | .name = "irda", | ||
585 | .parent = &clk_div_d1_bus.clk, | ||
586 | .enable = s5pc100_d1_4_ctrl, | ||
587 | .ctrlbit = (1 << 9), | ||
588 | }, { | ||
589 | .name = "ccan", | ||
590 | .parent = &clk_div_d1_bus.clk, | ||
591 | .enable = s5pc100_d1_4_ctrl, | ||
592 | .ctrlbit = (1 << 10), | ||
593 | }, { | ||
594 | .name = "ccan", | ||
595 | .parent = &clk_div_d1_bus.clk, | ||
596 | .enable = s5pc100_d1_4_ctrl, | ||
597 | .ctrlbit = (1 << 11), | ||
598 | }, { | ||
599 | .name = "hsitx", | ||
600 | .parent = &clk_div_d1_bus.clk, | ||
601 | .enable = s5pc100_d1_4_ctrl, | ||
602 | .ctrlbit = (1 << 12), | ||
603 | }, { | ||
604 | .name = "hsirx", | ||
605 | .parent = &clk_div_d1_bus.clk, | ||
606 | .enable = s5pc100_d1_4_ctrl, | ||
607 | .ctrlbit = (1 << 13), | ||
608 | }, { | ||
609 | .name = "ac97", | ||
610 | .parent = &clk_div_pclkd1.clk, | ||
611 | .enable = s5pc100_d1_5_ctrl, | ||
612 | .ctrlbit = (1 << 3), | ||
613 | }, { | ||
614 | .name = "pcm", | ||
615 | .devname = "samsung-pcm.0", | ||
616 | .parent = &clk_div_pclkd1.clk, | ||
617 | .enable = s5pc100_d1_5_ctrl, | ||
618 | .ctrlbit = (1 << 4), | ||
619 | }, { | ||
620 | .name = "pcm", | ||
621 | .devname = "samsung-pcm.1", | ||
622 | .parent = &clk_div_pclkd1.clk, | ||
623 | .enable = s5pc100_d1_5_ctrl, | ||
624 | .ctrlbit = (1 << 5), | ||
625 | }, { | ||
626 | .name = "spdif", | ||
627 | .parent = &clk_div_pclkd1.clk, | ||
628 | .enable = s5pc100_d1_5_ctrl, | ||
629 | .ctrlbit = (1 << 6), | ||
630 | }, { | ||
631 | .name = "adc", | ||
632 | .parent = &clk_div_pclkd1.clk, | ||
633 | .enable = s5pc100_d1_5_ctrl, | ||
634 | .ctrlbit = (1 << 7), | ||
635 | }, { | ||
636 | .name = "keypad", | ||
637 | .parent = &clk_div_pclkd1.clk, | ||
638 | .enable = s5pc100_d1_5_ctrl, | ||
639 | .ctrlbit = (1 << 8), | ||
640 | }, { | ||
641 | .name = "mmc_48m", | ||
642 | .devname = "s3c-sdhci.0", | ||
643 | .parent = &clk_mout_48m.clk, | ||
644 | .enable = s5pc100_sclk0_ctrl, | ||
645 | .ctrlbit = (1 << 15), | ||
646 | }, { | ||
647 | .name = "mmc_48m", | ||
648 | .devname = "s3c-sdhci.1", | ||
649 | .parent = &clk_mout_48m.clk, | ||
650 | .enable = s5pc100_sclk0_ctrl, | ||
651 | .ctrlbit = (1 << 16), | ||
652 | }, { | ||
653 | .name = "mmc_48m", | ||
654 | .devname = "s3c-sdhci.2", | ||
655 | .parent = &clk_mout_48m.clk, | ||
656 | .enable = s5pc100_sclk0_ctrl, | ||
657 | .ctrlbit = (1 << 17), | ||
658 | }, | ||
659 | }; | ||
660 | |||
661 | static struct clk clk_hsmmc2 = { | ||
662 | .name = "hsmmc", | ||
663 | .devname = "s3c-sdhci.2", | ||
664 | .parent = &clk_div_d1_bus.clk, | ||
665 | .enable = s5pc100_d1_0_ctrl, | ||
666 | .ctrlbit = (1 << 7), | ||
667 | }; | ||
668 | |||
669 | static struct clk clk_hsmmc1 = { | ||
670 | .name = "hsmmc", | ||
671 | .devname = "s3c-sdhci.1", | ||
672 | .parent = &clk_div_d1_bus.clk, | ||
673 | .enable = s5pc100_d1_0_ctrl, | ||
674 | .ctrlbit = (1 << 6), | ||
675 | }; | ||
676 | |||
677 | static struct clk clk_hsmmc0 = { | ||
678 | .name = "hsmmc", | ||
679 | .devname = "s3c-sdhci.0", | ||
680 | .parent = &clk_div_d1_bus.clk, | ||
681 | .enable = s5pc100_d1_0_ctrl, | ||
682 | .ctrlbit = (1 << 5), | ||
683 | }; | ||
684 | |||
685 | static struct clk clk_48m_spi0 = { | ||
686 | .name = "spi_48m", | ||
687 | .devname = "s5pc100-spi.0", | ||
688 | .parent = &clk_mout_48m.clk, | ||
689 | .enable = s5pc100_sclk0_ctrl, | ||
690 | .ctrlbit = (1 << 7), | ||
691 | }; | ||
692 | |||
693 | static struct clk clk_48m_spi1 = { | ||
694 | .name = "spi_48m", | ||
695 | .devname = "s5pc100-spi.1", | ||
696 | .parent = &clk_mout_48m.clk, | ||
697 | .enable = s5pc100_sclk0_ctrl, | ||
698 | .ctrlbit = (1 << 8), | ||
699 | }; | ||
700 | |||
701 | static struct clk clk_48m_spi2 = { | ||
702 | .name = "spi_48m", | ||
703 | .devname = "s5pc100-spi.2", | ||
704 | .parent = &clk_mout_48m.clk, | ||
705 | .enable = s5pc100_sclk0_ctrl, | ||
706 | .ctrlbit = (1 << 9), | ||
707 | }; | ||
708 | |||
709 | static struct clk clk_i2s0 = { | ||
710 | .name = "iis", | ||
711 | .devname = "samsung-i2s.0", | ||
712 | .parent = &clk_div_pclkd1.clk, | ||
713 | .enable = s5pc100_d1_5_ctrl, | ||
714 | .ctrlbit = (1 << 0), | ||
715 | }; | ||
716 | |||
717 | static struct clk clk_i2s1 = { | ||
718 | .name = "iis", | ||
719 | .devname = "samsung-i2s.1", | ||
720 | .parent = &clk_div_pclkd1.clk, | ||
721 | .enable = s5pc100_d1_5_ctrl, | ||
722 | .ctrlbit = (1 << 1), | ||
723 | }; | ||
724 | |||
725 | static struct clk clk_i2s2 = { | ||
726 | .name = "iis", | ||
727 | .devname = "samsung-i2s.2", | ||
728 | .parent = &clk_div_pclkd1.clk, | ||
729 | .enable = s5pc100_d1_5_ctrl, | ||
730 | .ctrlbit = (1 << 2), | ||
731 | }; | ||
732 | |||
733 | static struct clk clk_vclk54m = { | ||
734 | .name = "vclk_54m", | ||
735 | .rate = 54000000, | ||
736 | }; | ||
737 | |||
738 | static struct clk clk_i2scdclk0 = { | ||
739 | .name = "i2s_cdclk0", | ||
740 | }; | ||
741 | |||
742 | static struct clk clk_i2scdclk1 = { | ||
743 | .name = "i2s_cdclk1", | ||
744 | }; | ||
745 | |||
746 | static struct clk clk_i2scdclk2 = { | ||
747 | .name = "i2s_cdclk2", | ||
748 | }; | ||
749 | |||
750 | static struct clk clk_pcmcdclk0 = { | ||
751 | .name = "pcm_cdclk0", | ||
752 | }; | ||
753 | |||
754 | static struct clk clk_pcmcdclk1 = { | ||
755 | .name = "pcm_cdclk1", | ||
756 | }; | ||
757 | |||
758 | static struct clk *clk_src_group1_list[] = { | ||
759 | [0] = &clk_mout_epll.clk, | ||
760 | [1] = &clk_div_mpll2.clk, | ||
761 | [2] = &clk_fin_epll, | ||
762 | [3] = &clk_mout_hpll.clk, | ||
763 | }; | ||
764 | |||
765 | static struct clksrc_sources clk_src_group1 = { | ||
766 | .sources = clk_src_group1_list, | ||
767 | .nr_sources = ARRAY_SIZE(clk_src_group1_list), | ||
768 | }; | ||
769 | |||
770 | static struct clk *clk_src_group2_list[] = { | ||
771 | [0] = &clk_mout_epll.clk, | ||
772 | [1] = &clk_div_mpll.clk, | ||
773 | }; | ||
774 | |||
775 | static struct clksrc_sources clk_src_group2 = { | ||
776 | .sources = clk_src_group2_list, | ||
777 | .nr_sources = ARRAY_SIZE(clk_src_group2_list), | ||
778 | }; | ||
779 | |||
780 | static struct clk *clk_src_group3_list[] = { | ||
781 | [0] = &clk_mout_epll.clk, | ||
782 | [1] = &clk_div_mpll.clk, | ||
783 | [2] = &clk_fin_epll, | ||
784 | [3] = &clk_i2scdclk0, | ||
785 | [4] = &clk_pcmcdclk0, | ||
786 | [5] = &clk_mout_hpll.clk, | ||
787 | }; | ||
788 | |||
789 | static struct clksrc_sources clk_src_group3 = { | ||
790 | .sources = clk_src_group3_list, | ||
791 | .nr_sources = ARRAY_SIZE(clk_src_group3_list), | ||
792 | }; | ||
793 | |||
794 | static struct clksrc_clk clk_sclk_audio0 = { | ||
795 | .clk = { | ||
796 | .name = "sclk_audio", | ||
797 | .devname = "samsung-pcm.0", | ||
798 | .ctrlbit = (1 << 8), | ||
799 | .enable = s5pc100_sclk1_ctrl, | ||
800 | }, | ||
801 | .sources = &clk_src_group3, | ||
802 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 }, | ||
803 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 }, | ||
804 | }; | ||
805 | |||
806 | static struct clk *clk_src_group4_list[] = { | ||
807 | [0] = &clk_mout_epll.clk, | ||
808 | [1] = &clk_div_mpll.clk, | ||
809 | [2] = &clk_fin_epll, | ||
810 | [3] = &clk_i2scdclk1, | ||
811 | [4] = &clk_pcmcdclk1, | ||
812 | [5] = &clk_mout_hpll.clk, | ||
813 | }; | ||
814 | |||
815 | static struct clksrc_sources clk_src_group4 = { | ||
816 | .sources = clk_src_group4_list, | ||
817 | .nr_sources = ARRAY_SIZE(clk_src_group4_list), | ||
818 | }; | ||
819 | |||
820 | static struct clksrc_clk clk_sclk_audio1 = { | ||
821 | .clk = { | ||
822 | .name = "sclk_audio", | ||
823 | .devname = "samsung-pcm.1", | ||
824 | .ctrlbit = (1 << 9), | ||
825 | .enable = s5pc100_sclk1_ctrl, | ||
826 | }, | ||
827 | .sources = &clk_src_group4, | ||
828 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 }, | ||
829 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 }, | ||
830 | }; | ||
831 | |||
832 | static struct clk *clk_src_group5_list[] = { | ||
833 | [0] = &clk_mout_epll.clk, | ||
834 | [1] = &clk_div_mpll.clk, | ||
835 | [2] = &clk_fin_epll, | ||
836 | [3] = &clk_i2scdclk2, | ||
837 | [4] = &clk_mout_hpll.clk, | ||
838 | }; | ||
839 | |||
840 | static struct clksrc_sources clk_src_group5 = { | ||
841 | .sources = clk_src_group5_list, | ||
842 | .nr_sources = ARRAY_SIZE(clk_src_group5_list), | ||
843 | }; | ||
844 | |||
845 | static struct clksrc_clk clk_sclk_audio2 = { | ||
846 | .clk = { | ||
847 | .name = "sclk_audio", | ||
848 | .devname = "samsung-pcm.2", | ||
849 | .ctrlbit = (1 << 10), | ||
850 | .enable = s5pc100_sclk1_ctrl, | ||
851 | }, | ||
852 | .sources = &clk_src_group5, | ||
853 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 }, | ||
854 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 }, | ||
855 | }; | ||
856 | |||
857 | static struct clk *clk_src_group6_list[] = { | ||
858 | [0] = &s5p_clk_27m, | ||
859 | [1] = &clk_vclk54m, | ||
860 | [2] = &clk_div_hdmi.clk, | ||
861 | }; | ||
862 | |||
863 | static struct clksrc_sources clk_src_group6 = { | ||
864 | .sources = clk_src_group6_list, | ||
865 | .nr_sources = ARRAY_SIZE(clk_src_group6_list), | ||
866 | }; | ||
867 | |||
868 | static struct clk *clk_src_group7_list[] = { | ||
869 | [0] = &clk_mout_epll.clk, | ||
870 | [1] = &clk_div_mpll.clk, | ||
871 | [2] = &clk_mout_hpll.clk, | ||
872 | [3] = &clk_vclk54m, | ||
873 | }; | ||
874 | |||
875 | static struct clksrc_sources clk_src_group7 = { | ||
876 | .sources = clk_src_group7_list, | ||
877 | .nr_sources = ARRAY_SIZE(clk_src_group7_list), | ||
878 | }; | ||
879 | |||
880 | static struct clk *clk_src_mmc0_list[] = { | ||
881 | [0] = &clk_mout_epll.clk, | ||
882 | [1] = &clk_div_mpll.clk, | ||
883 | [2] = &clk_fin_epll, | ||
884 | }; | ||
885 | |||
886 | static struct clksrc_sources clk_src_mmc0 = { | ||
887 | .sources = clk_src_mmc0_list, | ||
888 | .nr_sources = ARRAY_SIZE(clk_src_mmc0_list), | ||
889 | }; | ||
890 | |||
891 | static struct clk *clk_src_mmc12_list[] = { | ||
892 | [0] = &clk_mout_epll.clk, | ||
893 | [1] = &clk_div_mpll.clk, | ||
894 | [2] = &clk_fin_epll, | ||
895 | [3] = &clk_mout_hpll.clk, | ||
896 | }; | ||
897 | |||
898 | static struct clksrc_sources clk_src_mmc12 = { | ||
899 | .sources = clk_src_mmc12_list, | ||
900 | .nr_sources = ARRAY_SIZE(clk_src_mmc12_list), | ||
901 | }; | ||
902 | |||
903 | static struct clk *clk_src_irda_usb_list[] = { | ||
904 | [0] = &clk_mout_epll.clk, | ||
905 | [1] = &clk_div_mpll.clk, | ||
906 | [2] = &clk_fin_epll, | ||
907 | [3] = &clk_mout_hpll.clk, | ||
908 | }; | ||
909 | |||
910 | static struct clksrc_sources clk_src_irda_usb = { | ||
911 | .sources = clk_src_irda_usb_list, | ||
912 | .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list), | ||
913 | }; | ||
914 | |||
915 | static struct clk *clk_src_pwi_list[] = { | ||
916 | [0] = &clk_fin_epll, | ||
917 | [1] = &clk_mout_epll.clk, | ||
918 | [2] = &clk_div_mpll.clk, | ||
919 | }; | ||
920 | |||
921 | static struct clksrc_sources clk_src_pwi = { | ||
922 | .sources = clk_src_pwi_list, | ||
923 | .nr_sources = ARRAY_SIZE(clk_src_pwi_list), | ||
924 | }; | ||
925 | |||
926 | static struct clk *clk_sclk_spdif_list[] = { | ||
927 | [0] = &clk_sclk_audio0.clk, | ||
928 | [1] = &clk_sclk_audio1.clk, | ||
929 | [2] = &clk_sclk_audio2.clk, | ||
930 | }; | ||
931 | |||
932 | static struct clksrc_sources clk_src_sclk_spdif = { | ||
933 | .sources = clk_sclk_spdif_list, | ||
934 | .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list), | ||
935 | }; | ||
936 | |||
937 | static struct clksrc_clk clk_sclk_spdif = { | ||
938 | .clk = { | ||
939 | .name = "sclk_spdif", | ||
940 | .ctrlbit = (1 << 11), | ||
941 | .enable = s5pc100_sclk1_ctrl, | ||
942 | .ops = &s5p_sclk_spdif_ops, | ||
943 | }, | ||
944 | .sources = &clk_src_sclk_spdif, | ||
945 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 }, | ||
946 | }; | ||
947 | |||
948 | static struct clksrc_clk clksrcs[] = { | ||
949 | { | ||
950 | .clk = { | ||
951 | .name = "sclk_mixer", | ||
952 | .ctrlbit = (1 << 6), | ||
953 | .enable = s5pc100_sclk0_ctrl, | ||
954 | |||
955 | }, | ||
956 | .sources = &clk_src_group6, | ||
957 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 }, | ||
958 | }, { | ||
959 | .clk = { | ||
960 | .name = "sclk_lcd", | ||
961 | .ctrlbit = (1 << 0), | ||
962 | .enable = s5pc100_sclk1_ctrl, | ||
963 | |||
964 | }, | ||
965 | .sources = &clk_src_group7, | ||
966 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 }, | ||
967 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 }, | ||
968 | }, { | ||
969 | .clk = { | ||
970 | .name = "sclk_fimc", | ||
971 | .devname = "s5p-fimc.0", | ||
972 | .ctrlbit = (1 << 1), | ||
973 | .enable = s5pc100_sclk1_ctrl, | ||
974 | |||
975 | }, | ||
976 | .sources = &clk_src_group7, | ||
977 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 }, | ||
978 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 }, | ||
979 | }, { | ||
980 | .clk = { | ||
981 | .name = "sclk_fimc", | ||
982 | .devname = "s5p-fimc.1", | ||
983 | .ctrlbit = (1 << 2), | ||
984 | .enable = s5pc100_sclk1_ctrl, | ||
985 | |||
986 | }, | ||
987 | .sources = &clk_src_group7, | ||
988 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 }, | ||
989 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 }, | ||
990 | }, { | ||
991 | .clk = { | ||
992 | .name = "sclk_fimc", | ||
993 | .devname = "s5p-fimc.2", | ||
994 | .ctrlbit = (1 << 3), | ||
995 | .enable = s5pc100_sclk1_ctrl, | ||
996 | |||
997 | }, | ||
998 | .sources = &clk_src_group7, | ||
999 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 }, | ||
1000 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 }, | ||
1001 | }, { | ||
1002 | .clk = { | ||
1003 | .name = "sclk_irda", | ||
1004 | .ctrlbit = (1 << 10), | ||
1005 | .enable = s5pc100_sclk0_ctrl, | ||
1006 | |||
1007 | }, | ||
1008 | .sources = &clk_src_irda_usb, | ||
1009 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | ||
1010 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | ||
1011 | }, { | ||
1012 | .clk = { | ||
1013 | .name = "sclk_irda", | ||
1014 | .ctrlbit = (1 << 10), | ||
1015 | .enable = s5pc100_sclk0_ctrl, | ||
1016 | |||
1017 | }, | ||
1018 | .sources = &clk_src_mmc12, | ||
1019 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 }, | ||
1020 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 }, | ||
1021 | }, { | ||
1022 | .clk = { | ||
1023 | .name = "sclk_pwi", | ||
1024 | .ctrlbit = (1 << 1), | ||
1025 | .enable = s5pc100_sclk0_ctrl, | ||
1026 | |||
1027 | }, | ||
1028 | .sources = &clk_src_pwi, | ||
1029 | .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 }, | ||
1030 | .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 }, | ||
1031 | }, { | ||
1032 | .clk = { | ||
1033 | .name = "sclk_uhost", | ||
1034 | .ctrlbit = (1 << 11), | ||
1035 | .enable = s5pc100_sclk0_ctrl, | ||
1036 | |||
1037 | }, | ||
1038 | .sources = &clk_src_irda_usb, | ||
1039 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 }, | ||
1040 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 }, | ||
1041 | }, | ||
1042 | }; | ||
1043 | |||
1044 | static struct clksrc_clk clk_sclk_uart = { | ||
1045 | .clk = { | ||
1046 | .name = "uclk1", | ||
1047 | .ctrlbit = (1 << 3), | ||
1048 | .enable = s5pc100_sclk0_ctrl, | ||
1049 | }, | ||
1050 | .sources = &clk_src_group2, | ||
1051 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, | ||
1052 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 }, | ||
1053 | }; | ||
1054 | |||
1055 | static struct clksrc_clk clk_sclk_mmc0 = { | ||
1056 | .clk = { | ||
1057 | .name = "sclk_mmc", | ||
1058 | .devname = "s3c-sdhci.0", | ||
1059 | .ctrlbit = (1 << 12), | ||
1060 | .enable = s5pc100_sclk1_ctrl, | ||
1061 | }, | ||
1062 | .sources = &clk_src_mmc0, | ||
1063 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 }, | ||
1064 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 }, | ||
1065 | }; | ||
1066 | |||
1067 | static struct clksrc_clk clk_sclk_mmc1 = { | ||
1068 | .clk = { | ||
1069 | .name = "sclk_mmc", | ||
1070 | .devname = "s3c-sdhci.1", | ||
1071 | .ctrlbit = (1 << 13), | ||
1072 | .enable = s5pc100_sclk1_ctrl, | ||
1073 | }, | ||
1074 | .sources = &clk_src_mmc12, | ||
1075 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 }, | ||
1076 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 }, | ||
1077 | }; | ||
1078 | |||
1079 | static struct clksrc_clk clk_sclk_mmc2 = { | ||
1080 | .clk = { | ||
1081 | .name = "sclk_mmc", | ||
1082 | .devname = "s3c-sdhci.2", | ||
1083 | .ctrlbit = (1 << 14), | ||
1084 | .enable = s5pc100_sclk1_ctrl, | ||
1085 | }, | ||
1086 | .sources = &clk_src_mmc12, | ||
1087 | .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 }, | ||
1088 | .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 }, | ||
1089 | }; | ||
1090 | |||
1091 | static struct clksrc_clk clk_sclk_spi0 = { | ||
1092 | .clk = { | ||
1093 | .name = "sclk_spi", | ||
1094 | .devname = "s5pc100-spi.0", | ||
1095 | .ctrlbit = (1 << 4), | ||
1096 | .enable = s5pc100_sclk0_ctrl, | ||
1097 | }, | ||
1098 | .sources = &clk_src_group1, | ||
1099 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 }, | ||
1100 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 }, | ||
1101 | }; | ||
1102 | |||
1103 | static struct clksrc_clk clk_sclk_spi1 = { | ||
1104 | .clk = { | ||
1105 | .name = "sclk_spi", | ||
1106 | .devname = "s5pc100-spi.1", | ||
1107 | .ctrlbit = (1 << 5), | ||
1108 | .enable = s5pc100_sclk0_ctrl, | ||
1109 | }, | ||
1110 | .sources = &clk_src_group1, | ||
1111 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 }, | ||
1112 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 }, | ||
1113 | }; | ||
1114 | |||
1115 | static struct clksrc_clk clk_sclk_spi2 = { | ||
1116 | .clk = { | ||
1117 | .name = "sclk_spi", | ||
1118 | .devname = "s5pc100-spi.2", | ||
1119 | .ctrlbit = (1 << 6), | ||
1120 | .enable = s5pc100_sclk0_ctrl, | ||
1121 | }, | ||
1122 | .sources = &clk_src_group1, | ||
1123 | .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 }, | ||
1124 | .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 }, | ||
1125 | }; | ||
1126 | |||
1127 | /* Clock initialisation code */ | ||
1128 | static struct clksrc_clk *sysclks[] = { | ||
1129 | &clk_mout_apll, | ||
1130 | &clk_mout_epll, | ||
1131 | &clk_mout_mpll, | ||
1132 | &clk_mout_hpll, | ||
1133 | &clk_mout_href, | ||
1134 | &clk_mout_48m, | ||
1135 | &clk_div_apll, | ||
1136 | &clk_div_arm, | ||
1137 | &clk_div_d0_bus, | ||
1138 | &clk_div_pclkd0, | ||
1139 | &clk_div_secss, | ||
1140 | &clk_div_apll2, | ||
1141 | &clk_mout_am, | ||
1142 | &clk_div_d1_bus, | ||
1143 | &clk_div_mpll2, | ||
1144 | &clk_div_mpll, | ||
1145 | &clk_mout_onenand, | ||
1146 | &clk_div_onenand, | ||
1147 | &clk_div_pclkd1, | ||
1148 | &clk_div_cam, | ||
1149 | &clk_div_hdmi, | ||
1150 | &clk_sclk_audio0, | ||
1151 | &clk_sclk_audio1, | ||
1152 | &clk_sclk_audio2, | ||
1153 | &clk_sclk_spdif, | ||
1154 | }; | ||
1155 | |||
1156 | static struct clk *clk_cdev[] = { | ||
1157 | &clk_hsmmc0, | ||
1158 | &clk_hsmmc1, | ||
1159 | &clk_hsmmc2, | ||
1160 | &clk_48m_spi0, | ||
1161 | &clk_48m_spi1, | ||
1162 | &clk_48m_spi2, | ||
1163 | &clk_i2s0, | ||
1164 | &clk_i2s1, | ||
1165 | &clk_i2s2, | ||
1166 | }; | ||
1167 | |||
1168 | static struct clksrc_clk *clksrc_cdev[] = { | ||
1169 | &clk_sclk_uart, | ||
1170 | &clk_sclk_mmc0, | ||
1171 | &clk_sclk_mmc1, | ||
1172 | &clk_sclk_mmc2, | ||
1173 | &clk_sclk_spi0, | ||
1174 | &clk_sclk_spi1, | ||
1175 | &clk_sclk_spi2, | ||
1176 | }; | ||
1177 | |||
1178 | void __init_or_cpufreq s5pc100_setup_clocks(void) | ||
1179 | { | ||
1180 | unsigned long xtal; | ||
1181 | unsigned long arm; | ||
1182 | unsigned long hclkd0; | ||
1183 | unsigned long hclkd1; | ||
1184 | unsigned long pclkd0; | ||
1185 | unsigned long pclkd1; | ||
1186 | unsigned long apll; | ||
1187 | unsigned long mpll; | ||
1188 | unsigned long epll; | ||
1189 | unsigned long hpll; | ||
1190 | unsigned int ptr; | ||
1191 | |||
1192 | /* Set S5PC100 functions for clk_fout_epll */ | ||
1193 | clk_fout_epll.enable = s5p_epll_enable; | ||
1194 | clk_fout_epll.ops = &s5pc100_epll_ops; | ||
1195 | |||
1196 | printk(KERN_DEBUG "%s: registering clocks\n", __func__); | ||
1197 | |||
1198 | xtal = clk_get_rate(&clk_xtal); | ||
1199 | |||
1200 | printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal); | ||
1201 | |||
1202 | apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON)); | ||
1203 | mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON)); | ||
1204 | epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON)); | ||
1205 | hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON)); | ||
1206 | |||
1207 | printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n", | ||
1208 | print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll)); | ||
1209 | |||
1210 | clk_fout_apll.rate = apll; | ||
1211 | clk_fout_mpll.rate = mpll; | ||
1212 | clk_fout_epll.rate = epll; | ||
1213 | clk_mout_hpll.clk.rate = hpll; | ||
1214 | |||
1215 | for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++) | ||
1216 | s3c_set_clksrc(&clksrcs[ptr], true); | ||
1217 | |||
1218 | arm = clk_get_rate(&clk_div_arm.clk); | ||
1219 | hclkd0 = clk_get_rate(&clk_div_d0_bus.clk); | ||
1220 | pclkd0 = clk_get_rate(&clk_div_pclkd0.clk); | ||
1221 | hclkd1 = clk_get_rate(&clk_div_d1_bus.clk); | ||
1222 | pclkd1 = clk_get_rate(&clk_div_pclkd1.clk); | ||
1223 | |||
1224 | printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n", | ||
1225 | print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1)); | ||
1226 | |||
1227 | clk_f.rate = arm; | ||
1228 | clk_h.rate = hclkd1; | ||
1229 | clk_p.rate = pclkd1; | ||
1230 | } | ||
1231 | |||
1232 | /* | ||
1233 | * The following clocks will be enabled during clock initialization. | ||
1234 | */ | ||
1235 | static struct clk init_clocks[] = { | ||
1236 | { | ||
1237 | .name = "tzic", | ||
1238 | .parent = &clk_div_d0_bus.clk, | ||
1239 | .enable = s5pc100_d0_0_ctrl, | ||
1240 | .ctrlbit = (1 << 1), | ||
1241 | }, { | ||
1242 | .name = "intc", | ||
1243 | .parent = &clk_div_d0_bus.clk, | ||
1244 | .enable = s5pc100_d0_0_ctrl, | ||
1245 | .ctrlbit = (1 << 0), | ||
1246 | }, { | ||
1247 | .name = "ebi", | ||
1248 | .parent = &clk_div_d0_bus.clk, | ||
1249 | .enable = s5pc100_d0_1_ctrl, | ||
1250 | .ctrlbit = (1 << 5), | ||
1251 | }, { | ||
1252 | .name = "intmem", | ||
1253 | .parent = &clk_div_d0_bus.clk, | ||
1254 | .enable = s5pc100_d0_1_ctrl, | ||
1255 | .ctrlbit = (1 << 4), | ||
1256 | }, { | ||
1257 | .name = "sromc", | ||
1258 | .parent = &clk_div_d0_bus.clk, | ||
1259 | .enable = s5pc100_d0_1_ctrl, | ||
1260 | .ctrlbit = (1 << 1), | ||
1261 | }, { | ||
1262 | .name = "dmc", | ||
1263 | .parent = &clk_div_d0_bus.clk, | ||
1264 | .enable = s5pc100_d0_1_ctrl, | ||
1265 | .ctrlbit = (1 << 0), | ||
1266 | }, { | ||
1267 | .name = "chipid", | ||
1268 | .parent = &clk_div_d0_bus.clk, | ||
1269 | .enable = s5pc100_d0_1_ctrl, | ||
1270 | .ctrlbit = (1 << 0), | ||
1271 | }, { | ||
1272 | .name = "gpio", | ||
1273 | .parent = &clk_div_d1_bus.clk, | ||
1274 | .enable = s5pc100_d1_3_ctrl, | ||
1275 | .ctrlbit = (1 << 1), | ||
1276 | }, { | ||
1277 | .name = "uart", | ||
1278 | .devname = "s3c6400-uart.0", | ||
1279 | .parent = &clk_div_d1_bus.clk, | ||
1280 | .enable = s5pc100_d1_4_ctrl, | ||
1281 | .ctrlbit = (1 << 0), | ||
1282 | }, { | ||
1283 | .name = "uart", | ||
1284 | .devname = "s3c6400-uart.1", | ||
1285 | .parent = &clk_div_d1_bus.clk, | ||
1286 | .enable = s5pc100_d1_4_ctrl, | ||
1287 | .ctrlbit = (1 << 1), | ||
1288 | }, { | ||
1289 | .name = "uart", | ||
1290 | .devname = "s3c6400-uart.2", | ||
1291 | .parent = &clk_div_d1_bus.clk, | ||
1292 | .enable = s5pc100_d1_4_ctrl, | ||
1293 | .ctrlbit = (1 << 2), | ||
1294 | }, { | ||
1295 | .name = "uart", | ||
1296 | .devname = "s3c6400-uart.3", | ||
1297 | .parent = &clk_div_d1_bus.clk, | ||
1298 | .enable = s5pc100_d1_4_ctrl, | ||
1299 | .ctrlbit = (1 << 3), | ||
1300 | }, { | ||
1301 | .name = "timers", | ||
1302 | .parent = &clk_div_d1_bus.clk, | ||
1303 | .enable = s5pc100_d1_3_ctrl, | ||
1304 | .ctrlbit = (1 << 6), | ||
1305 | }, | ||
1306 | }; | ||
1307 | |||
1308 | static struct clk *clks[] __initdata = { | ||
1309 | &clk_ext, | ||
1310 | &clk_i2scdclk0, | ||
1311 | &clk_i2scdclk1, | ||
1312 | &clk_i2scdclk2, | ||
1313 | &clk_pcmcdclk0, | ||
1314 | &clk_pcmcdclk1, | ||
1315 | }; | ||
1316 | |||
1317 | static struct clk_lookup s5pc100_clk_lookup[] = { | ||
1318 | CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p), | ||
1319 | CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk), | ||
1320 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0), | ||
1321 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1), | ||
1322 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2), | ||
1323 | CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk), | ||
1324 | CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk), | ||
1325 | CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk), | ||
1326 | CLKDEV_INIT(NULL, "spi_busclk0", &clk_p), | ||
1327 | CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0), | ||
1328 | CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk), | ||
1329 | CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1), | ||
1330 | CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk), | ||
1331 | CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2), | ||
1332 | CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk), | ||
1333 | CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0), | ||
1334 | CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1), | ||
1335 | CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2), | ||
1336 | }; | ||
1337 | |||
1338 | void __init s5pc100_register_clocks(void) | ||
1339 | { | ||
1340 | int ptr; | ||
1341 | |||
1342 | s3c24xx_register_clocks(clks, ARRAY_SIZE(clks)); | ||
1343 | |||
1344 | for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++) | ||
1345 | s3c_register_clksrc(sysclks[ptr], 1); | ||
1346 | |||
1347 | s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs)); | ||
1348 | s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks)); | ||
1349 | for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++) | ||
1350 | s3c_register_clksrc(clksrc_cdev[ptr], 1); | ||
1351 | |||
1352 | s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
1353 | s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off)); | ||
1354 | clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup)); | ||
1355 | |||
1356 | s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev)); | ||
1357 | for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++) | ||
1358 | s3c_disable_clocks(clk_cdev[ptr], 1); | ||
1359 | |||
1360 | s3c24xx_register_clock(&dummy_apb_pclk); | ||
1361 | } | ||
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c deleted file mode 100644 index 6a41bf7dacf6..000000000000 --- a/arch/arm/mach-s5pc100/common.c +++ /dev/null | |||
@@ -1,255 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * Copyright 2009 Samsung Electronics Co. | ||
6 | * Byungho Min <bhmin@samsung.com> | ||
7 | * | ||
8 | * Common Codes for S5PC100 | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | #include <linux/interrupt.h> | ||
18 | #include <linux/list.h> | ||
19 | #include <linux/timer.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/device.h> | ||
24 | #include <linux/serial_core.h> | ||
25 | #include <linux/serial_s3c.h> | ||
26 | #include <clocksource/samsung_pwm.h> | ||
27 | #include <linux/platform_device.h> | ||
28 | #include <linux/sched.h> | ||
29 | #include <linux/reboot.h> | ||
30 | |||
31 | #include <asm/irq.h> | ||
32 | #include <asm/proc-fns.h> | ||
33 | #include <asm/system_misc.h> | ||
34 | #include <asm/mach/arch.h> | ||
35 | #include <asm/mach/map.h> | ||
36 | #include <asm/mach/irq.h> | ||
37 | |||
38 | #include <mach/map.h> | ||
39 | #include <mach/hardware.h> | ||
40 | #include <mach/regs-clock.h> | ||
41 | |||
42 | #include <plat/cpu.h> | ||
43 | #include <plat/devs.h> | ||
44 | #include <plat/clock.h> | ||
45 | #include <plat/sdhci.h> | ||
46 | #include <plat/adc-core.h> | ||
47 | #include <plat/ata-core.h> | ||
48 | #include <plat/fb-core.h> | ||
49 | #include <plat/iic-core.h> | ||
50 | #include <plat/onenand-core.h> | ||
51 | #include <plat/pwm-core.h> | ||
52 | #include <plat/spi-core.h> | ||
53 | #include <plat/watchdog-reset.h> | ||
54 | |||
55 | #include "common.h" | ||
56 | |||
57 | static const char name_s5pc100[] = "S5PC100"; | ||
58 | |||
59 | static struct cpu_table cpu_ids[] __initdata = { | ||
60 | { | ||
61 | .idcode = S5PC100_CPU_ID, | ||
62 | .idmask = S5PC100_CPU_MASK, | ||
63 | .map_io = s5pc100_map_io, | ||
64 | .init_clocks = s5pc100_init_clocks, | ||
65 | .init_uarts = s5pc100_init_uarts, | ||
66 | .init = s5pc100_init, | ||
67 | .name = name_s5pc100, | ||
68 | }, | ||
69 | }; | ||
70 | |||
71 | /* Initial IO mappings */ | ||
72 | |||
73 | static struct map_desc s5pc100_iodesc[] __initdata = { | ||
74 | { | ||
75 | .virtual = (unsigned long)S5P_VA_CHIPID, | ||
76 | .pfn = __phys_to_pfn(S5PC100_PA_CHIPID), | ||
77 | .length = SZ_4K, | ||
78 | .type = MT_DEVICE, | ||
79 | }, { | ||
80 | .virtual = (unsigned long)S3C_VA_SYS, | ||
81 | .pfn = __phys_to_pfn(S5PC100_PA_SYSCON), | ||
82 | .length = SZ_64K, | ||
83 | .type = MT_DEVICE, | ||
84 | }, { | ||
85 | .virtual = (unsigned long)S3C_VA_TIMER, | ||
86 | .pfn = __phys_to_pfn(S5PC100_PA_TIMER), | ||
87 | .length = SZ_16K, | ||
88 | .type = MT_DEVICE, | ||
89 | }, { | ||
90 | .virtual = (unsigned long)S3C_VA_WATCHDOG, | ||
91 | .pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG), | ||
92 | .length = SZ_4K, | ||
93 | .type = MT_DEVICE, | ||
94 | }, { | ||
95 | .virtual = (unsigned long)S5P_VA_SROMC, | ||
96 | .pfn = __phys_to_pfn(S5PC100_PA_SROMC), | ||
97 | .length = SZ_4K, | ||
98 | .type = MT_DEVICE, | ||
99 | }, { | ||
100 | .virtual = (unsigned long)S5P_VA_SYSTIMER, | ||
101 | .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER), | ||
102 | .length = SZ_16K, | ||
103 | .type = MT_DEVICE, | ||
104 | }, { | ||
105 | .virtual = (unsigned long)S5P_VA_GPIO, | ||
106 | .pfn = __phys_to_pfn(S5PC100_PA_GPIO), | ||
107 | .length = SZ_4K, | ||
108 | .type = MT_DEVICE, | ||
109 | }, { | ||
110 | .virtual = (unsigned long)VA_VIC0, | ||
111 | .pfn = __phys_to_pfn(S5PC100_PA_VIC0), | ||
112 | .length = SZ_16K, | ||
113 | .type = MT_DEVICE, | ||
114 | }, { | ||
115 | .virtual = (unsigned long)VA_VIC1, | ||
116 | .pfn = __phys_to_pfn(S5PC100_PA_VIC1), | ||
117 | .length = SZ_16K, | ||
118 | .type = MT_DEVICE, | ||
119 | }, { | ||
120 | .virtual = (unsigned long)VA_VIC2, | ||
121 | .pfn = __phys_to_pfn(S5PC100_PA_VIC2), | ||
122 | .length = SZ_16K, | ||
123 | .type = MT_DEVICE, | ||
124 | }, { | ||
125 | .virtual = (unsigned long)S3C_VA_UART, | ||
126 | .pfn = __phys_to_pfn(S3C_PA_UART), | ||
127 | .length = SZ_512K, | ||
128 | .type = MT_DEVICE, | ||
129 | }, { | ||
130 | .virtual = (unsigned long)S5PC100_VA_OTHERS, | ||
131 | .pfn = __phys_to_pfn(S5PC100_PA_OTHERS), | ||
132 | .length = SZ_4K, | ||
133 | .type = MT_DEVICE, | ||
134 | } | ||
135 | }; | ||
136 | |||
137 | static struct samsung_pwm_variant s5pc100_pwm_variant = { | ||
138 | .bits = 32, | ||
139 | .div_base = 0, | ||
140 | .has_tint_cstat = true, | ||
141 | .tclk_mask = (1 << 5), | ||
142 | }; | ||
143 | |||
144 | void __init samsung_set_timer_source(unsigned int event, unsigned int source) | ||
145 | { | ||
146 | s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; | ||
147 | s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); | ||
148 | } | ||
149 | |||
150 | void __init samsung_timer_init(void) | ||
151 | { | ||
152 | unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { | ||
153 | IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, | ||
154 | IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, | ||
155 | }; | ||
156 | |||
157 | samsung_pwm_clocksource_init(S3C_VA_TIMER, | ||
158 | timer_irqs, &s5pc100_pwm_variant); | ||
159 | } | ||
160 | |||
161 | /* | ||
162 | * s5pc100_map_io | ||
163 | * | ||
164 | * register the standard CPU IO areas | ||
165 | */ | ||
166 | |||
167 | void __init s5pc100_init_io(struct map_desc *mach_desc, int size) | ||
168 | { | ||
169 | /* initialize the io descriptors we need for initialization */ | ||
170 | iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); | ||
171 | if (mach_desc) | ||
172 | iotable_init(mach_desc, size); | ||
173 | |||
174 | /* detect cpu id and rev. */ | ||
175 | s5p_init_cpu(S5P_VA_CHIPID); | ||
176 | |||
177 | s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); | ||
178 | |||
179 | samsung_pwm_set_platdata(&s5pc100_pwm_variant); | ||
180 | } | ||
181 | |||
182 | void __init s5pc100_map_io(void) | ||
183 | { | ||
184 | /* initialise device information early */ | ||
185 | s5pc100_default_sdhci0(); | ||
186 | s5pc100_default_sdhci1(); | ||
187 | s5pc100_default_sdhci2(); | ||
188 | |||
189 | s3c_adc_setname("s3c64xx-adc"); | ||
190 | |||
191 | /* the i2c devices are directly compatible with s3c2440 */ | ||
192 | s3c_i2c0_setname("s3c2440-i2c"); | ||
193 | s3c_i2c1_setname("s3c2440-i2c"); | ||
194 | |||
195 | s3c_onenand_setname("s5pc100-onenand"); | ||
196 | s3c_fb_setname("s5pc100-fb"); | ||
197 | s3c_cfcon_setname("s5pc100-pata"); | ||
198 | |||
199 | s3c64xx_spi_setname("s5pc100-spi"); | ||
200 | } | ||
201 | |||
202 | void __init s5pc100_init_clocks(int xtal) | ||
203 | { | ||
204 | printk(KERN_DEBUG "%s: initializing clocks\n", __func__); | ||
205 | |||
206 | s3c24xx_register_baseclocks(xtal); | ||
207 | s5p_register_clocks(xtal); | ||
208 | s5pc100_register_clocks(); | ||
209 | s5pc100_setup_clocks(); | ||
210 | samsung_wdt_reset_init(S3C_VA_WATCHDOG); | ||
211 | } | ||
212 | |||
213 | void __init s5pc100_init_irq(void) | ||
214 | { | ||
215 | u32 vic[] = {~0, ~0, ~0}; | ||
216 | |||
217 | /* VIC0, VIC1, and VIC2 are fully populated. */ | ||
218 | s5p_init_irq(vic, ARRAY_SIZE(vic)); | ||
219 | } | ||
220 | |||
221 | static struct bus_type s5pc100_subsys = { | ||
222 | .name = "s5pc100-core", | ||
223 | .dev_name = "s5pc100-core", | ||
224 | }; | ||
225 | |||
226 | static struct device s5pc100_dev = { | ||
227 | .bus = &s5pc100_subsys, | ||
228 | }; | ||
229 | |||
230 | static int __init s5pc100_core_init(void) | ||
231 | { | ||
232 | return subsys_system_register(&s5pc100_subsys, NULL); | ||
233 | } | ||
234 | core_initcall(s5pc100_core_init); | ||
235 | |||
236 | int __init s5pc100_init(void) | ||
237 | { | ||
238 | printk(KERN_INFO "S5PC100: Initializing architecture\n"); | ||
239 | return device_register(&s5pc100_dev); | ||
240 | } | ||
241 | |||
242 | /* uart registration process */ | ||
243 | |||
244 | void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no) | ||
245 | { | ||
246 | s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); | ||
247 | } | ||
248 | |||
249 | void s5pc100_restart(enum reboot_mode mode, const char *cmd) | ||
250 | { | ||
251 | if (mode != REBOOT_SOFT) | ||
252 | samsung_wdt_reset(); | ||
253 | |||
254 | soft_restart(0); | ||
255 | } | ||
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h deleted file mode 100644 index 08d782d65d7b..000000000000 --- a/arch/arm/mach-s5pc100/common.h +++ /dev/null | |||
@@ -1,30 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
3 | * http://www.samsung.com | ||
4 | * | ||
5 | * Common Header for S5PC100 machines | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H | ||
13 | #define __ARCH_ARM_MACH_S5PC100_COMMON_H | ||
14 | |||
15 | #include <linux/reboot.h> | ||
16 | |||
17 | void s5pc100_init_io(struct map_desc *mach_desc, int size); | ||
18 | void s5pc100_init_irq(void); | ||
19 | |||
20 | void s5pc100_register_clocks(void); | ||
21 | void s5pc100_setup_clocks(void); | ||
22 | |||
23 | void s5pc100_restart(enum reboot_mode mode, const char *cmd); | ||
24 | |||
25 | extern int s5pc100_init(void); | ||
26 | extern void s5pc100_map_io(void); | ||
27 | extern void s5pc100_init_clocks(int xtal); | ||
28 | extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no); | ||
29 | |||
30 | #endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */ | ||
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c deleted file mode 100644 index 46f488b09391..000000000000 --- a/arch/arm/mach-s5pc100/dev-audio.c +++ /dev/null | |||
@@ -1,239 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/dev-audio.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co. Ltd | ||
4 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/platform_device.h> | ||
12 | #include <linux/dma-mapping.h> | ||
13 | #include <linux/gpio.h> | ||
14 | |||
15 | #include <plat/gpio-cfg.h> | ||
16 | #include <linux/platform_data/asoc-s3c.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <mach/dma.h> | ||
20 | #include <mach/irqs.h> | ||
21 | |||
22 | static int s5pc100_cfg_i2s(struct platform_device *pdev) | ||
23 | { | ||
24 | /* configure GPIO for i2s port */ | ||
25 | switch (pdev->id) { | ||
26 | case 0: /* Dedicated pins */ | ||
27 | break; | ||
28 | case 1: | ||
29 | s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2)); | ||
30 | break; | ||
31 | case 2: | ||
32 | s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4)); | ||
33 | break; | ||
34 | default: | ||
35 | printk(KERN_ERR "Invalid Device %d\n", pdev->id); | ||
36 | return -EINVAL; | ||
37 | } | ||
38 | |||
39 | return 0; | ||
40 | } | ||
41 | |||
42 | static struct s3c_audio_pdata i2sv5_pdata = { | ||
43 | .cfg_gpio = s5pc100_cfg_i2s, | ||
44 | .type = { | ||
45 | .i2s = { | ||
46 | .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI | ||
47 | | QUIRK_NEED_RSTCLR, | ||
48 | }, | ||
49 | }, | ||
50 | }; | ||
51 | |||
52 | static struct resource s5pc100_iis0_resource[] = { | ||
53 | [0] = DEFINE_RES_MEM(S5PC100_PA_I2S0, SZ_256), | ||
54 | [1] = DEFINE_RES_DMA(DMACH_I2S0_TX), | ||
55 | [2] = DEFINE_RES_DMA(DMACH_I2S0_RX), | ||
56 | [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), | ||
57 | }; | ||
58 | |||
59 | struct platform_device s5pc100_device_iis0 = { | ||
60 | .name = "samsung-i2s", | ||
61 | .id = 0, | ||
62 | .num_resources = ARRAY_SIZE(s5pc100_iis0_resource), | ||
63 | .resource = s5pc100_iis0_resource, | ||
64 | .dev = { | ||
65 | .platform_data = &i2sv5_pdata, | ||
66 | }, | ||
67 | }; | ||
68 | |||
69 | static struct s3c_audio_pdata i2sv3_pdata = { | ||
70 | .cfg_gpio = s5pc100_cfg_i2s, | ||
71 | }; | ||
72 | |||
73 | static struct resource s5pc100_iis1_resource[] = { | ||
74 | [0] = DEFINE_RES_MEM(S5PC100_PA_I2S1, SZ_256), | ||
75 | [1] = DEFINE_RES_DMA(DMACH_I2S1_TX), | ||
76 | [2] = DEFINE_RES_DMA(DMACH_I2S1_RX), | ||
77 | }; | ||
78 | |||
79 | struct platform_device s5pc100_device_iis1 = { | ||
80 | .name = "samsung-i2s", | ||
81 | .id = 1, | ||
82 | .num_resources = ARRAY_SIZE(s5pc100_iis1_resource), | ||
83 | .resource = s5pc100_iis1_resource, | ||
84 | .dev = { | ||
85 | .platform_data = &i2sv3_pdata, | ||
86 | }, | ||
87 | }; | ||
88 | |||
89 | static struct resource s5pc100_iis2_resource[] = { | ||
90 | [0] = DEFINE_RES_MEM(S5PC100_PA_I2S2, SZ_256), | ||
91 | [1] = DEFINE_RES_DMA(DMACH_I2S2_TX), | ||
92 | [2] = DEFINE_RES_DMA(DMACH_I2S2_RX), | ||
93 | }; | ||
94 | |||
95 | struct platform_device s5pc100_device_iis2 = { | ||
96 | .name = "samsung-i2s", | ||
97 | .id = 2, | ||
98 | .num_resources = ARRAY_SIZE(s5pc100_iis2_resource), | ||
99 | .resource = s5pc100_iis2_resource, | ||
100 | .dev = { | ||
101 | .platform_data = &i2sv3_pdata, | ||
102 | }, | ||
103 | }; | ||
104 | |||
105 | /* PCM Controller platform_devices */ | ||
106 | |||
107 | static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev) | ||
108 | { | ||
109 | switch (pdev->id) { | ||
110 | case 0: | ||
111 | s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5)); | ||
112 | break; | ||
113 | |||
114 | case 1: | ||
115 | s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3)); | ||
116 | break; | ||
117 | |||
118 | default: | ||
119 | printk(KERN_DEBUG "Invalid PCM Controller number!"); | ||
120 | return -EINVAL; | ||
121 | } | ||
122 | |||
123 | return 0; | ||
124 | } | ||
125 | |||
126 | static struct s3c_audio_pdata s3c_pcm_pdata = { | ||
127 | .cfg_gpio = s5pc100_pcm_cfg_gpio, | ||
128 | }; | ||
129 | |||
130 | static struct resource s5pc100_pcm0_resource[] = { | ||
131 | [0] = DEFINE_RES_MEM(S5PC100_PA_PCM0, SZ_256), | ||
132 | [1] = DEFINE_RES_DMA(DMACH_PCM0_TX), | ||
133 | [2] = DEFINE_RES_DMA(DMACH_PCM0_RX), | ||
134 | }; | ||
135 | |||
136 | struct platform_device s5pc100_device_pcm0 = { | ||
137 | .name = "samsung-pcm", | ||
138 | .id = 0, | ||
139 | .num_resources = ARRAY_SIZE(s5pc100_pcm0_resource), | ||
140 | .resource = s5pc100_pcm0_resource, | ||
141 | .dev = { | ||
142 | .platform_data = &s3c_pcm_pdata, | ||
143 | }, | ||
144 | }; | ||
145 | |||
146 | static struct resource s5pc100_pcm1_resource[] = { | ||
147 | [0] = DEFINE_RES_MEM(S5PC100_PA_PCM1, SZ_256), | ||
148 | [1] = DEFINE_RES_DMA(DMACH_PCM1_TX), | ||
149 | [2] = DEFINE_RES_DMA(DMACH_PCM1_RX), | ||
150 | }; | ||
151 | |||
152 | struct platform_device s5pc100_device_pcm1 = { | ||
153 | .name = "samsung-pcm", | ||
154 | .id = 1, | ||
155 | .num_resources = ARRAY_SIZE(s5pc100_pcm1_resource), | ||
156 | .resource = s5pc100_pcm1_resource, | ||
157 | .dev = { | ||
158 | .platform_data = &s3c_pcm_pdata, | ||
159 | }, | ||
160 | }; | ||
161 | |||
162 | /* AC97 Controller platform devices */ | ||
163 | |||
164 | static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev) | ||
165 | { | ||
166 | return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4)); | ||
167 | } | ||
168 | |||
169 | static struct resource s5pc100_ac97_resource[] = { | ||
170 | [0] = DEFINE_RES_MEM(S5PC100_PA_AC97, SZ_256), | ||
171 | [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), | ||
172 | [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), | ||
173 | [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), | ||
174 | [4] = DEFINE_RES_IRQ(IRQ_AC97), | ||
175 | }; | ||
176 | |||
177 | static struct s3c_audio_pdata s3c_ac97_pdata = { | ||
178 | .cfg_gpio = s5pc100_ac97_cfg_gpio, | ||
179 | }; | ||
180 | |||
181 | static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32); | ||
182 | |||
183 | struct platform_device s5pc100_device_ac97 = { | ||
184 | .name = "samsung-ac97", | ||
185 | .id = -1, | ||
186 | .num_resources = ARRAY_SIZE(s5pc100_ac97_resource), | ||
187 | .resource = s5pc100_ac97_resource, | ||
188 | .dev = { | ||
189 | .platform_data = &s3c_ac97_pdata, | ||
190 | .dma_mask = &s5pc100_ac97_dmamask, | ||
191 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
192 | }, | ||
193 | }; | ||
194 | |||
195 | /* S/PDIF Controller platform_device */ | ||
196 | static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev) | ||
197 | { | ||
198 | s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3)); | ||
199 | |||
200 | return 0; | ||
201 | } | ||
202 | |||
203 | static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev) | ||
204 | { | ||
205 | s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3)); | ||
206 | |||
207 | return 0; | ||
208 | } | ||
209 | |||
210 | static struct resource s5pc100_spdif_resource[] = { | ||
211 | [0] = DEFINE_RES_MEM(S5PC100_PA_SPDIF, SZ_256), | ||
212 | [1] = DEFINE_RES_DMA(DMACH_SPDIF), | ||
213 | }; | ||
214 | |||
215 | static struct s3c_audio_pdata s5p_spdif_pdata = { | ||
216 | .cfg_gpio = s5pc100_spdif_cfg_gpd, | ||
217 | }; | ||
218 | |||
219 | static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32); | ||
220 | |||
221 | struct platform_device s5pc100_device_spdif = { | ||
222 | .name = "samsung-spdif", | ||
223 | .id = -1, | ||
224 | .num_resources = ARRAY_SIZE(s5pc100_spdif_resource), | ||
225 | .resource = s5pc100_spdif_resource, | ||
226 | .dev = { | ||
227 | .platform_data = &s5p_spdif_pdata, | ||
228 | .dma_mask = &s5pc100_spdif_dmamask, | ||
229 | .coherent_dma_mask = DMA_BIT_MASK(32), | ||
230 | }, | ||
231 | }; | ||
232 | |||
233 | void __init s5pc100_spdif_setup_gpio(int gpio) | ||
234 | { | ||
235 | if (gpio == S5PC100_SPDIF_GPD) | ||
236 | s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd; | ||
237 | else | ||
238 | s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3; | ||
239 | } | ||
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c deleted file mode 100644 index b1418409709e..000000000000 --- a/arch/arm/mach-s5pc100/dma.c +++ /dev/null | |||
@@ -1,130 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/dma.c | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
7 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License as published by | ||
11 | * the Free Software Foundation; either version 2 of the License, or | ||
12 | * (at your option) any later version. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | * You should have received a copy of the GNU General Public License | ||
20 | * along with this program; if not, write to the Free Software | ||
21 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
22 | */ | ||
23 | |||
24 | #include <linux/dma-mapping.h> | ||
25 | #include <linux/amba/bus.h> | ||
26 | #include <linux/amba/pl330.h> | ||
27 | |||
28 | #include <asm/irq.h> | ||
29 | #include <plat/devs.h> | ||
30 | #include <plat/irqs.h> | ||
31 | |||
32 | #include <mach/map.h> | ||
33 | #include <mach/irqs.h> | ||
34 | #include <mach/dma.h> | ||
35 | |||
36 | static u8 pdma0_peri[] = { | ||
37 | DMACH_UART0_RX, | ||
38 | DMACH_UART0_TX, | ||
39 | DMACH_UART1_RX, | ||
40 | DMACH_UART1_TX, | ||
41 | DMACH_UART2_RX, | ||
42 | DMACH_UART2_TX, | ||
43 | DMACH_UART3_RX, | ||
44 | DMACH_UART3_TX, | ||
45 | DMACH_IRDA, | ||
46 | DMACH_I2S0_RX, | ||
47 | DMACH_I2S0_TX, | ||
48 | DMACH_I2S0S_TX, | ||
49 | DMACH_I2S1_RX, | ||
50 | DMACH_I2S1_TX, | ||
51 | DMACH_I2S2_RX, | ||
52 | DMACH_I2S2_TX, | ||
53 | DMACH_SPI0_RX, | ||
54 | DMACH_SPI0_TX, | ||
55 | DMACH_SPI1_RX, | ||
56 | DMACH_SPI1_TX, | ||
57 | DMACH_SPI2_RX, | ||
58 | DMACH_SPI2_TX, | ||
59 | DMACH_AC97_MICIN, | ||
60 | DMACH_AC97_PCMIN, | ||
61 | DMACH_AC97_PCMOUT, | ||
62 | DMACH_EXTERNAL, | ||
63 | DMACH_PWM, | ||
64 | DMACH_SPDIF, | ||
65 | DMACH_HSI_RX, | ||
66 | DMACH_HSI_TX, | ||
67 | }; | ||
68 | |||
69 | static struct dma_pl330_platdata s5pc100_pdma0_pdata = { | ||
70 | .nr_valid_peri = ARRAY_SIZE(pdma0_peri), | ||
71 | .peri_id = pdma0_peri, | ||
72 | }; | ||
73 | |||
74 | static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, | ||
75 | S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata); | ||
76 | |||
77 | static u8 pdma1_peri[] = { | ||
78 | DMACH_UART0_RX, | ||
79 | DMACH_UART0_TX, | ||
80 | DMACH_UART1_RX, | ||
81 | DMACH_UART1_TX, | ||
82 | DMACH_UART2_RX, | ||
83 | DMACH_UART2_TX, | ||
84 | DMACH_UART3_RX, | ||
85 | DMACH_UART3_TX, | ||
86 | DMACH_IRDA, | ||
87 | DMACH_I2S0_RX, | ||
88 | DMACH_I2S0_TX, | ||
89 | DMACH_I2S0S_TX, | ||
90 | DMACH_I2S1_RX, | ||
91 | DMACH_I2S1_TX, | ||
92 | DMACH_I2S2_RX, | ||
93 | DMACH_I2S2_TX, | ||
94 | DMACH_SPI0_RX, | ||
95 | DMACH_SPI0_TX, | ||
96 | DMACH_SPI1_RX, | ||
97 | DMACH_SPI1_TX, | ||
98 | DMACH_SPI2_RX, | ||
99 | DMACH_SPI2_TX, | ||
100 | DMACH_PCM0_RX, | ||
101 | DMACH_PCM0_TX, | ||
102 | DMACH_PCM1_RX, | ||
103 | DMACH_PCM1_TX, | ||
104 | DMACH_MSM_REQ0, | ||
105 | DMACH_MSM_REQ1, | ||
106 | DMACH_MSM_REQ2, | ||
107 | DMACH_MSM_REQ3, | ||
108 | }; | ||
109 | |||
110 | static struct dma_pl330_platdata s5pc100_pdma1_pdata = { | ||
111 | .nr_valid_peri = ARRAY_SIZE(pdma1_peri), | ||
112 | .peri_id = pdma1_peri, | ||
113 | }; | ||
114 | |||
115 | static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, | ||
116 | S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata); | ||
117 | |||
118 | static int __init s5pc100_dma_init(void) | ||
119 | { | ||
120 | dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); | ||
121 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); | ||
122 | amba_device_register(&s5pc100_pdma0_device, &iomem_resource); | ||
123 | |||
124 | dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); | ||
125 | dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); | ||
126 | amba_device_register(&s5pc100_pdma1_device, &iomem_resource); | ||
127 | |||
128 | return 0; | ||
129 | } | ||
130 | arch_initcall(s5pc100_dma_init); | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S deleted file mode 100644 index 22c23859e45e..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S +++ /dev/null | |||
@@ -1,39 +0,0 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/debug-macro.S | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * | ||
7 | * Based on mach-s3c6400/include/mach/debug-macro.S | ||
8 | * | ||
9 | * This program is free software; you can redistribute it and/or modify | ||
10 | * it under the terms of the GNU General Public License version 2 as | ||
11 | * published by the Free Software Foundation. | ||
12 | */ | ||
13 | |||
14 | /* pull in the relevant register and map files. */ | ||
15 | |||
16 | #include <linux/serial_s3c.h> | ||
17 | #include <mach/map.h> | ||
18 | |||
19 | /* note, for the boot process to work we have to keep the UART | ||
20 | * virtual address aligned to an 1MiB boundary for the L1 | ||
21 | * mapping the head code makes. We keep the UART virtual address | ||
22 | * aligned and add in the offset when we load the value here. | ||
23 | */ | ||
24 | |||
25 | .macro addruart, rp, rv, tmp | ||
26 | ldr \rp, = S3C_PA_UART | ||
27 | ldr \rv, = S3C_VA_UART | ||
28 | #if CONFIG_DEBUG_S3C_UART != 0 | ||
29 | add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART) | ||
30 | add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART) | ||
31 | #endif | ||
32 | .endm | ||
33 | |||
34 | /* include the reset of the code which will do the work, we're only | ||
35 | * compiling for a single cpu processor type so the default of s3c2440 | ||
36 | * will be fine with us. | ||
37 | */ | ||
38 | |||
39 | #include <debug/samsung.S> | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h deleted file mode 100644 index 201842a3769e..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/dma.h +++ /dev/null | |||
@@ -1,26 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Samsung Electronics Co. Ltd. | ||
3 | * Jaswinder Singh <jassi.brar@samsung.com> | ||
4 | * | ||
5 | * This program is free software; you can redistribute it and/or modify | ||
6 | * it under the terms of the GNU General Public License as published by | ||
7 | * the Free Software Foundation; either version 2 of the License, or | ||
8 | * (at your option) any later version. | ||
9 | * | ||
10 | * This program is distributed in the hope that it will be useful, | ||
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
13 | * GNU General Public License for more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program; if not, write to the Free Software | ||
17 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | ||
18 | */ | ||
19 | |||
20 | #ifndef __MACH_DMA_H | ||
21 | #define __MACH_DMA_H | ||
22 | |||
23 | /* This platform uses the common DMA API driver for PL330 */ | ||
24 | #include <plat/dma-pl330.h> | ||
25 | |||
26 | #endif /* __MACH_DMA_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S deleted file mode 100644 index bad0700457db..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S +++ /dev/null | |||
@@ -1,19 +0,0 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/entry-macro.S | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Based on mach-s3c6400/include/mach/entry-macro.S | ||
7 | * | ||
8 | * Low-level IRQ helper macros for the Samsung S5PC1XX series | ||
9 | * | ||
10 | * This file is licensed under the terms of the GNU General Public | ||
11 | * License version 2. This program is licensed "as is" without any | ||
12 | * warranty of any kind, whether express or implied. | ||
13 | */ | ||
14 | |||
15 | .macro get_irqnr_preamble, base, tmp | ||
16 | .endm | ||
17 | |||
18 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
19 | .endm | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h deleted file mode 100644 index 5e1a924b595f..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/gpio.h +++ /dev/null | |||
@@ -1,144 +0,0 @@ | |||
1 | /* arch/arm/mach-s5pc100/include/mach/gpio.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - GPIO lib support | ||
7 | * | ||
8 | * Base on mach-s3c6400/include/mach/gpio.h | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #ifndef __ASM_ARCH_GPIO_H | ||
16 | #define __ASM_ARCH_GPIO_H __FILE__ | ||
17 | |||
18 | /* GPIO bank sizes */ | ||
19 | #define S5PC100_GPIO_A0_NR (8) | ||
20 | #define S5PC100_GPIO_A1_NR (5) | ||
21 | #define S5PC100_GPIO_B_NR (8) | ||
22 | #define S5PC100_GPIO_C_NR (5) | ||
23 | #define S5PC100_GPIO_D_NR (7) | ||
24 | #define S5PC100_GPIO_E0_NR (8) | ||
25 | #define S5PC100_GPIO_E1_NR (6) | ||
26 | #define S5PC100_GPIO_F0_NR (8) | ||
27 | #define S5PC100_GPIO_F1_NR (8) | ||
28 | #define S5PC100_GPIO_F2_NR (8) | ||
29 | #define S5PC100_GPIO_F3_NR (4) | ||
30 | #define S5PC100_GPIO_G0_NR (8) | ||
31 | #define S5PC100_GPIO_G1_NR (3) | ||
32 | #define S5PC100_GPIO_G2_NR (7) | ||
33 | #define S5PC100_GPIO_G3_NR (7) | ||
34 | #define S5PC100_GPIO_H0_NR (8) | ||
35 | #define S5PC100_GPIO_H1_NR (8) | ||
36 | #define S5PC100_GPIO_H2_NR (8) | ||
37 | #define S5PC100_GPIO_H3_NR (8) | ||
38 | #define S5PC100_GPIO_I_NR (8) | ||
39 | #define S5PC100_GPIO_J0_NR (8) | ||
40 | #define S5PC100_GPIO_J1_NR (5) | ||
41 | #define S5PC100_GPIO_J2_NR (8) | ||
42 | #define S5PC100_GPIO_J3_NR (8) | ||
43 | #define S5PC100_GPIO_J4_NR (4) | ||
44 | #define S5PC100_GPIO_K0_NR (8) | ||
45 | #define S5PC100_GPIO_K1_NR (6) | ||
46 | #define S5PC100_GPIO_K2_NR (8) | ||
47 | #define S5PC100_GPIO_K3_NR (8) | ||
48 | #define S5PC100_GPIO_L0_NR (8) | ||
49 | #define S5PC100_GPIO_L1_NR (8) | ||
50 | #define S5PC100_GPIO_L2_NR (8) | ||
51 | #define S5PC100_GPIO_L3_NR (8) | ||
52 | #define S5PC100_GPIO_L4_NR (8) | ||
53 | |||
54 | /* GPIO bank numbes */ | ||
55 | |||
56 | /* CONFIG_S3C_GPIO_SPACE allows the user to select extra | ||
57 | * space for debugging purposes so that any accidental | ||
58 | * change from one gpio bank to another can be caught. | ||
59 | */ | ||
60 | |||
61 | #define S5PC100_GPIO_NEXT(__gpio) \ | ||
62 | ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) | ||
63 | |||
64 | enum s5p_gpio_number { | ||
65 | S5PC100_GPIO_A0_START = 0, | ||
66 | S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0), | ||
67 | S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1), | ||
68 | S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B), | ||
69 | S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C), | ||
70 | S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D), | ||
71 | S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0), | ||
72 | S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1), | ||
73 | S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0), | ||
74 | S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1), | ||
75 | S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2), | ||
76 | S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3), | ||
77 | S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0), | ||
78 | S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1), | ||
79 | S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2), | ||
80 | S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3), | ||
81 | S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0), | ||
82 | S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1), | ||
83 | S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2), | ||
84 | S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3), | ||
85 | S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I), | ||
86 | S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0), | ||
87 | S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1), | ||
88 | S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2), | ||
89 | S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3), | ||
90 | S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4), | ||
91 | S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0), | ||
92 | S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1), | ||
93 | S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2), | ||
94 | S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3), | ||
95 | S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0), | ||
96 | S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1), | ||
97 | S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2), | ||
98 | S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3), | ||
99 | S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4), | ||
100 | }; | ||
101 | |||
102 | /* S5PC100 GPIO number definitions. */ | ||
103 | #define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr)) | ||
104 | #define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr)) | ||
105 | #define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr)) | ||
106 | #define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr)) | ||
107 | #define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr)) | ||
108 | #define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr)) | ||
109 | #define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr)) | ||
110 | #define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr)) | ||
111 | #define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr)) | ||
112 | #define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr)) | ||
113 | #define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr)) | ||
114 | #define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr)) | ||
115 | #define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr)) | ||
116 | #define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr)) | ||
117 | #define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr)) | ||
118 | #define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr)) | ||
119 | #define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr)) | ||
120 | #define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr)) | ||
121 | #define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr)) | ||
122 | #define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr)) | ||
123 | #define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr)) | ||
124 | #define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr)) | ||
125 | #define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr)) | ||
126 | #define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr)) | ||
127 | #define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr)) | ||
128 | #define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr)) | ||
129 | #define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr)) | ||
130 | #define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr)) | ||
131 | #define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr)) | ||
132 | #define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr)) | ||
133 | #define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr)) | ||
134 | #define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) | ||
135 | #define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) | ||
136 | #define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) | ||
137 | |||
138 | /* It used the end of the S5PC100 gpios */ | ||
139 | #define S3C_GPIO_END S5PC100_GPIO_END | ||
140 | |||
141 | /* define the number of gpios we need to the one after the MP04() range */ | ||
142 | #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) | ||
143 | |||
144 | #endif /* __ASM_ARCH_GPIO_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h deleted file mode 100644 index 6b38618c2fd9..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/hardware.h +++ /dev/null | |||
@@ -1,14 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/hardware.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - Hardware support | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_HARDWARE_H | ||
10 | #define __ASM_ARCH_HARDWARE_H __FILE__ | ||
11 | |||
12 | /* currently nothing here, placeholder */ | ||
13 | |||
14 | #endif /* __ASM_ARCH_HARDWARE_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h deleted file mode 100644 index d2eb4757381f..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/irqs.h +++ /dev/null | |||
@@ -1,115 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/irqs.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - IRQ definitions | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_ARCH_IRQS_H | ||
10 | #define __ASM_ARCH_IRQS_H __FILE__ | ||
11 | |||
12 | #include <plat/irqs.h> | ||
13 | |||
14 | /* VIC0: system, DMA, timer */ | ||
15 | #define IRQ_EINT16_31 S5P_IRQ_VIC0(16) | ||
16 | #define IRQ_BATF S5P_IRQ_VIC0(17) | ||
17 | #define IRQ_MDMA S5P_IRQ_VIC0(18) | ||
18 | #define IRQ_PDMA0 S5P_IRQ_VIC0(19) | ||
19 | #define IRQ_PDMA1 S5P_IRQ_VIC0(20) | ||
20 | #define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21) | ||
21 | #define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22) | ||
22 | #define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23) | ||
23 | #define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24) | ||
24 | #define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25) | ||
25 | #define IRQ_SYSTIMER S5P_IRQ_VIC0(26) | ||
26 | #define IRQ_WDT S5P_IRQ_VIC0(27) | ||
27 | #define IRQ_RTC_ALARM S5P_IRQ_VIC0(28) | ||
28 | #define IRQ_RTC_TIC S5P_IRQ_VIC0(29) | ||
29 | #define IRQ_GPIOINT S5P_IRQ_VIC0(30) | ||
30 | |||
31 | /* VIC1: ARM, power, memory, connectivity */ | ||
32 | #define IRQ_PMU S5P_IRQ_VIC1(0) | ||
33 | #define IRQ_CORTEX1 S5P_IRQ_VIC1(1) | ||
34 | #define IRQ_CORTEX2 S5P_IRQ_VIC1(2) | ||
35 | #define IRQ_CORTEX3 S5P_IRQ_VIC1(3) | ||
36 | #define IRQ_CORTEX4 S5P_IRQ_VIC1(4) | ||
37 | #define IRQ_IEMAPC S5P_IRQ_VIC1(5) | ||
38 | #define IRQ_IEMIEC S5P_IRQ_VIC1(6) | ||
39 | #define IRQ_ONENAND S5P_IRQ_VIC1(7) | ||
40 | #define IRQ_NFC S5P_IRQ_VIC1(8) | ||
41 | #define IRQ_CFCON S5P_IRQ_VIC1(9) | ||
42 | #define IRQ_UART0 S5P_IRQ_VIC1(10) | ||
43 | #define IRQ_UART1 S5P_IRQ_VIC1(11) | ||
44 | #define IRQ_UART2 S5P_IRQ_VIC1(12) | ||
45 | #define IRQ_UART3 S5P_IRQ_VIC1(13) | ||
46 | #define IRQ_IIC S5P_IRQ_VIC1(14) | ||
47 | #define IRQ_SPI0 S5P_IRQ_VIC1(15) | ||
48 | #define IRQ_SPI1 S5P_IRQ_VIC1(16) | ||
49 | #define IRQ_SPI2 S5P_IRQ_VIC1(17) | ||
50 | #define IRQ_IRDA S5P_IRQ_VIC1(18) | ||
51 | #define IRQ_IIC2 S5P_IRQ_VIC1(19) | ||
52 | #define IRQ_IIC3 S5P_IRQ_VIC1(20) | ||
53 | #define IRQ_HSIRX S5P_IRQ_VIC1(21) | ||
54 | #define IRQ_HSITX S5P_IRQ_VIC1(22) | ||
55 | #define IRQ_UHOST S5P_IRQ_VIC1(23) | ||
56 | #define IRQ_OTG S5P_IRQ_VIC1(24) | ||
57 | #define IRQ_MSM S5P_IRQ_VIC1(25) | ||
58 | #define IRQ_HSMMC0 S5P_IRQ_VIC1(26) | ||
59 | #define IRQ_HSMMC1 S5P_IRQ_VIC1(27) | ||
60 | #define IRQ_HSMMC2 S5P_IRQ_VIC1(28) | ||
61 | #define IRQ_MIPICSI S5P_IRQ_VIC1(29) | ||
62 | #define IRQ_MIPIDSI S5P_IRQ_VIC1(30) | ||
63 | |||
64 | /* VIC2: multimedia, audio, security */ | ||
65 | #define IRQ_LCD0 S5P_IRQ_VIC2(0) | ||
66 | #define IRQ_LCD1 S5P_IRQ_VIC2(1) | ||
67 | #define IRQ_LCD2 S5P_IRQ_VIC2(2) | ||
68 | #define IRQ_LCD3 S5P_IRQ_VIC2(3) | ||
69 | #define IRQ_ROTATOR S5P_IRQ_VIC2(4) | ||
70 | #define IRQ_FIMC0 S5P_IRQ_VIC2(5) | ||
71 | #define IRQ_FIMC1 S5P_IRQ_VIC2(6) | ||
72 | #define IRQ_FIMC2 S5P_IRQ_VIC2(7) | ||
73 | #define IRQ_JPEG S5P_IRQ_VIC2(8) | ||
74 | #define IRQ_2D S5P_IRQ_VIC2(9) | ||
75 | #define IRQ_3D S5P_IRQ_VIC2(10) | ||
76 | #define IRQ_MIXER S5P_IRQ_VIC2(11) | ||
77 | #define IRQ_HDMI S5P_IRQ_VIC2(12) | ||
78 | #define IRQ_IIC1 S5P_IRQ_VIC2(13) | ||
79 | #define IRQ_MFC S5P_IRQ_VIC2(14) | ||
80 | #define IRQ_TVENC S5P_IRQ_VIC2(15) | ||
81 | #define IRQ_I2S0 S5P_IRQ_VIC2(16) | ||
82 | #define IRQ_I2S1 S5P_IRQ_VIC2(17) | ||
83 | #define IRQ_I2S2 S5P_IRQ_VIC2(18) | ||
84 | #define IRQ_AC97 S5P_IRQ_VIC2(19) | ||
85 | #define IRQ_PCM0 S5P_IRQ_VIC2(20) | ||
86 | #define IRQ_PCM1 S5P_IRQ_VIC2(21) | ||
87 | #define IRQ_SPDIF S5P_IRQ_VIC2(22) | ||
88 | #define IRQ_ADC S5P_IRQ_VIC2(23) | ||
89 | #define IRQ_PENDN S5P_IRQ_VIC2(24) | ||
90 | #define IRQ_TC IRQ_PENDN | ||
91 | #define IRQ_KEYPAD S5P_IRQ_VIC2(25) | ||
92 | #define IRQ_CG S5P_IRQ_VIC2(26) | ||
93 | #define IRQ_SEC S5P_IRQ_VIC2(27) | ||
94 | #define IRQ_SECRX S5P_IRQ_VIC2(28) | ||
95 | #define IRQ_SECTX S5P_IRQ_VIC2(29) | ||
96 | #define IRQ_SDMIRQ S5P_IRQ_VIC2(30) | ||
97 | #define IRQ_SDMFIQ S5P_IRQ_VIC2(31) | ||
98 | #define IRQ_VIC_END S5P_IRQ_VIC2(31) | ||
99 | |||
100 | #define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) | ||
101 | #define S5P_EINT_BASE2 (IRQ_VIC_END + 1) | ||
102 | |||
103 | /* GPIO interrupt */ | ||
104 | #define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) | ||
105 | #define S5P_GPIOINT_GROUP_MAXNR 21 | ||
106 | |||
107 | /* Set the default NR_IRQS */ | ||
108 | #define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) | ||
109 | |||
110 | /* Compatibility */ | ||
111 | #define IRQ_LCD_FIFO IRQ_LCD0 | ||
112 | #define IRQ_LCD_VSYNC IRQ_LCD1 | ||
113 | #define IRQ_LCD_SYSTEM IRQ_LCD2 | ||
114 | |||
115 | #endif /* __ASM_ARCH_IRQS_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h deleted file mode 100644 index 2550b6112b82..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/map.h +++ /dev/null | |||
@@ -1,137 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/map.h | ||
2 | * | ||
3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * Copyright 2009 Samsung Electronics Co. | ||
7 | * Byungho Min <bhmin@samsung.com> | ||
8 | * | ||
9 | * S5PC100 - Memory map definitions | ||
10 | * | ||
11 | * This program is free software; you can redistribute it and/or modify | ||
12 | * it under the terms of the GNU General Public License version 2 as | ||
13 | * published by the Free Software Foundation. | ||
14 | */ | ||
15 | |||
16 | #ifndef __ASM_ARCH_MAP_H | ||
17 | #define __ASM_ARCH_MAP_H __FILE__ | ||
18 | |||
19 | #include <plat/map-base.h> | ||
20 | #include <plat/map-s5p.h> | ||
21 | |||
22 | #define S5PC100_PA_SDRAM 0x20000000 | ||
23 | |||
24 | #define S5PC100_PA_ONENAND 0xE7100000 | ||
25 | #define S5PC100_PA_ONENAND_BUF 0xB0000000 | ||
26 | |||
27 | #define S5PC100_PA_CHIPID 0xE0000000 | ||
28 | |||
29 | #define S5PC100_PA_SYSCON 0xE0100000 | ||
30 | |||
31 | #define S5PC100_PA_OTHERS 0xE0200000 | ||
32 | |||
33 | #define S5PC100_PA_GPIO 0xE0300000 | ||
34 | |||
35 | #define S5PC100_PA_VIC0 0xE4000000 | ||
36 | #define S5PC100_PA_VIC1 0xE4100000 | ||
37 | #define S5PC100_PA_VIC2 0xE4200000 | ||
38 | |||
39 | #define S5PC100_PA_SROMC 0xE7000000 | ||
40 | |||
41 | #define S5PC100_PA_CFCON 0xE7800000 | ||
42 | |||
43 | #define S5PC100_PA_MDMA 0xE8100000 | ||
44 | #define S5PC100_PA_PDMA0 0xE9000000 | ||
45 | #define S5PC100_PA_PDMA1 0xE9200000 | ||
46 | |||
47 | #define S5PC100_PA_TIMER 0xEA000000 | ||
48 | #define S5PC100_PA_SYSTIMER 0xEA100000 | ||
49 | #define S5PC100_PA_WATCHDOG 0xEA200000 | ||
50 | #define S5PC100_PA_RTC 0xEA300000 | ||
51 | |||
52 | #define S5PC100_PA_UART 0xEC000000 | ||
53 | |||
54 | #define S5PC100_PA_IIC0 0xEC100000 | ||
55 | #define S5PC100_PA_IIC1 0xEC200000 | ||
56 | |||
57 | #define S5PC100_PA_SPI0 0xEC300000 | ||
58 | #define S5PC100_PA_SPI1 0xEC400000 | ||
59 | #define S5PC100_PA_SPI2 0xEC500000 | ||
60 | |||
61 | #define S5PC100_PA_USB_HSOTG 0xED200000 | ||
62 | #define S5PC100_PA_USB_HSPHY 0xED300000 | ||
63 | |||
64 | #define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) | ||
65 | |||
66 | #define S5PC100_PA_FB 0xEE000000 | ||
67 | |||
68 | #define S5PC100_PA_FIMC0 0xEE200000 | ||
69 | #define S5PC100_PA_FIMC1 0xEE300000 | ||
70 | #define S5PC100_PA_FIMC2 0xEE400000 | ||
71 | |||
72 | #define S5PC100_PA_I2S0 0xF2000000 | ||
73 | #define S5PC100_PA_I2S1 0xF2100000 | ||
74 | #define S5PC100_PA_I2S2 0xF2200000 | ||
75 | |||
76 | #define S5PC100_PA_AC97 0xF2300000 | ||
77 | |||
78 | #define S5PC100_PA_PCM0 0xF2400000 | ||
79 | #define S5PC100_PA_PCM1 0xF2500000 | ||
80 | |||
81 | #define S5PC100_PA_SPDIF 0xF2600000 | ||
82 | |||
83 | #define S5PC100_PA_TSADC 0xF3000000 | ||
84 | |||
85 | #define S5PC100_PA_KEYPAD 0xF3100000 | ||
86 | |||
87 | /* Compatibiltiy Defines */ | ||
88 | |||
89 | #define S3C_PA_FB S5PC100_PA_FB | ||
90 | #define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) | ||
91 | #define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) | ||
92 | #define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) | ||
93 | #define S3C_PA_IIC S5PC100_PA_IIC0 | ||
94 | #define S3C_PA_IIC1 S5PC100_PA_IIC1 | ||
95 | #define S3C_PA_KEYPAD S5PC100_PA_KEYPAD | ||
96 | #define S3C_PA_ONENAND S5PC100_PA_ONENAND | ||
97 | #define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF | ||
98 | #define S3C_PA_RTC S5PC100_PA_RTC | ||
99 | #define S3C_PA_TSADC S5PC100_PA_TSADC | ||
100 | #define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG | ||
101 | #define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY | ||
102 | #define S3C_PA_WDT S5PC100_PA_WATCHDOG | ||
103 | #define S3C_PA_SPI0 S5PC100_PA_SPI0 | ||
104 | #define S3C_PA_SPI1 S5PC100_PA_SPI1 | ||
105 | #define S3C_PA_SPI2 S5PC100_PA_SPI2 | ||
106 | |||
107 | #define S5P_PA_CHIPID S5PC100_PA_CHIPID | ||
108 | #define S5P_PA_FIMC0 S5PC100_PA_FIMC0 | ||
109 | #define S5P_PA_FIMC1 S5PC100_PA_FIMC1 | ||
110 | #define S5P_PA_FIMC2 S5PC100_PA_FIMC2 | ||
111 | #define S5P_PA_SDRAM S5PC100_PA_SDRAM | ||
112 | #define S5P_PA_SROMC S5PC100_PA_SROMC | ||
113 | #define S5P_PA_SYSCON S5PC100_PA_SYSCON | ||
114 | #define S5P_PA_TIMER S5PC100_PA_TIMER | ||
115 | |||
116 | #define SAMSUNG_PA_ADC S5PC100_PA_TSADC | ||
117 | #define SAMSUNG_PA_CFCON S5PC100_PA_CFCON | ||
118 | #define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD | ||
119 | #define SAMSUNG_PA_TIMER S5PC100_PA_TIMER | ||
120 | |||
121 | #define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) | ||
122 | |||
123 | #define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M) | ||
124 | |||
125 | /* UART */ | ||
126 | |||
127 | #define S3C_PA_UART S5PC100_PA_UART | ||
128 | |||
129 | #define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) | ||
130 | #define S5P_PA_UART0 S5P_PA_UART(0) | ||
131 | #define S5P_PA_UART1 S5P_PA_UART(1) | ||
132 | #define S5P_PA_UART2 S5P_PA_UART(2) | ||
133 | #define S5P_PA_UART3 S5P_PA_UART(3) | ||
134 | |||
135 | #define S5P_SZ_UART SZ_256 | ||
136 | |||
137 | #endif /* __ASM_ARCH_MAP_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h deleted file mode 100644 index bc92da2e0ba2..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h +++ /dev/null | |||
@@ -1,80 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * S5PC100 - Clock register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_CLOCK_H | ||
14 | #define __ASM_ARCH_REGS_CLOCK_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | #define S5P_CLKREG(x) (S3C_VA_SYS + (x)) | ||
19 | |||
20 | #define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x)) | ||
21 | |||
22 | #define S5P_APLL_LOCK S5P_CLKREG(0x00) | ||
23 | #define S5P_MPLL_LOCK S5P_CLKREG(0x04) | ||
24 | #define S5P_EPLL_LOCK S5P_CLKREG(0x08) | ||
25 | #define S5P_HPLL_LOCK S5P_CLKREG(0x0C) | ||
26 | |||
27 | #define S5P_APLL_CON S5P_CLKREG(0x100) | ||
28 | #define S5P_MPLL_CON S5P_CLKREG(0x104) | ||
29 | #define S5P_EPLL_CON S5P_CLKREG(0x108) | ||
30 | #define S5P_HPLL_CON S5P_CLKREG(0x10C) | ||
31 | |||
32 | #define S5P_CLK_SRC0 S5P_CLKREG(0x200) | ||
33 | #define S5P_CLK_SRC1 S5P_CLKREG(0x204) | ||
34 | #define S5P_CLK_SRC2 S5P_CLKREG(0x208) | ||
35 | #define S5P_CLK_SRC3 S5P_CLKREG(0x20C) | ||
36 | |||
37 | #define S5P_CLK_DIV0 S5P_CLKREG(0x300) | ||
38 | #define S5P_CLK_DIV1 S5P_CLKREG(0x304) | ||
39 | #define S5P_CLK_DIV2 S5P_CLKREG(0x308) | ||
40 | #define S5P_CLK_DIV3 S5P_CLKREG(0x30C) | ||
41 | #define S5P_CLK_DIV4 S5P_CLKREG(0x310) | ||
42 | |||
43 | #define S5P_CLK_OUT S5P_CLKREG(0x400) | ||
44 | |||
45 | #define S5P_CLKGATE_D00 S5P_CLKREG(0x500) | ||
46 | #define S5P_CLKGATE_D01 S5P_CLKREG(0x504) | ||
47 | #define S5P_CLKGATE_D02 S5P_CLKREG(0x508) | ||
48 | |||
49 | #define S5P_CLKGATE_D10 S5P_CLKREG(0x520) | ||
50 | #define S5P_CLKGATE_D11 S5P_CLKREG(0x524) | ||
51 | #define S5P_CLKGATE_D12 S5P_CLKREG(0x528) | ||
52 | #define S5P_CLKGATE_D13 S5P_CLKREG(0x52C) | ||
53 | #define S5P_CLKGATE_D14 S5P_CLKREG(0x530) | ||
54 | #define S5P_CLKGATE_D15 S5P_CLKREG(0x534) | ||
55 | |||
56 | #define S5P_CLKGATE_D20 S5P_CLKREG(0x540) | ||
57 | |||
58 | #define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560) | ||
59 | #define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564) | ||
60 | |||
61 | /* CLKDIV0 */ | ||
62 | #define S5P_CLKDIV0_D0_MASK (0x7<<8) | ||
63 | #define S5P_CLKDIV0_D0_SHIFT (8) | ||
64 | #define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12) | ||
65 | #define S5P_CLKDIV0_PCLKD0_SHIFT (12) | ||
66 | |||
67 | /* CLKDIV1 */ | ||
68 | #define S5P_CLKDIV1_D1_MASK (0x7<<12) | ||
69 | #define S5P_CLKDIV1_D1_SHIFT (12) | ||
70 | #define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) | ||
71 | #define S5P_CLKDIV1_PCLKD1_SHIFT (16) | ||
72 | |||
73 | #define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) | ||
74 | #define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200) | ||
75 | |||
76 | #define S5PC100_SWRESET_RESETVAL 0xc100 | ||
77 | |||
78 | #define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 | ||
79 | |||
80 | #endif /* __ASM_ARCH_REGS_CLOCK_H */ | ||
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h deleted file mode 100644 index 0bf73209ec7b..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h +++ /dev/null | |||
@@ -1,38 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - GPIO register definitions | ||
7 | */ | ||
8 | |||
9 | #ifndef __ASM_MACH_S5PC100_REGS_GPIO_H | ||
10 | #define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__ | ||
11 | |||
12 | #include <mach/map.h> | ||
13 | |||
14 | #define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00) | ||
15 | #define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4)) | ||
16 | |||
17 | #define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) | ||
18 | #define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4)) | ||
19 | |||
20 | #define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00) | ||
21 | #define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4)) | ||
22 | |||
23 | #define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40) | ||
24 | #define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4)) | ||
25 | |||
26 | #define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) | ||
27 | |||
28 | #define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) | ||
29 | |||
30 | #define EINT_MODE S3C_GPIO_SFN(0x2) | ||
31 | |||
32 | #define EINT_GPIO_0(x) S5PC100_GPH0(x) | ||
33 | #define EINT_GPIO_1(x) S5PC100_GPH1(x) | ||
34 | #define EINT_GPIO_2(x) S5PC100_GPH2(x) | ||
35 | #define EINT_GPIO_3(x) S5PC100_GPH3(x) | ||
36 | |||
37 | #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ | ||
38 | |||
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h deleted file mode 100644 index 761627897f30..000000000000 --- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h +++ /dev/null | |||
@@ -1,18 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * S5PC100 - IRQ register definitions | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #ifndef __ASM_ARCH_REGS_IRQ_H | ||
14 | #define __ASM_ARCH_REGS_IRQ_H __FILE__ | ||
15 | |||
16 | #include <mach/map.h> | ||
17 | |||
18 | #endif /* __ASM_ARCH_REGS_IRQ_H */ | ||
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c deleted file mode 100644 index 668af3ac31f3..000000000000 --- a/arch/arm/mach-s5pc100/mach-smdkc100.c +++ /dev/null | |||
@@ -1,264 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/mach-smdkc100.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Author: Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | * | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/types.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/list.h> | ||
16 | #include <linux/timer.h> | ||
17 | #include <linux/init.h> | ||
18 | #include <linux/serial_core.h> | ||
19 | #include <linux/serial_s3c.h> | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/io.h> | ||
22 | #include <linux/gpio.h> | ||
23 | #include <linux/i2c.h> | ||
24 | #include <linux/fb.h> | ||
25 | #include <linux/delay.h> | ||
26 | #include <linux/input.h> | ||
27 | #include <linux/pwm_backlight.h> | ||
28 | |||
29 | #include <asm/mach/arch.h> | ||
30 | #include <asm/mach/map.h> | ||
31 | |||
32 | #include <mach/map.h> | ||
33 | #include <mach/regs-gpio.h> | ||
34 | |||
35 | #include <video/platform_lcd.h> | ||
36 | #include <video/samsung_fimd.h> | ||
37 | |||
38 | #include <asm/irq.h> | ||
39 | #include <asm/mach-types.h> | ||
40 | |||
41 | #include <plat/gpio-cfg.h> | ||
42 | |||
43 | #include <plat/clock.h> | ||
44 | #include <plat/devs.h> | ||
45 | #include <plat/cpu.h> | ||
46 | #include <plat/fb.h> | ||
47 | #include <linux/platform_data/i2c-s3c2410.h> | ||
48 | #include <linux/platform_data/ata-samsung_cf.h> | ||
49 | #include <plat/adc.h> | ||
50 | #include <plat/keypad.h> | ||
51 | #include <linux/platform_data/touchscreen-s3c2410.h> | ||
52 | #include <linux/platform_data/asoc-s3c.h> | ||
53 | #include <plat/backlight.h> | ||
54 | #include <plat/samsung-time.h> | ||
55 | |||
56 | #include "common.h" | ||
57 | |||
58 | /* Following are default values for UCON, ULCON and UFCON UART registers */ | ||
59 | #define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ | ||
60 | S3C2410_UCON_RXILEVEL | \ | ||
61 | S3C2410_UCON_TXIRQMODE | \ | ||
62 | S3C2410_UCON_RXIRQMODE | \ | ||
63 | S3C2410_UCON_RXFIFO_TOI | \ | ||
64 | S3C2443_UCON_RXERR_IRQEN) | ||
65 | |||
66 | #define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8 | ||
67 | |||
68 | #define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ | ||
69 | S3C2440_UFCON_RXTRIG8 | \ | ||
70 | S3C2440_UFCON_TXTRIG16) | ||
71 | |||
72 | static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { | ||
73 | [0] = { | ||
74 | .hwport = 0, | ||
75 | .flags = 0, | ||
76 | .ucon = SMDKC100_UCON_DEFAULT, | ||
77 | .ulcon = SMDKC100_ULCON_DEFAULT, | ||
78 | .ufcon = SMDKC100_UFCON_DEFAULT, | ||
79 | }, | ||
80 | [1] = { | ||
81 | .hwport = 1, | ||
82 | .flags = 0, | ||
83 | .ucon = SMDKC100_UCON_DEFAULT, | ||
84 | .ulcon = SMDKC100_ULCON_DEFAULT, | ||
85 | .ufcon = SMDKC100_UFCON_DEFAULT, | ||
86 | }, | ||
87 | [2] = { | ||
88 | .hwport = 2, | ||
89 | .flags = 0, | ||
90 | .ucon = SMDKC100_UCON_DEFAULT, | ||
91 | .ulcon = SMDKC100_ULCON_DEFAULT, | ||
92 | .ufcon = SMDKC100_UFCON_DEFAULT, | ||
93 | }, | ||
94 | [3] = { | ||
95 | .hwport = 3, | ||
96 | .flags = 0, | ||
97 | .ucon = SMDKC100_UCON_DEFAULT, | ||
98 | .ulcon = SMDKC100_ULCON_DEFAULT, | ||
99 | .ufcon = SMDKC100_UFCON_DEFAULT, | ||
100 | }, | ||
101 | }; | ||
102 | |||
103 | /* I2C0 */ | ||
104 | static struct i2c_board_info i2c_devs0[] __initdata = { | ||
105 | {I2C_BOARD_INFO("wm8580", 0x1b),}, | ||
106 | }; | ||
107 | |||
108 | /* I2C1 */ | ||
109 | static struct i2c_board_info i2c_devs1[] __initdata = { | ||
110 | }; | ||
111 | |||
112 | /* LCD power controller */ | ||
113 | static void smdkc100_lcd_power_set(struct plat_lcd_data *pd, | ||
114 | unsigned int power) | ||
115 | { | ||
116 | if (power) { | ||
117 | /* module reset */ | ||
118 | gpio_direction_output(S5PC100_GPH0(6), 1); | ||
119 | mdelay(100); | ||
120 | gpio_direction_output(S5PC100_GPH0(6), 0); | ||
121 | mdelay(10); | ||
122 | gpio_direction_output(S5PC100_GPH0(6), 1); | ||
123 | mdelay(10); | ||
124 | } | ||
125 | } | ||
126 | |||
127 | static struct plat_lcd_data smdkc100_lcd_power_data = { | ||
128 | .set_power = smdkc100_lcd_power_set, | ||
129 | }; | ||
130 | |||
131 | static struct platform_device smdkc100_lcd_powerdev = { | ||
132 | .name = "platform-lcd", | ||
133 | .dev.parent = &s3c_device_fb.dev, | ||
134 | .dev.platform_data = &smdkc100_lcd_power_data, | ||
135 | }; | ||
136 | |||
137 | /* Frame Buffer */ | ||
138 | static struct s3c_fb_pd_win smdkc100_fb_win0 = { | ||
139 | .max_bpp = 32, | ||
140 | .default_bpp = 16, | ||
141 | .xres = 800, | ||
142 | .yres = 480, | ||
143 | }; | ||
144 | |||
145 | static struct fb_videomode smdkc100_lcd_timing = { | ||
146 | .left_margin = 8, | ||
147 | .right_margin = 13, | ||
148 | .upper_margin = 7, | ||
149 | .lower_margin = 5, | ||
150 | .hsync_len = 3, | ||
151 | .vsync_len = 1, | ||
152 | .xres = 800, | ||
153 | .yres = 480, | ||
154 | .refresh = 80, | ||
155 | }; | ||
156 | |||
157 | static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { | ||
158 | .win[0] = &smdkc100_fb_win0, | ||
159 | .vtiming = &smdkc100_lcd_timing, | ||
160 | .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, | ||
161 | .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, | ||
162 | .setup_gpio = s5pc100_fb_gpio_setup_24bpp, | ||
163 | }; | ||
164 | |||
165 | static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = { | ||
166 | .setup_gpio = s5pc100_ide_setup_gpio, | ||
167 | }; | ||
168 | |||
169 | static uint32_t smdkc100_keymap[] __initdata = { | ||
170 | /* KEY(row, col, keycode) */ | ||
171 | KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), | ||
172 | KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), | ||
173 | KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), | ||
174 | KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) | ||
175 | }; | ||
176 | |||
177 | static struct matrix_keymap_data smdkc100_keymap_data __initdata = { | ||
178 | .keymap = smdkc100_keymap, | ||
179 | .keymap_size = ARRAY_SIZE(smdkc100_keymap), | ||
180 | }; | ||
181 | |||
182 | static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = { | ||
183 | .keymap_data = &smdkc100_keymap_data, | ||
184 | .rows = 2, | ||
185 | .cols = 8, | ||
186 | }; | ||
187 | |||
188 | static struct platform_device *smdkc100_devices[] __initdata = { | ||
189 | &s3c_device_adc, | ||
190 | &s3c_device_cfcon, | ||
191 | &s3c_device_i2c0, | ||
192 | &s3c_device_i2c1, | ||
193 | &s3c_device_fb, | ||
194 | &s3c_device_hsmmc0, | ||
195 | &s3c_device_hsmmc1, | ||
196 | &s3c_device_hsmmc2, | ||
197 | &samsung_device_pwm, | ||
198 | &s3c_device_ts, | ||
199 | &s3c_device_wdt, | ||
200 | &smdkc100_lcd_powerdev, | ||
201 | &s5pc100_device_iis0, | ||
202 | &samsung_device_keypad, | ||
203 | &s5pc100_device_ac97, | ||
204 | &s3c_device_rtc, | ||
205 | &s5p_device_fimc0, | ||
206 | &s5p_device_fimc1, | ||
207 | &s5p_device_fimc2, | ||
208 | &s5pc100_device_spdif, | ||
209 | }; | ||
210 | |||
211 | /* LCD Backlight data */ | ||
212 | static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = { | ||
213 | .no = S5PC100_GPD(0), | ||
214 | .func = S3C_GPIO_SFN(2), | ||
215 | }; | ||
216 | |||
217 | static struct platform_pwm_backlight_data smdkc100_bl_data = { | ||
218 | .pwm_id = 0, | ||
219 | .enable_gpio = -1, | ||
220 | }; | ||
221 | |||
222 | static void __init smdkc100_map_io(void) | ||
223 | { | ||
224 | s5pc100_init_io(NULL, 0); | ||
225 | s3c24xx_init_clocks(12000000); | ||
226 | s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); | ||
227 | samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); | ||
228 | } | ||
229 | |||
230 | static void __init smdkc100_machine_init(void) | ||
231 | { | ||
232 | s3c24xx_ts_set_platdata(NULL); | ||
233 | |||
234 | /* I2C */ | ||
235 | s3c_i2c0_set_platdata(NULL); | ||
236 | s3c_i2c1_set_platdata(NULL); | ||
237 | i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); | ||
238 | i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); | ||
239 | |||
240 | s3c_fb_set_platdata(&smdkc100_lcd_pdata); | ||
241 | s3c_ide_set_platdata(&smdkc100_ide_pdata); | ||
242 | |||
243 | samsung_keypad_set_platdata(&smdkc100_keypad_data); | ||
244 | |||
245 | s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD); | ||
246 | |||
247 | /* LCD init */ | ||
248 | gpio_request(S5PC100_GPH0(6), "GPH0"); | ||
249 | smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); | ||
250 | |||
251 | platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); | ||
252 | |||
253 | samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data); | ||
254 | } | ||
255 | |||
256 | MACHINE_START(SMDKC100, "SMDKC100") | ||
257 | /* Maintainer: Byungho Min <bhmin@samsung.com> */ | ||
258 | .atag_offset = 0x100, | ||
259 | .init_irq = s5pc100_init_irq, | ||
260 | .map_io = smdkc100_map_io, | ||
261 | .init_machine = smdkc100_machine_init, | ||
262 | .init_time = samsung_timer_init, | ||
263 | .restart = s5pc100_restart, | ||
264 | MACHINE_END | ||
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c deleted file mode 100644 index 8978e4cf9ed5..000000000000 --- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c +++ /dev/null | |||
@@ -1,35 +0,0 @@ | |||
1 | /* | ||
2 | * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c | ||
3 | * | ||
4 | * Copyright 2009 Samsung Electronics | ||
5 | * | ||
6 | * Base S5PC100 setup information for 24bpp LCD framebuffer | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/types.h> | ||
15 | #include <linux/fb.h> | ||
16 | #include <linux/gpio.h> | ||
17 | |||
18 | #include <mach/map.h> | ||
19 | #include <plat/fb.h> | ||
20 | #include <plat/gpio-cfg.h> | ||
21 | |||
22 | #define DISR_OFFSET 0x7008 | ||
23 | |||
24 | static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr) | ||
25 | { | ||
26 | s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2)); | ||
27 | } | ||
28 | |||
29 | void s5pc100_fb_gpio_setup_24bpp(void) | ||
30 | { | ||
31 | s5pc100_fb_setgpios(S5PC100_GPF0(0), 8); | ||
32 | s5pc100_fb_setgpios(S5PC100_GPF1(0), 8); | ||
33 | s5pc100_fb_setgpios(S5PC100_GPF2(0), 8); | ||
34 | s5pc100_fb_setgpios(S5PC100_GPF3(0), 4); | ||
35 | } | ||
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c deleted file mode 100644 index 89a6a769d622..000000000000 --- a/arch/arm/mach-s5pc100/setup-i2c0.c +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/setup-i2c0.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Base S5PC100 I2C bus 0 gpio configuration | ||
7 | * | ||
8 | * Based on plat-s3c64xx/setup-i2c0.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <linux/gpio.h> | ||
21 | #include <linux/platform_data/i2c-s3c2410.h> | ||
22 | #include <plat/gpio-cfg.h> | ||
23 | |||
24 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | ||
25 | { | ||
26 | s3c_gpio_cfgall_range(S5PC100_GPD(3), 2, | ||
27 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
28 | } | ||
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c deleted file mode 100644 index faa667ef02cb..000000000000 --- a/arch/arm/mach-s5pc100/setup-i2c1.c +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/setup-i2c1.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Electronics Co. | ||
4 | * Byungho Min <bhmin@samsung.com> | ||
5 | * | ||
6 | * Base S5PC100 I2C bus 1 gpio configuration | ||
7 | * | ||
8 | * Based on plat-s3c64xx/setup-i2c1.c | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License version 2 as | ||
12 | * published by the Free Software Foundation. | ||
13 | */ | ||
14 | |||
15 | #include <linux/kernel.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; /* don't need the contents */ | ||
19 | |||
20 | #include <linux/gpio.h> | ||
21 | #include <linux/platform_data/i2c-s3c2410.h> | ||
22 | #include <plat/gpio-cfg.h> | ||
23 | |||
24 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) | ||
25 | { | ||
26 | s3c_gpio_cfgall_range(S5PC100_GPD(5), 2, | ||
27 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
28 | } | ||
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c deleted file mode 100644 index 223aae044466..000000000000 --- a/arch/arm/mach-s5pc100/setup-ide.c +++ /dev/null | |||
@@ -1,57 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/setup-ide.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com | ||
5 | * | ||
6 | * S5PC100 setup information for IDE | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/kernel.h> | ||
14 | #include <linux/gpio.h> | ||
15 | #include <linux/io.h> | ||
16 | |||
17 | #include <mach/regs-clock.h> | ||
18 | #include <plat/gpio-cfg.h> | ||
19 | |||
20 | static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr) | ||
21 | { | ||
22 | s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4)); | ||
23 | |||
24 | for (; nr > 0; nr--, base++) | ||
25 | s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4); | ||
26 | } | ||
27 | |||
28 | void s5pc100_ide_setup_gpio(void) | ||
29 | { | ||
30 | u32 reg; | ||
31 | |||
32 | /* Independent CF interface, CF chip select configuration */ | ||
33 | reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f); | ||
34 | writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG); | ||
35 | |||
36 | /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ | ||
37 | s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8); | ||
38 | |||
39 | /*CF_Data[0 - 7] */ | ||
40 | s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8); | ||
41 | |||
42 | /* CF_Data[8 - 15] */ | ||
43 | s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8); | ||
44 | |||
45 | /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ | ||
46 | s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4); | ||
47 | |||
48 | /* EBI_OE, EBI_WE */ | ||
49 | s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0)); | ||
50 | |||
51 | /* CF_OE, CF_WE */ | ||
52 | s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2)); | ||
53 | |||
54 | /* CF_CD */ | ||
55 | s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); | ||
56 | s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE); | ||
57 | } | ||
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c deleted file mode 100644 index ada377f0c206..000000000000 --- a/arch/arm/mach-s5pc100/setup-keypad.c +++ /dev/null | |||
@@ -1,23 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/setup-keypad.c | ||
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * GPIO configuration for S5PC100 KeyPad device | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify | ||
9 | * it under the terms of the GNU General Public License version 2 as | ||
10 | * published by the Free Software Foundation. | ||
11 | */ | ||
12 | |||
13 | #include <linux/gpio.h> | ||
14 | #include <plat/gpio-cfg.h> | ||
15 | |||
16 | void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) | ||
17 | { | ||
18 | /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ | ||
19 | s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3)); | ||
20 | |||
21 | /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ | ||
22 | s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3)); | ||
23 | } | ||
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c deleted file mode 100644 index 6010c0310cb5..000000000000 --- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c +++ /dev/null | |||
@@ -1,70 +0,0 @@ | |||
1 | /* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c | ||
2 | * | ||
3 | * Copyright 2009 Samsung Eletronics | ||
4 | * | ||
5 | * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) | ||
6 | * | ||
7 | * This program is free software; you can redistribute it and/or modify | ||
8 | * it under the terms of the GNU General Public License version 2 as | ||
9 | * published by the Free Software Foundation. | ||
10 | */ | ||
11 | |||
12 | #include <linux/kernel.h> | ||
13 | #include <linux/types.h> | ||
14 | #include <linux/interrupt.h> | ||
15 | #include <linux/platform_device.h> | ||
16 | #include <linux/io.h> | ||
17 | #include <linux/gpio.h> | ||
18 | #include <linux/mmc/host.h> | ||
19 | #include <linux/mmc/card.h> | ||
20 | |||
21 | #include <plat/gpio-cfg.h> | ||
22 | #include <plat/sdhci.h> | ||
23 | |||
24 | void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | ||
25 | { | ||
26 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; | ||
27 | unsigned int num; | ||
28 | |||
29 | num = width; | ||
30 | /* In case of 8 width, we should decrease the 2 */ | ||
31 | if (width == 8) | ||
32 | num = width - 2; | ||
33 | |||
34 | /* Set all the necessary GPG0/GPG1 pins to special-function 0 */ | ||
35 | s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2)); | ||
36 | |||
37 | if (width == 8) | ||
38 | s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2)); | ||
39 | |||
40 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | ||
41 | s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); | ||
42 | s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2)); | ||
43 | } | ||
44 | } | ||
45 | |||
46 | void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) | ||
47 | { | ||
48 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; | ||
49 | |||
50 | /* Set all the necessary GPG2 pins to special-function 2 */ | ||
51 | s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2)); | ||
52 | |||
53 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | ||
54 | s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); | ||
55 | s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2)); | ||
56 | } | ||
57 | } | ||
58 | |||
59 | void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) | ||
60 | { | ||
61 | struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; | ||
62 | |||
63 | /* Set all the necessary GPG3 pins to special-function 2 */ | ||
64 | s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2)); | ||
65 | |||
66 | if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { | ||
67 | s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); | ||
68 | s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2)); | ||
69 | } | ||
70 | } | ||
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c deleted file mode 100644 index 183567961de1..000000000000 --- a/arch/arm/mach-s5pc100/setup-spi.c +++ /dev/null | |||
@@ -1,41 +0,0 @@ | |||
1 | /* linux/arch/arm/mach-s5pc100/setup-spi.c | ||
2 | * | ||
3 | * Copyright (C) 2011 Samsung Electronics Ltd. | ||
4 | * http://www.samsung.com/ | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify | ||
7 | * it under the terms of the GNU General Public License version 2 as | ||
8 | * published by the Free Software Foundation. | ||
9 | */ | ||
10 | |||
11 | #include <linux/gpio.h> | ||
12 | #include <plat/gpio-cfg.h> | ||
13 | |||
14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | ||
15 | int s3c64xx_spi0_cfg_gpio(void) | ||
16 | { | ||
17 | s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, | ||
18 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
19 | return 0; | ||
20 | } | ||
21 | #endif | ||
22 | |||
23 | #ifdef CONFIG_S3C64XX_DEV_SPI1 | ||
24 | int s3c64xx_spi1_cfg_gpio(void) | ||
25 | { | ||
26 | s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, | ||
27 | S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); | ||
28 | return 0; | ||
29 | } | ||
30 | #endif | ||
31 | |||
32 | #ifdef CONFIG_S3C64XX_DEV_SPI2 | ||
33 | int s3c64xx_spi2_cfg_gpio(void) | ||
34 | { | ||
35 | s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); | ||
36 | s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); | ||
37 | s3c_gpio_cfgall_range(S5PC100_GPB(2), 2, | ||
38 | S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); | ||
39 | return 0; | ||
40 | } | ||
41 | #endif | ||
diff --git a/arch/arm/mach-s5pv210/dev-audio.c b/arch/arm/mach-s5pv210/dev-audio.c index 2d67361ef431..90356ad10c54 100644 --- a/arch/arm/mach-s5pv210/dev-audio.c +++ b/arch/arm/mach-s5pv210/dev-audio.c | |||
@@ -10,7 +10,6 @@ | |||
10 | 10 | ||
11 | #include <linux/platform_device.h> | 11 | #include <linux/platform_device.h> |
12 | #include <linux/dma-mapping.h> | 12 | #include <linux/dma-mapping.h> |
13 | #include <linux/gpio.h> | ||
14 | 13 | ||
15 | #include <plat/gpio-cfg.h> | 14 | #include <plat/gpio-cfg.h> |
16 | #include <linux/platform_data/asoc-s3c.h> | 15 | #include <linux/platform_data/asoc-s3c.h> |
@@ -18,6 +17,7 @@ | |||
18 | #include <mach/map.h> | 17 | #include <mach/map.h> |
19 | #include <mach/dma.h> | 18 | #include <mach/dma.h> |
20 | #include <mach/irqs.h> | 19 | #include <mach/irqs.h> |
20 | #include <mach/gpio-samsung.h> | ||
21 | 21 | ||
22 | #define S5PV210_AUDSS_INT_MEM (0xC0000000) | 22 | #define S5PV210_AUDSS_INT_MEM (0xC0000000) |
23 | 23 | ||
diff --git a/arch/arm/mach-s5pv210/include/mach/gpio.h b/arch/arm/mach-s5pv210/include/mach/gpio-samsung.h index 6c8b903c02e4..e193b891e7b2 100644 --- a/arch/arm/mach-s5pv210/include/mach/gpio.h +++ b/arch/arm/mach-s5pv210/include/mach/gpio-samsung.h | |||
@@ -1,5 +1,4 @@ | |||
1 | /* linux/arch/arm/mach-s5pv210/include/mach/gpio.h | 1 | /* |
2 | * | ||
3 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. | 2 | * Copyright (c) 2010 Samsung Electronics Co., Ltd. |
4 | * http://www.samsung.com/ | 3 | * http://www.samsung.com/ |
5 | * | 4 | * |
@@ -133,8 +132,4 @@ enum s5p_gpio_number { | |||
133 | #define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1) | 132 | #define S5PV210_GPIO_END (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + 1) |
134 | #define S3C_GPIO_END S5PV210_GPIO_END | 133 | #define S3C_GPIO_END S5PV210_GPIO_END |
135 | 134 | ||
136 | /* define the number of gpios we need to the one after the MP05() range */ | ||
137 | #define ARCH_NR_GPIOS (S5PV210_MP05(S5PV210_GPIO_MP05_NR) + \ | ||
138 | CONFIG_SAMSUNG_GPIO_EXTRA + 1) | ||
139 | |||
140 | #endif /* __ASM_ARCH_GPIO_H */ | 135 | #endif /* __ASM_ARCH_GPIO_H */ |
diff --git a/arch/arm/mach-s5pv210/mach-aquila.c b/arch/arm/mach-s5pv210/mach-aquila.c index cc37edacda26..4262d8ff1988 100644 --- a/arch/arm/mach-s5pv210/mach-aquila.c +++ b/arch/arm/mach-s5pv210/mach-aquila.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include <video/samsung_fimd.h> | 31 | #include <video/samsung_fimd.h> |
32 | #include <mach/map.h> | 32 | #include <mach/map.h> |
33 | #include <mach/regs-clock.h> | 33 | #include <mach/regs-clock.h> |
34 | #include <mach/gpio-samsung.h> | ||
34 | 35 | ||
35 | #include <plat/gpio-cfg.h> | 36 | #include <plat/gpio-cfg.h> |
36 | #include <plat/devs.h> | 37 | #include <plat/devs.h> |
diff --git a/arch/arm/mach-s5pv210/mach-goni.c b/arch/arm/mach-s5pv210/mach-goni.c index c1ce921c4088..096a8173a1d9 100644 --- a/arch/arm/mach-s5pv210/mach-goni.c +++ b/arch/arm/mach-s5pv210/mach-goni.c | |||
@@ -38,6 +38,7 @@ | |||
38 | #include <video/samsung_fimd.h> | 38 | #include <video/samsung_fimd.h> |
39 | #include <mach/map.h> | 39 | #include <mach/map.h> |
40 | #include <mach/regs-clock.h> | 40 | #include <mach/regs-clock.h> |
41 | #include <mach/gpio-samsung.h> | ||
41 | 42 | ||
42 | #include <plat/gpio-cfg.h> | 43 | #include <plat/gpio-cfg.h> |
43 | #include <plat/devs.h> | 44 | #include <plat/devs.h> |
diff --git a/arch/arm/mach-s5pv210/mach-smdkv210.c b/arch/arm/mach-s5pv210/mach-smdkv210.c index 2a6655fb63e7..a146089c9ee6 100644 --- a/arch/arm/mach-s5pv210/mach-smdkv210.c +++ b/arch/arm/mach-s5pv210/mach-smdkv210.c | |||
@@ -32,6 +32,7 @@ | |||
32 | 32 | ||
33 | #include <mach/map.h> | 33 | #include <mach/map.h> |
34 | #include <mach/regs-clock.h> | 34 | #include <mach/regs-clock.h> |
35 | #include <mach/gpio-samsung.h> | ||
35 | 36 | ||
36 | #include <plat/regs-srom.h> | 37 | #include <plat/regs-srom.h> |
37 | #include <plat/gpio-cfg.h> | 38 | #include <plat/gpio-cfg.h> |
diff --git a/arch/arm/mach-s5pv210/setup-fb-24bpp.c b/arch/arm/mach-s5pv210/setup-fb-24bpp.c index 55103c8220b3..815e329f70c4 100644 --- a/arch/arm/mach-s5pv210/setup-fb-24bpp.c +++ b/arch/arm/mach-s5pv210/setup-fb-24bpp.c | |||
@@ -13,12 +13,12 @@ | |||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/types.h> | 14 | #include <linux/types.h> |
15 | #include <linux/fb.h> | 15 | #include <linux/fb.h> |
16 | #include <linux/gpio.h> | ||
17 | 16 | ||
18 | #include <mach/map.h> | 17 | #include <mach/map.h> |
19 | #include <plat/fb.h> | 18 | #include <plat/fb.h> |
20 | #include <mach/regs-clock.h> | 19 | #include <mach/regs-clock.h> |
21 | #include <plat/gpio-cfg.h> | 20 | #include <plat/gpio-cfg.h> |
21 | #include <mach/gpio-samsung.h> | ||
22 | 22 | ||
23 | static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr) | 23 | static void s5pv210_fb_cfg_gpios(unsigned int base, unsigned int nr) |
24 | { | 24 | { |
diff --git a/arch/arm/mach-s5pv210/setup-fimc.c b/arch/arm/mach-s5pv210/setup-fimc.c index 54cc5b11be0b..36945ec437f8 100644 --- a/arch/arm/mach-s5pv210/setup-fimc.c +++ b/arch/arm/mach-s5pv210/setup-fimc.c | |||
@@ -8,9 +8,10 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | 11 | #include <linux/kernel.h> |
12 | #include <plat/gpio-cfg.h> | 12 | #include <plat/gpio-cfg.h> |
13 | #include <plat/camport.h> | 13 | #include <plat/camport.h> |
14 | #include <mach/gpio-samsung.h> | ||
14 | 15 | ||
15 | int s5pv210_fimc_setup_gpio(enum s5p_camport_id id) | 16 | int s5pv210_fimc_setup_gpio(enum s5p_camport_id id) |
16 | { | 17 | { |
diff --git a/arch/arm/mach-s5pv210/setup-i2c0.c b/arch/arm/mach-s5pv210/setup-i2c0.c index 4a15849766c0..b0f2b69ac743 100644 --- a/arch/arm/mach-s5pv210/setup-i2c0.c +++ b/arch/arm/mach-s5pv210/setup-i2c0.c | |||
@@ -14,12 +14,12 @@ | |||
14 | 14 | ||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/gpio.h> | ||
18 | 17 | ||
19 | struct platform_device; /* don't need the contents */ | 18 | struct platform_device; /* don't need the contents */ |
20 | 19 | ||
21 | #include <linux/platform_data/i2c-s3c2410.h> | 20 | #include <linux/platform_data/i2c-s3c2410.h> |
22 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
22 | #include <mach/gpio-samsung.h> | ||
23 | 23 | ||
24 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) | 24 | void s3c_i2c0_cfg_gpio(struct platform_device *dev) |
25 | { | 25 | { |
diff --git a/arch/arm/mach-s5pv210/setup-i2c1.c b/arch/arm/mach-s5pv210/setup-i2c1.c index 4777f6b97a92..aac1da7b9071 100644 --- a/arch/arm/mach-s5pv210/setup-i2c1.c +++ b/arch/arm/mach-s5pv210/setup-i2c1.c | |||
@@ -14,12 +14,12 @@ | |||
14 | 14 | ||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/gpio.h> | ||
18 | 17 | ||
19 | struct platform_device; /* don't need the contents */ | 18 | struct platform_device; /* don't need the contents */ |
20 | 19 | ||
21 | #include <linux/platform_data/i2c-s3c2410.h> | 20 | #include <linux/platform_data/i2c-s3c2410.h> |
22 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
22 | #include <mach/gpio-samsung.h> | ||
23 | 23 | ||
24 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) | 24 | void s3c_i2c1_cfg_gpio(struct platform_device *dev) |
25 | { | 25 | { |
diff --git a/arch/arm/mach-s5pv210/setup-i2c2.c b/arch/arm/mach-s5pv210/setup-i2c2.c index bbce6c74b915..eff4503b903f 100644 --- a/arch/arm/mach-s5pv210/setup-i2c2.c +++ b/arch/arm/mach-s5pv210/setup-i2c2.c | |||
@@ -14,12 +14,12 @@ | |||
14 | 14 | ||
15 | #include <linux/kernel.h> | 15 | #include <linux/kernel.h> |
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | #include <linux/gpio.h> | ||
18 | 17 | ||
19 | struct platform_device; /* don't need the contents */ | 18 | struct platform_device; /* don't need the contents */ |
20 | 19 | ||
21 | #include <linux/platform_data/i2c-s3c2410.h> | 20 | #include <linux/platform_data/i2c-s3c2410.h> |
22 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
22 | #include <mach/gpio-samsung.h> | ||
23 | 23 | ||
24 | void s3c_i2c2_cfg_gpio(struct platform_device *dev) | 24 | void s3c_i2c2_cfg_gpio(struct platform_device *dev) |
25 | { | 25 | { |
diff --git a/arch/arm/mach-s5pv210/setup-ide.c b/arch/arm/mach-s5pv210/setup-ide.c index ea123d546bd2..5b6042d97892 100644 --- a/arch/arm/mach-s5pv210/setup-ide.c +++ b/arch/arm/mach-s5pv210/setup-ide.c | |||
@@ -11,9 +11,9 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | #include <linux/gpio.h> | ||
15 | 14 | ||
16 | #include <plat/gpio-cfg.h> | 15 | #include <plat/gpio-cfg.h> |
16 | #include <mach/gpio-samsung.h> | ||
17 | 17 | ||
18 | static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr) | 18 | static void s5pv210_ide_cfg_gpios(unsigned int base, unsigned int nr) |
19 | { | 19 | { |
diff --git a/arch/arm/mach-s5pv210/setup-keypad.c b/arch/arm/mach-s5pv210/setup-keypad.c index c56420a52f48..faf6178f3a1b 100644 --- a/arch/arm/mach-s5pv210/setup-keypad.c +++ b/arch/arm/mach-s5pv210/setup-keypad.c | |||
@@ -11,8 +11,8 @@ | |||
11 | * | 11 | * |
12 | */ | 12 | */ |
13 | 13 | ||
14 | #include <linux/gpio.h> | ||
15 | #include <plat/gpio-cfg.h> | 14 | #include <plat/gpio-cfg.h> |
15 | #include <mach/gpio-samsung.h> | ||
16 | 16 | ||
17 | void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) | 17 | void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) |
18 | { | 18 | { |
diff --git a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c index 0512ada00522..0dd055b47579 100644 --- a/arch/arm/mach-s5pv210/setup-sdhci-gpio.c +++ b/arch/arm/mach-s5pv210/setup-sdhci-gpio.c | |||
@@ -15,12 +15,12 @@ | |||
15 | #include <linux/interrupt.h> | 15 | #include <linux/interrupt.h> |
16 | #include <linux/platform_device.h> | 16 | #include <linux/platform_device.h> |
17 | #include <linux/io.h> | 17 | #include <linux/io.h> |
18 | #include <linux/gpio.h> | ||
19 | #include <linux/mmc/host.h> | 18 | #include <linux/mmc/host.h> |
20 | #include <linux/mmc/card.h> | 19 | #include <linux/mmc/card.h> |
21 | 20 | ||
22 | #include <plat/gpio-cfg.h> | 21 | #include <plat/gpio-cfg.h> |
23 | #include <plat/sdhci.h> | 22 | #include <plat/sdhci.h> |
23 | #include <mach/gpio-samsung.h> | ||
24 | 24 | ||
25 | void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) | 25 | void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) |
26 | { | 26 | { |
diff --git a/arch/arm/mach-s5pv210/setup-spi.c b/arch/arm/mach-s5pv210/setup-spi.c index 81aecc162f82..e1faf8ea4502 100644 --- a/arch/arm/mach-s5pv210/setup-spi.c +++ b/arch/arm/mach-s5pv210/setup-spi.c | |||
@@ -8,8 +8,8 @@ | |||
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/gpio.h> | ||
12 | #include <plat/gpio-cfg.h> | 11 | #include <plat/gpio-cfg.h> |
12 | #include <mach/gpio-samsung.h> | ||
13 | 13 | ||
14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 | 14 | #ifdef CONFIG_S3C64XX_DEV_SPI0 |
15 | int s3c64xx_spi0_cfg_gpio(void) | 15 | int s3c64xx_spi0_cfg_gpio(void) |
diff --git a/arch/arm/mach-shmobile/board-ape6evm-reference.c b/arch/arm/mach-shmobile/board-ape6evm-reference.c index 3276afcf3cc9..2f7723e5fe91 100644 --- a/arch/arm/mach-shmobile/board-ape6evm-reference.c +++ b/arch/arm/mach-shmobile/board-ape6evm-reference.c | |||
@@ -24,11 +24,13 @@ | |||
24 | #include <linux/pinctrl/machine.h> | 24 | #include <linux/pinctrl/machine.h> |
25 | #include <linux/platform_device.h> | 25 | #include <linux/platform_device.h> |
26 | #include <linux/sh_clk.h> | 26 | #include <linux/sh_clk.h> |
27 | #include <mach/common.h> | 27 | |
28 | #include <mach/r8a73a4.h> | ||
29 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
30 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
31 | 30 | ||
31 | #include "common.h" | ||
32 | #include "r8a73a4.h" | ||
33 | |||
32 | static void __init ape6evm_add_standard_devices(void) | 34 | static void __init ape6evm_add_standard_devices(void) |
33 | { | 35 | { |
34 | 36 | ||
diff --git a/arch/arm/mach-shmobile/board-ape6evm.c b/arch/arm/mach-shmobile/board-ape6evm.c index 7ab99a4972a0..1585b8830b13 100644 --- a/arch/arm/mach-shmobile/board-ape6evm.c +++ b/arch/arm/mach-shmobile/board-ape6evm.c | |||
@@ -33,12 +33,14 @@ | |||
33 | #include <linux/regulator/machine.h> | 33 | #include <linux/regulator/machine.h> |
34 | #include <linux/sh_clk.h> | 34 | #include <linux/sh_clk.h> |
35 | #include <linux/smsc911x.h> | 35 | #include <linux/smsc911x.h> |
36 | #include <mach/common.h> | 36 | |
37 | #include <mach/irqs.h> | ||
38 | #include <mach/r8a73a4.h> | ||
39 | #include <asm/mach-types.h> | 37 | #include <asm/mach-types.h> |
40 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
41 | 39 | ||
40 | #include "common.h" | ||
41 | #include "irqs.h" | ||
42 | #include "r8a73a4.h" | ||
43 | |||
42 | /* LEDS */ | 44 | /* LEDS */ |
43 | static struct gpio_led ape6evm_leds[] = { | 45 | static struct gpio_led ape6evm_leds[] = { |
44 | { | 46 | { |
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c index f660fbb96e0b..208576667b22 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva-reference.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva-reference.c | |||
@@ -24,11 +24,13 @@ | |||
24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
25 | #include <linux/gpio.h> | 25 | #include <linux/gpio.h> |
26 | #include <linux/io.h> | 26 | #include <linux/io.h> |
27 | #include <mach/common.h> | 27 | |
28 | #include <mach/r8a7740.h> | ||
29 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
30 | #include <asm/hardware/cache-l2x0.h> | 29 | #include <asm/hardware/cache-l2x0.h> |
31 | 30 | ||
31 | #include "common.h" | ||
32 | #include "r8a7740.h" | ||
33 | |||
32 | /* | 34 | /* |
33 | * CON1 Camera Module | 35 | * CON1 Camera Module |
34 | * CON2 Extension Bus | 36 | * CON2 Extension Bus |
diff --git a/arch/arm/mach-shmobile/board-armadillo800eva.c b/arch/arm/mach-shmobile/board-armadillo800eva.c index 689c121157ec..42b6afaa69af 100644 --- a/arch/arm/mach-shmobile/board-armadillo800eva.c +++ b/arch/arm/mach-shmobile/board-armadillo800eva.c | |||
@@ -45,9 +45,7 @@ | |||
45 | #include <linux/mmc/sh_mobile_sdhi.h> | 45 | #include <linux/mmc/sh_mobile_sdhi.h> |
46 | #include <linux/i2c-gpio.h> | 46 | #include <linux/i2c-gpio.h> |
47 | #include <linux/reboot.h> | 47 | #include <linux/reboot.h> |
48 | #include <mach/common.h> | 48 | |
49 | #include <mach/irqs.h> | ||
50 | #include <mach/r8a7740.h> | ||
51 | #include <media/mt9t112.h> | 49 | #include <media/mt9t112.h> |
52 | #include <media/sh_mobile_ceu.h> | 50 | #include <media/sh_mobile_ceu.h> |
53 | #include <media/soc_camera.h> | 51 | #include <media/soc_camera.h> |
@@ -62,6 +60,10 @@ | |||
62 | #include <sound/sh_fsi.h> | 60 | #include <sound/sh_fsi.h> |
63 | #include <sound/simple_card.h> | 61 | #include <sound/simple_card.h> |
64 | 62 | ||
63 | #include "common.h" | ||
64 | #include "irqs.h" | ||
65 | #include "pm-rmobile.h" | ||
66 | #include "r8a7740.h" | ||
65 | #include "sh-gpio.h" | 67 | #include "sh-gpio.h" |
66 | 68 | ||
67 | /* | 69 | /* |
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c index 027373f8de82..ba840cd333b9 100644 --- a/arch/arm/mach-shmobile/board-bockw-reference.c +++ b/arch/arm/mach-shmobile/board-bockw-reference.c | |||
@@ -19,10 +19,12 @@ | |||
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/of_platform.h> | 21 | #include <linux/of_platform.h> |
22 | #include <mach/common.h> | 22 | |
23 | #include <mach/r8a7778.h> | ||
24 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
25 | 24 | ||
25 | #include "common.h" | ||
26 | #include "r8a7778.h" | ||
27 | |||
26 | /* | 28 | /* |
27 | * see board-bock.c for checking detail of dip-switch | 29 | * see board-bock.c for checking detail of dip-switch |
28 | */ | 30 | */ |
diff --git a/arch/arm/mach-shmobile/board-bockw.c b/arch/arm/mach-shmobile/board-bockw.c index 3ec82a4c35c5..8a83eb39d3f1 100644 --- a/arch/arm/mach-shmobile/board-bockw.c +++ b/arch/arm/mach-shmobile/board-bockw.c | |||
@@ -34,14 +34,16 @@ | |||
34 | #include <linux/spi/spi.h> | 34 | #include <linux/spi/spi.h> |
35 | #include <linux/spi/flash.h> | 35 | #include <linux/spi/flash.h> |
36 | #include <linux/usb/renesas_usbhs.h> | 36 | #include <linux/usb/renesas_usbhs.h> |
37 | |||
37 | #include <media/soc_camera.h> | 38 | #include <media/soc_camera.h> |
38 | #include <mach/common.h> | ||
39 | #include <mach/irqs.h> | ||
40 | #include <mach/r8a7778.h> | ||
41 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
42 | #include <sound/rcar_snd.h> | 40 | #include <sound/rcar_snd.h> |
43 | #include <sound/simple_card.h> | 41 | #include <sound/simple_card.h> |
44 | 42 | ||
43 | #include "common.h" | ||
44 | #include "irqs.h" | ||
45 | #include "r8a7778.h" | ||
46 | |||
45 | #define FPGA 0x18200000 | 47 | #define FPGA 0x18200000 |
46 | #define IRQ0MR 0x30 | 48 | #define IRQ0MR 0x30 |
47 | #define COMCTLR 0x101c | 49 | #define COMCTLR 0x101c |
diff --git a/arch/arm/mach-shmobile/board-genmai-reference.c b/arch/arm/mach-shmobile/board-genmai-reference.c index 2ff6ad6e608e..e5448f7b868a 100644 --- a/arch/arm/mach-shmobile/board-genmai-reference.c +++ b/arch/arm/mach-shmobile/board-genmai-reference.c | |||
@@ -20,12 +20,14 @@ | |||
20 | 20 | ||
21 | #include <linux/kernel.h> | 21 | #include <linux/kernel.h> |
22 | #include <linux/of_platform.h> | 22 | #include <linux/of_platform.h> |
23 | #include <mach/clock.h> | 23 | |
24 | #include <mach/common.h> | ||
25 | #include <mach/r7s72100.h> | ||
26 | #include <asm/mach-types.h> | 24 | #include <asm/mach-types.h> |
27 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
28 | 26 | ||
27 | #include "clock.h" | ||
28 | #include "common.h" | ||
29 | #include "r7s72100.h" | ||
30 | |||
29 | /* | 31 | /* |
30 | * This is a really crude hack to provide clkdev support to platform | 32 | * This is a really crude hack to provide clkdev support to platform |
31 | * devices until they get moved to DT. | 33 | * devices until they get moved to DT. |
@@ -47,7 +49,7 @@ static const char * const genmai_boards_compat_dt[] __initconst = { | |||
47 | }; | 49 | }; |
48 | 50 | ||
49 | DT_MACHINE_START(GENMAI_DT, "genmai") | 51 | DT_MACHINE_START(GENMAI_DT, "genmai") |
50 | .init_early = r7s72100_init_early, | 52 | .init_early = shmobile_init_delay, |
51 | .init_machine = genmai_add_standard_devices, | 53 | .init_machine = genmai_add_standard_devices, |
52 | .dt_compat = genmai_boards_compat_dt, | 54 | .dt_compat = genmai_boards_compat_dt, |
53 | MACHINE_END | 55 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/board-genmai.c b/arch/arm/mach-shmobile/board-genmai.c index 37184ff8c5c2..7bf2d8057535 100644 --- a/arch/arm/mach-shmobile/board-genmai.c +++ b/arch/arm/mach-shmobile/board-genmai.c | |||
@@ -25,12 +25,14 @@ | |||
25 | #include <linux/sh_eth.h> | 25 | #include <linux/sh_eth.h> |
26 | #include <linux/spi/rspi.h> | 26 | #include <linux/spi/rspi.h> |
27 | #include <linux/spi/spi.h> | 27 | #include <linux/spi/spi.h> |
28 | #include <mach/common.h> | 28 | |
29 | #include <mach/irqs.h> | ||
30 | #include <mach/r7s72100.h> | ||
31 | #include <asm/mach-types.h> | 29 | #include <asm/mach-types.h> |
32 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
33 | 31 | ||
32 | #include "common.h" | ||
33 | #include "irqs.h" | ||
34 | #include "r7s72100.h" | ||
35 | |||
34 | /* Ether */ | 36 | /* Ether */ |
35 | static const struct sh_eth_plat_data ether_pdata __initconst = { | 37 | static const struct sh_eth_plat_data ether_pdata __initconst = { |
36 | .phy = 0x00, /* PD60610 */ | 38 | .phy = 0x00, /* PD60610 */ |
@@ -153,7 +155,7 @@ static const char * const genmai_boards_compat_dt[] __initconst = { | |||
153 | }; | 155 | }; |
154 | 156 | ||
155 | DT_MACHINE_START(GENMAI_DT, "genmai") | 157 | DT_MACHINE_START(GENMAI_DT, "genmai") |
156 | .init_early = r7s72100_init_early, | 158 | .init_early = shmobile_init_delay, |
157 | .init_machine = genmai_add_standard_devices, | 159 | .init_machine = genmai_add_standard_devices, |
158 | .dt_compat = genmai_boards_compat_dt, | 160 | .dt_compat = genmai_boards_compat_dt, |
159 | MACHINE_END | 161 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/board-koelsch-reference.c b/arch/arm/mach-shmobile/board-koelsch-reference.c index d322a162b4b0..1d3f67d4ccd6 100644 --- a/arch/arm/mach-shmobile/board-koelsch-reference.c +++ b/arch/arm/mach-shmobile/board-koelsch-reference.c | |||
@@ -23,12 +23,12 @@ | |||
23 | #include <linux/kernel.h> | 23 | #include <linux/kernel.h> |
24 | #include <linux/of_platform.h> | 24 | #include <linux/of_platform.h> |
25 | #include <linux/platform_data/rcar-du.h> | 25 | #include <linux/platform_data/rcar-du.h> |
26 | #include <mach/clock.h> | ||
27 | #include <mach/common.h> | ||
28 | #include <mach/irqs.h> | ||
29 | #include <mach/rcar-gen2.h> | ||
30 | #include <mach/r8a7791.h> | 26 | #include <mach/r8a7791.h> |
31 | #include <asm/mach/arch.h> | 27 | #include <asm/mach/arch.h> |
28 | #include "clock.h" | ||
29 | #include "common.h" | ||
30 | #include "irqs.h" | ||
31 | #include "rcar-gen2.h" | ||
32 | 32 | ||
33 | /* DU */ | 33 | /* DU */ |
34 | static struct rcar_du_encoder_data koelsch_du_encoders[] = { | 34 | static struct rcar_du_encoder_data koelsch_du_encoders[] = { |
diff --git a/arch/arm/mach-shmobile/board-koelsch.c b/arch/arm/mach-shmobile/board-koelsch.c index d3aa6ae05eeb..c932f2ca85b1 100644 --- a/arch/arm/mach-shmobile/board-koelsch.c +++ b/arch/arm/mach-shmobile/board-koelsch.c | |||
@@ -45,12 +45,12 @@ | |||
45 | #include <linux/spi/flash.h> | 45 | #include <linux/spi/flash.h> |
46 | #include <linux/spi/rspi.h> | 46 | #include <linux/spi/rspi.h> |
47 | #include <linux/spi/spi.h> | 47 | #include <linux/spi/spi.h> |
48 | #include <mach/common.h> | ||
49 | #include <mach/irqs.h> | ||
50 | #include <mach/r8a7791.h> | 48 | #include <mach/r8a7791.h> |
51 | #include <mach/rcar-gen2.h> | ||
52 | #include <asm/mach-types.h> | 49 | #include <asm/mach-types.h> |
53 | #include <asm/mach/arch.h> | 50 | #include <asm/mach/arch.h> |
51 | #include "common.h" | ||
52 | #include "irqs.h" | ||
53 | #include "rcar-gen2.h" | ||
54 | 54 | ||
55 | /* DU */ | 55 | /* DU */ |
56 | static struct rcar_du_encoder_data koelsch_du_encoders[] = { | 56 | static struct rcar_du_encoder_data koelsch_du_encoders[] = { |
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c index a735a1d80c28..5d2621f202d1 100644 --- a/arch/arm/mach-shmobile/board-kzm9g-reference.c +++ b/arch/arm/mach-shmobile/board-kzm9g-reference.c | |||
@@ -25,12 +25,14 @@ | |||
25 | #include <linux/irq.h> | 25 | #include <linux/irq.h> |
26 | #include <linux/input.h> | 26 | #include <linux/input.h> |
27 | #include <linux/of_platform.h> | 27 | #include <linux/of_platform.h> |
28 | #include <mach/sh73a0.h> | 28 | |
29 | #include <mach/common.h> | ||
30 | #include <asm/hardware/cache-l2x0.h> | 29 | #include <asm/hardware/cache-l2x0.h> |
31 | #include <asm/mach-types.h> | 30 | #include <asm/mach-types.h> |
32 | #include <asm/mach/arch.h> | 31 | #include <asm/mach/arch.h> |
33 | 32 | ||
33 | #include "common.h" | ||
34 | #include "sh73a0.h" | ||
35 | |||
34 | static void __init kzm_init(void) | 36 | static void __init kzm_init(void) |
35 | { | 37 | { |
36 | sh73a0_add_standard_devices_dt(); | 38 | sh73a0_add_standard_devices_dt(); |
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c index 01e0d1386db7..f8bc7f8f86ad 100644 --- a/arch/arm/mach-shmobile/board-kzm9g.c +++ b/arch/arm/mach-shmobile/board-kzm9g.c | |||
@@ -41,16 +41,18 @@ | |||
41 | #include <linux/usb/r8a66597.h> | 41 | #include <linux/usb/r8a66597.h> |
42 | #include <linux/usb/renesas_usbhs.h> | 42 | #include <linux/usb/renesas_usbhs.h> |
43 | #include <linux/videodev2.h> | 43 | #include <linux/videodev2.h> |
44 | |||
44 | #include <sound/sh_fsi.h> | 45 | #include <sound/sh_fsi.h> |
45 | #include <sound/simple_card.h> | 46 | #include <sound/simple_card.h> |
46 | #include <mach/irqs.h> | ||
47 | #include <mach/sh73a0.h> | ||
48 | #include <mach/common.h> | ||
49 | #include <asm/hardware/cache-l2x0.h> | 47 | #include <asm/hardware/cache-l2x0.h> |
50 | #include <asm/mach-types.h> | 48 | #include <asm/mach-types.h> |
51 | #include <asm/mach/arch.h> | 49 | #include <asm/mach/arch.h> |
52 | #include <video/sh_mobile_lcdc.h> | 50 | #include <video/sh_mobile_lcdc.h> |
53 | 51 | ||
52 | #include "common.h" | ||
53 | #include "irqs.h" | ||
54 | #include "sh73a0.h" | ||
55 | |||
54 | /* | 56 | /* |
55 | * external GPIO | 57 | * external GPIO |
56 | */ | 58 | */ |
diff --git a/arch/arm/mach-shmobile/board-lager-reference.c b/arch/arm/mach-shmobile/board-lager-reference.c index 749832e3f33c..8dcff51a8f45 100644 --- a/arch/arm/mach-shmobile/board-lager-reference.c +++ b/arch/arm/mach-shmobile/board-lager-reference.c | |||
@@ -22,13 +22,15 @@ | |||
22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
24 | #include <linux/platform_data/rcar-du.h> | 24 | #include <linux/platform_data/rcar-du.h> |
25 | #include <mach/clock.h> | 25 | |
26 | #include <mach/common.h> | ||
27 | #include <mach/irqs.h> | ||
28 | #include <mach/rcar-gen2.h> | ||
29 | #include <mach/r8a7790.h> | ||
30 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
31 | 27 | ||
28 | #include "clock.h" | ||
29 | #include "common.h" | ||
30 | #include "irqs.h" | ||
31 | #include "r8a7790.h" | ||
32 | #include "rcar-gen2.h" | ||
33 | |||
32 | /* DU */ | 34 | /* DU */ |
33 | static struct rcar_du_encoder_data lager_du_encoders[] = { | 35 | static struct rcar_du_encoder_data lager_du_encoders[] = { |
34 | { | 36 | { |
@@ -129,7 +131,7 @@ static const char *lager_boards_compat_dt[] __initdata = { | |||
129 | 131 | ||
130 | DT_MACHINE_START(LAGER_DT, "lager") | 132 | DT_MACHINE_START(LAGER_DT, "lager") |
131 | .smp = smp_ops(r8a7790_smp_ops), | 133 | .smp = smp_ops(r8a7790_smp_ops), |
132 | .init_early = r8a7790_init_early, | 134 | .init_early = shmobile_init_delay, |
133 | .init_time = rcar_gen2_timer_init, | 135 | .init_time = rcar_gen2_timer_init, |
134 | .init_machine = lager_add_standard_devices, | 136 | .init_machine = lager_add_standard_devices, |
135 | .init_late = shmobile_init_late, | 137 | .init_late = shmobile_init_late, |
diff --git a/arch/arm/mach-shmobile/board-lager.c b/arch/arm/mach-shmobile/board-lager.c index d18296164e89..18331ac375f1 100644 --- a/arch/arm/mach-shmobile/board-lager.c +++ b/arch/arm/mach-shmobile/board-lager.c | |||
@@ -31,6 +31,8 @@ | |||
31 | #include <linux/mmc/host.h> | 31 | #include <linux/mmc/host.h> |
32 | #include <linux/mmc/sh_mmcif.h> | 32 | #include <linux/mmc/sh_mmcif.h> |
33 | #include <linux/mmc/sh_mobile_sdhi.h> | 33 | #include <linux/mmc/sh_mobile_sdhi.h> |
34 | #include <linux/mtd/partitions.h> | ||
35 | #include <linux/mtd/mtd.h> | ||
34 | #include <linux/pinctrl/machine.h> | 36 | #include <linux/pinctrl/machine.h> |
35 | #include <linux/platform_data/camera-rcar.h> | 37 | #include <linux/platform_data/camera-rcar.h> |
36 | #include <linux/platform_data/gpio-rcar.h> | 38 | #include <linux/platform_data/gpio-rcar.h> |
@@ -43,22 +45,23 @@ | |||
43 | #include <linux/regulator/gpio-regulator.h> | 45 | #include <linux/regulator/gpio-regulator.h> |
44 | #include <linux/regulator/machine.h> | 46 | #include <linux/regulator/machine.h> |
45 | #include <linux/sh_eth.h> | 47 | #include <linux/sh_eth.h> |
48 | #include <linux/spi/flash.h> | ||
49 | #include <linux/spi/rspi.h> | ||
50 | #include <linux/spi/spi.h> | ||
46 | #include <linux/usb/phy.h> | 51 | #include <linux/usb/phy.h> |
47 | #include <linux/usb/renesas_usbhs.h> | 52 | #include <linux/usb/renesas_usbhs.h> |
48 | #include <mach/common.h> | 53 | |
49 | #include <mach/irqs.h> | ||
50 | #include <mach/r8a7790.h> | ||
51 | #include <media/soc_camera.h> | 54 | #include <media/soc_camera.h> |
52 | #include <asm/mach-types.h> | 55 | #include <asm/mach-types.h> |
53 | #include <asm/mach/arch.h> | 56 | #include <asm/mach/arch.h> |
54 | #include <linux/mtd/partitions.h> | ||
55 | #include <linux/mtd/mtd.h> | ||
56 | #include <linux/spi/flash.h> | ||
57 | #include <linux/spi/rspi.h> | ||
58 | #include <linux/spi/spi.h> | ||
59 | #include <sound/rcar_snd.h> | 57 | #include <sound/rcar_snd.h> |
60 | #include <sound/simple_card.h> | 58 | #include <sound/simple_card.h> |
61 | 59 | ||
60 | #include "common.h" | ||
61 | #include "irqs.h" | ||
62 | #include "r8a7790.h" | ||
63 | #include "rcar-gen2.h" | ||
64 | |||
62 | /* | 65 | /* |
63 | * SSI-AK4643 | 66 | * SSI-AK4643 |
64 | * | 67 | * |
@@ -880,7 +883,7 @@ static const char * const lager_boards_compat_dt[] __initconst = { | |||
880 | 883 | ||
881 | DT_MACHINE_START(LAGER_DT, "lager") | 884 | DT_MACHINE_START(LAGER_DT, "lager") |
882 | .smp = smp_ops(r8a7790_smp_ops), | 885 | .smp = smp_ops(r8a7790_smp_ops), |
883 | .init_early = r8a7790_init_early, | 886 | .init_early = shmobile_init_delay, |
884 | .init_time = rcar_gen2_timer_init, | 887 | .init_time = rcar_gen2_timer_init, |
885 | .init_machine = lager_init, | 888 | .init_machine = lager_init, |
886 | .init_late = shmobile_init_late, | 889 | .init_late = shmobile_init_late, |
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c index 112553f0f9bf..79f448e93abb 100644 --- a/arch/arm/mach-shmobile/board-mackerel.c +++ b/arch/arm/mach-shmobile/board-mackerel.c | |||
@@ -47,10 +47,11 @@ | |||
47 | #include <linux/regulator/fixed.h> | 47 | #include <linux/regulator/fixed.h> |
48 | #include <linux/regulator/machine.h> | 48 | #include <linux/regulator/machine.h> |
49 | #include <linux/smsc911x.h> | 49 | #include <linux/smsc911x.h> |
50 | #include <linux/sh_intc.h> | 50 | #include <linux/sh_clk.h> |
51 | #include <linux/tca6416_keypad.h> | 51 | #include <linux/tca6416_keypad.h> |
52 | #include <linux/usb/renesas_usbhs.h> | 52 | #include <linux/usb/renesas_usbhs.h> |
53 | #include <linux/dma-mapping.h> | 53 | #include <linux/dma-mapping.h> |
54 | |||
54 | #include <video/sh_mobile_hdmi.h> | 55 | #include <video/sh_mobile_hdmi.h> |
55 | #include <video/sh_mobile_lcdc.h> | 56 | #include <video/sh_mobile_lcdc.h> |
56 | #include <media/sh_mobile_ceu.h> | 57 | #include <media/sh_mobile_ceu.h> |
@@ -58,15 +59,14 @@ | |||
58 | #include <media/soc_camera_platform.h> | 59 | #include <media/soc_camera_platform.h> |
59 | #include <sound/sh_fsi.h> | 60 | #include <sound/sh_fsi.h> |
60 | #include <sound/simple_card.h> | 61 | #include <sound/simple_card.h> |
61 | |||
62 | #include <mach/common.h> | ||
63 | #include <mach/irqs.h> | ||
64 | #include <mach/sh7372.h> | ||
65 | |||
66 | #include <asm/mach/arch.h> | 62 | #include <asm/mach/arch.h> |
67 | #include <asm/mach-types.h> | 63 | #include <asm/mach-types.h> |
68 | 64 | ||
65 | #include "common.h" | ||
66 | #include "irqs.h" | ||
67 | #include "pm-rmobile.h" | ||
69 | #include "sh-gpio.h" | 68 | #include "sh-gpio.h" |
69 | #include "sh7372.h" | ||
70 | 70 | ||
71 | /* | 71 | /* |
72 | * Address Interface BusWidth note | 72 | * Address Interface BusWidth note |
diff --git a/arch/arm/mach-shmobile/board-marzen-reference.c b/arch/arm/mach-shmobile/board-marzen-reference.c index 2773936bf7dc..94bd57203ff5 100644 --- a/arch/arm/mach-shmobile/board-marzen-reference.c +++ b/arch/arm/mach-shmobile/board-marzen-reference.c | |||
@@ -20,10 +20,10 @@ | |||
20 | */ | 20 | */ |
21 | 21 | ||
22 | #include <mach/r8a7779.h> | 22 | #include <mach/r8a7779.h> |
23 | #include <mach/common.h> | ||
24 | #include <mach/irqs.h> | ||
25 | #include <asm/irq.h> | 23 | #include <asm/irq.h> |
26 | #include <asm/mach/arch.h> | 24 | #include <asm/mach/arch.h> |
25 | #include "common.h" | ||
26 | #include "irqs.h" | ||
27 | 27 | ||
28 | static void __init marzen_init(void) | 28 | static void __init marzen_init(void) |
29 | { | 29 | { |
diff --git a/arch/arm/mach-shmobile/board-marzen.c b/arch/arm/mach-shmobile/board-marzen.c index 6ed324ce848f..d0b5b746fe05 100644 --- a/arch/arm/mach-shmobile/board-marzen.c +++ b/arch/arm/mach-shmobile/board-marzen.c | |||
@@ -43,11 +43,11 @@ | |||
43 | #include <linux/mfd/tmio.h> | 43 | #include <linux/mfd/tmio.h> |
44 | #include <media/soc_camera.h> | 44 | #include <media/soc_camera.h> |
45 | #include <mach/r8a7779.h> | 45 | #include <mach/r8a7779.h> |
46 | #include <mach/common.h> | ||
47 | #include <mach/irqs.h> | ||
48 | #include <asm/mach-types.h> | 46 | #include <asm/mach-types.h> |
49 | #include <asm/mach/arch.h> | 47 | #include <asm/mach/arch.h> |
50 | #include <asm/traps.h> | 48 | #include <asm/traps.h> |
49 | #include "common.h" | ||
50 | #include "irqs.h" | ||
51 | 51 | ||
52 | /* Fixed 3.3V regulator to be used by SDHI0 */ | 52 | /* Fixed 3.3V regulator to be used by SDHI0 */ |
53 | static struct regulator_consumer_supply fixed3v3_power_consumers[] = { | 53 | static struct regulator_consumer_supply fixed3v3_power_consumers[] = { |
diff --git a/arch/arm/mach-shmobile/clock-r7s72100.c b/arch/arm/mach-shmobile/clock-r7s72100.c index df187484de5d..3eb2ec401e0c 100644 --- a/arch/arm/mach-shmobile/clock-r7s72100.c +++ b/arch/arm/mach-shmobile/clock-r7s72100.c | |||
@@ -19,8 +19,9 @@ | |||
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/sh_clk.h> | 20 | #include <linux/sh_clk.h> |
21 | #include <linux/clkdev.h> | 21 | #include <linux/clkdev.h> |
22 | #include <mach/common.h> | 22 | |
23 | #include <mach/r7s72100.h> | 23 | #include "common.h" |
24 | #include "r7s72100.h" | ||
24 | 25 | ||
25 | /* Frequency Control Registers */ | 26 | /* Frequency Control Registers */ |
26 | #define FRQCR 0xfcfe0010 | 27 | #define FRQCR 0xfcfe0010 |
diff --git a/arch/arm/mach-shmobile/clock-r8a73a4.c b/arch/arm/mach-shmobile/clock-r8a73a4.c index b5bc22c6a858..0f431498229b 100644 --- a/arch/arm/mach-shmobile/clock-r8a73a4.c +++ b/arch/arm/mach-shmobile/clock-r8a73a4.c | |||
@@ -22,8 +22,8 @@ | |||
22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
23 | #include <linux/sh_clk.h> | 23 | #include <linux/sh_clk.h> |
24 | #include <linux/clkdev.h> | 24 | #include <linux/clkdev.h> |
25 | #include <mach/clock.h> | 25 | #include "common.h" |
26 | #include <mach/common.h> | 26 | #include "clock.h" |
27 | 27 | ||
28 | #define CPG_BASE 0xe6150000 | 28 | #define CPG_BASE 0xe6150000 |
29 | #define CPG_LEN 0x270 | 29 | #define CPG_LEN 0x270 |
diff --git a/arch/arm/mach-shmobile/clock-r8a7740.c b/arch/arm/mach-shmobile/clock-r8a7740.c index 50931e3c97c7..789091cfa37a 100644 --- a/arch/arm/mach-shmobile/clock-r8a7740.c +++ b/arch/arm/mach-shmobile/clock-r8a7740.c | |||
@@ -22,9 +22,10 @@ | |||
22 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/sh_clk.h> | 23 | #include <linux/sh_clk.h> |
24 | #include <linux/clkdev.h> | 24 | #include <linux/clkdev.h> |
25 | #include <mach/clock.h> | 25 | |
26 | #include <mach/common.h> | 26 | #include "clock.h" |
27 | #include <mach/r8a7740.h> | 27 | #include "common.h" |
28 | #include "r8a7740.h" | ||
28 | 29 | ||
29 | /* | 30 | /* |
30 | * | MDx | XTAL1/EXTAL1 | System | EXTALR | | 31 | * | MDx | XTAL1/EXTAL1 | System | EXTALR | |
diff --git a/arch/arm/mach-shmobile/clock-r8a7778.c b/arch/arm/mach-shmobile/clock-r8a7778.c index 13f8f3ab8840..16bbc94a1520 100644 --- a/arch/arm/mach-shmobile/clock-r8a7778.c +++ b/arch/arm/mach-shmobile/clock-r8a7778.c | |||
@@ -39,8 +39,8 @@ | |||
39 | #include <linux/io.h> | 39 | #include <linux/io.h> |
40 | #include <linux/sh_clk.h> | 40 | #include <linux/sh_clk.h> |
41 | #include <linux/clkdev.h> | 41 | #include <linux/clkdev.h> |
42 | #include <mach/clock.h> | 42 | #include "clock.h" |
43 | #include <mach/common.h> | 43 | #include "common.h" |
44 | 44 | ||
45 | #define MSTPCR0 IOMEM(0xffc80030) | 45 | #define MSTPCR0 IOMEM(0xffc80030) |
46 | #define MSTPCR1 IOMEM(0xffc80034) | 46 | #define MSTPCR1 IOMEM(0xffc80034) |
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c index a13298bd37a8..d81539a26dbd 100644 --- a/arch/arm/mach-shmobile/clock-r8a7779.c +++ b/arch/arm/mach-shmobile/clock-r8a7779.c | |||
@@ -23,8 +23,8 @@ | |||
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/sh_clk.h> | 24 | #include <linux/sh_clk.h> |
25 | #include <linux/clkdev.h> | 25 | #include <linux/clkdev.h> |
26 | #include <mach/clock.h> | 26 | #include "clock.h" |
27 | #include <mach/common.h> | 27 | #include "common.h" |
28 | 28 | ||
29 | /* | 29 | /* |
30 | * MD1 = 1 MD1 = 0 | 30 | * MD1 = 1 MD1 = 0 |
diff --git a/arch/arm/mach-shmobile/clock-r8a7790.c b/arch/arm/mach-shmobile/clock-r8a7790.c index 296a057109e4..17435c1aa2fe 100644 --- a/arch/arm/mach-shmobile/clock-r8a7790.c +++ b/arch/arm/mach-shmobile/clock-r8a7790.c | |||
@@ -22,9 +22,11 @@ | |||
22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
23 | #include <linux/sh_clk.h> | 23 | #include <linux/sh_clk.h> |
24 | #include <linux/clkdev.h> | 24 | #include <linux/clkdev.h> |
25 | #include <mach/clock.h> | 25 | |
26 | #include <mach/common.h> | 26 | #include "clock.h" |
27 | #include <mach/r8a7790.h> | 27 | #include "common.h" |
28 | #include "r8a7790.h" | ||
29 | #include "rcar-gen2.h" | ||
28 | 30 | ||
29 | /* | 31 | /* |
30 | * MD EXTAL PLL0 PLL1 PLL3 | 32 | * MD EXTAL PLL0 PLL1 PLL3 |
diff --git a/arch/arm/mach-shmobile/clock-r8a7791.c b/arch/arm/mach-shmobile/clock-r8a7791.c index e2fdfcc14436..10e193d707f5 100644 --- a/arch/arm/mach-shmobile/clock-r8a7791.c +++ b/arch/arm/mach-shmobile/clock-r8a7791.c | |||
@@ -23,9 +23,9 @@ | |||
23 | #include <linux/kernel.h> | 23 | #include <linux/kernel.h> |
24 | #include <linux/sh_clk.h> | 24 | #include <linux/sh_clk.h> |
25 | #include <linux/clkdev.h> | 25 | #include <linux/clkdev.h> |
26 | #include <mach/clock.h> | 26 | #include "clock.h" |
27 | #include <mach/common.h> | 27 | #include "common.h" |
28 | #include <mach/rcar-gen2.h> | 28 | #include "rcar-gen2.h" |
29 | 29 | ||
30 | /* | 30 | /* |
31 | * MD EXTAL PLL0 PLL1 PLL3 | 31 | * MD EXTAL PLL0 PLL1 PLL3 |
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c index d16d9ca7f79e..7071676145c4 100644 --- a/arch/arm/mach-shmobile/clock-sh7372.c +++ b/arch/arm/mach-shmobile/clock-sh7372.c | |||
@@ -21,8 +21,8 @@ | |||
21 | #include <linux/io.h> | 21 | #include <linux/io.h> |
22 | #include <linux/sh_clk.h> | 22 | #include <linux/sh_clk.h> |
23 | #include <linux/clkdev.h> | 23 | #include <linux/clkdev.h> |
24 | #include <mach/clock.h> | 24 | #include "clock.h" |
25 | #include <mach/common.h> | 25 | #include "common.h" |
26 | 26 | ||
27 | /* SH7372 registers */ | 27 | /* SH7372 registers */ |
28 | #define FRQCRA IOMEM(0xe6150000) | 28 | #define FRQCRA IOMEM(0xe6150000) |
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c index 0d9cd1fe0212..37f48383e05a 100644 --- a/arch/arm/mach-shmobile/clock-sh73a0.c +++ b/arch/arm/mach-shmobile/clock-sh73a0.c | |||
@@ -22,8 +22,8 @@ | |||
22 | #include <linux/sh_clk.h> | 22 | #include <linux/sh_clk.h> |
23 | #include <linux/clkdev.h> | 23 | #include <linux/clkdev.h> |
24 | #include <asm/processor.h> | 24 | #include <asm/processor.h> |
25 | #include <mach/clock.h> | 25 | #include "clock.h" |
26 | #include <mach/common.h> | 26 | #include "common.h" |
27 | 27 | ||
28 | #define FRQCRA IOMEM(0xe6150000) | 28 | #define FRQCRA IOMEM(0xe6150000) |
29 | #define FRQCRB IOMEM(0xe6150004) | 29 | #define FRQCRB IOMEM(0xe6150004) |
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c index e7232a0373b9..806f94038cc4 100644 --- a/arch/arm/mach-shmobile/clock.c +++ b/arch/arm/mach-shmobile/clock.c | |||
@@ -25,7 +25,7 @@ | |||
25 | #ifdef CONFIG_COMMON_CLK | 25 | #ifdef CONFIG_COMMON_CLK |
26 | #include <linux/clk.h> | 26 | #include <linux/clk.h> |
27 | #include <linux/clkdev.h> | 27 | #include <linux/clkdev.h> |
28 | #include <mach/clock.h> | 28 | #include "clock.h" |
29 | 29 | ||
30 | void __init shmobile_clk_workaround(const struct clk_name *clks, | 30 | void __init shmobile_clk_workaround(const struct clk_name *clks, |
31 | int nr_clks, bool enable) | 31 | int nr_clks, bool enable) |
@@ -49,8 +49,8 @@ void __init shmobile_clk_workaround(const struct clk_name *clks, | |||
49 | #else /* CONFIG_COMMON_CLK */ | 49 | #else /* CONFIG_COMMON_CLK */ |
50 | #include <linux/sh_clk.h> | 50 | #include <linux/sh_clk.h> |
51 | #include <linux/export.h> | 51 | #include <linux/export.h> |
52 | #include <mach/clock.h> | 52 | #include "clock.h" |
53 | #include <mach/common.h> | 53 | #include "common.h" |
54 | 54 | ||
55 | unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) | 55 | unsigned long shmobile_fixed_ratio_clk_recalc(struct clk *clk) |
56 | { | 56 | { |
diff --git a/arch/arm/mach-shmobile/include/mach/clock.h b/arch/arm/mach-shmobile/clock.h index 31b6417463e6..31b6417463e6 100644 --- a/arch/arm/mach-shmobile/include/mach/clock.h +++ b/arch/arm/mach-shmobile/clock.h | |||
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/common.h index f7a360edcc35..f7a360edcc35 100644 --- a/arch/arm/mach-shmobile/include/mach/common.h +++ b/arch/arm/mach-shmobile/common.h | |||
diff --git a/arch/arm/mach-shmobile/console.c b/arch/arm/mach-shmobile/console.c index 9411a5bf4fd6..f2e79f2376e1 100644 --- a/arch/arm/mach-shmobile/console.c +++ b/arch/arm/mach-shmobile/console.c | |||
@@ -19,8 +19,8 @@ | |||
19 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
20 | #include <linux/init.h> | 20 | #include <linux/init.h> |
21 | #include <linux/platform_device.h> | 21 | #include <linux/platform_device.h> |
22 | #include <mach/common.h> | ||
23 | #include <asm/mach/map.h> | 22 | #include <asm/mach/map.h> |
23 | #include "common.h" | ||
24 | 24 | ||
25 | void __init shmobile_setup_console(void) | 25 | void __init shmobile_setup_console(void) |
26 | { | 26 | { |
diff --git a/arch/arm/mach-shmobile/include/mach/dma-register.h b/arch/arm/mach-shmobile/dma-register.h index 97c40bd9b94f..97c40bd9b94f 100644 --- a/arch/arm/mach-shmobile/include/mach/dma-register.h +++ b/arch/arm/mach-shmobile/dma-register.h | |||
diff --git a/arch/arm/mach-shmobile/include/mach/irqs.h b/arch/arm/mach-shmobile/include/mach/irqs.h index d241bfd6926d..5aee83f079e2 100644 --- a/arch/arm/mach-shmobile/include/mach/irqs.h +++ b/arch/arm/mach-shmobile/include/mach/irqs.h | |||
@@ -1,24 +1,10 @@ | |||
1 | #ifndef __ASM_MACH_IRQS_H | 1 | #ifndef __ASM_MACH_IRQS_H |
2 | #define __ASM_MACH_IRQS_H | 2 | #define __ASM_MACH_IRQS_H |
3 | 3 | ||
4 | #include <linux/sh_intc.h> | 4 | /* Stuck here until drivers/pinctl/sh-pfc gets rid of legacy code */ |
5 | |||
6 | /* GIC */ | ||
7 | #define gic_spi(nr) ((nr) + 32) | ||
8 | #define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ | ||
9 | |||
10 | /* INTCS */ | ||
11 | #define INTCS_VECT_BASE 0x3400 | ||
12 | #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) | ||
13 | #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) | ||
14 | 5 | ||
15 | /* External IRQ pins */ | 6 | /* External IRQ pins */ |
16 | #define IRQPIN_BASE 2000 | 7 | #define IRQPIN_BASE 2000 |
17 | #define irq_pin(nr) ((nr) + IRQPIN_BASE) | 8 | #define irq_pin(nr) ((nr) + IRQPIN_BASE) |
18 | 9 | ||
19 | /* GPIO IRQ */ | ||
20 | #define _GPIO_IRQ_BASE 2500 | ||
21 | #define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x)) | ||
22 | #define GPIO_IRQ(x, y) (_GPIO_IRQ_BASE + (32 * x) + y) | ||
23 | |||
24 | #endif /* __ASM_MACH_IRQS_H */ | 10 | #endif /* __ASM_MACH_IRQS_H */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7779.h b/arch/arm/mach-shmobile/include/mach/r8a7779.h index 88eeceaf1088..def10a29e09a 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7779.h +++ b/arch/arm/mach-shmobile/include/mach/r8a7779.h | |||
@@ -2,8 +2,6 @@ | |||
2 | #define __ASM_R8A7779_H__ | 2 | #define __ASM_R8A7779_H__ |
3 | 3 | ||
4 | #include <linux/sh_clk.h> | 4 | #include <linux/sh_clk.h> |
5 | #include <linux/pm_domain.h> | ||
6 | #include <mach/pm-rcar.h> | ||
7 | 5 | ||
8 | /* HPB-DMA slave IDs */ | 6 | /* HPB-DMA slave IDs */ |
9 | enum { | 7 | enum { |
@@ -12,16 +10,6 @@ enum { | |||
12 | HPBDMA_SLAVE_SDHI0_RX, | 10 | HPBDMA_SLAVE_SDHI0_RX, |
13 | }; | 11 | }; |
14 | 12 | ||
15 | struct r8a7779_pm_domain { | ||
16 | struct generic_pm_domain genpd; | ||
17 | struct rcar_sysc_ch ch; | ||
18 | }; | ||
19 | |||
20 | static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) | ||
21 | { | ||
22 | return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; | ||
23 | } | ||
24 | |||
25 | extern void r8a7779_init_delay(void); | 13 | extern void r8a7779_init_delay(void); |
26 | extern void r8a7779_init_irq_extpin(int irlm); | 14 | extern void r8a7779_init_irq_extpin(int irlm); |
27 | extern void r8a7779_init_irq_extpin_dt(int irlm); | 15 | extern void r8a7779_init_irq_extpin_dt(int irlm); |
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c index a91caad7db7c..e2af00b1bd9d 100644 --- a/arch/arm/mach-shmobile/intc-sh7372.c +++ b/arch/arm/mach-shmobile/intc-sh7372.c | |||
@@ -22,11 +22,10 @@ | |||
22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
23 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/sh_intc.h> | ||
26 | #include <mach/intc.h> | ||
27 | #include <mach/irqs.h> | ||
28 | #include <asm/mach-types.h> | 25 | #include <asm/mach-types.h> |
29 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
27 | #include "intc.h" | ||
28 | #include "irqs.h" | ||
30 | 29 | ||
31 | enum { | 30 | enum { |
32 | UNUSED_INTCA = 0, | 31 | UNUSED_INTCA = 0, |
diff --git a/arch/arm/mach-shmobile/intc-sh73a0.c b/arch/arm/mach-shmobile/intc-sh73a0.c index 19a26f4579b3..44457a94897b 100644 --- a/arch/arm/mach-shmobile/intc-sh73a0.c +++ b/arch/arm/mach-shmobile/intc-sh73a0.c | |||
@@ -22,15 +22,16 @@ | |||
22 | #include <linux/module.h> | 22 | #include <linux/module.h> |
23 | #include <linux/irq.h> | 23 | #include <linux/irq.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/sh_intc.h> | ||
26 | #include <linux/irqchip.h> | 25 | #include <linux/irqchip.h> |
27 | #include <linux/irqchip/arm-gic.h> | 26 | #include <linux/irqchip/arm-gic.h> |
28 | #include <mach/intc.h> | 27 | |
29 | #include <mach/irqs.h> | ||
30 | #include <mach/sh73a0.h> | ||
31 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
32 | #include <asm/mach/arch.h> | 29 | #include <asm/mach/arch.h> |
33 | 30 | ||
31 | #include "intc.h" | ||
32 | #include "irqs.h" | ||
33 | #include "sh73a0.h" | ||
34 | |||
34 | enum { | 35 | enum { |
35 | UNUSED = 0, | 36 | UNUSED = 0, |
36 | 37 | ||
diff --git a/arch/arm/mach-shmobile/include/mach/intc.h b/arch/arm/mach-shmobile/intc.h index a5603c76cfe0..a5603c76cfe0 100644 --- a/arch/arm/mach-shmobile/include/mach/intc.h +++ b/arch/arm/mach-shmobile/intc.h | |||
diff --git a/arch/arm/mach-shmobile/irqs.h b/arch/arm/mach-shmobile/irqs.h new file mode 100644 index 000000000000..4ff2d2aa94f0 --- /dev/null +++ b/arch/arm/mach-shmobile/irqs.h | |||
@@ -0,0 +1,21 @@ | |||
1 | #ifndef __SHMOBILE_IRQS_H | ||
2 | #define __SHMOBILE_IRQS_H | ||
3 | |||
4 | #include <linux/sh_intc.h> | ||
5 | #include <mach/irqs.h> | ||
6 | |||
7 | /* GIC */ | ||
8 | #define gic_spi(nr) ((nr) + 32) | ||
9 | #define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */ | ||
10 | |||
11 | /* INTCS */ | ||
12 | #define INTCS_VECT_BASE 0x3400 | ||
13 | #define INTCS_VECT(n, vect) INTC_VECT((n), INTCS_VECT_BASE + (vect)) | ||
14 | #define intcs_evt2irq(evt) evt2irq(INTCS_VECT_BASE + (evt)) | ||
15 | |||
16 | /* GPIO IRQ */ | ||
17 | #define _GPIO_IRQ_BASE 2500 | ||
18 | #define GPIO_IRQ_BASE(x) (_GPIO_IRQ_BASE + (32 * x)) | ||
19 | #define GPIO_IRQ(x, y) (_GPIO_IRQ_BASE + (32 * x) + y) | ||
20 | |||
21 | #endif /* __SHMOBILE_IRQS_H */ | ||
diff --git a/arch/arm/mach-shmobile/platsmp-apmu.c b/arch/arm/mach-shmobile/platsmp-apmu.c index 8cb641c00fdb..fe648f5d8f06 100644 --- a/arch/arm/mach-shmobile/platsmp-apmu.c +++ b/arch/arm/mach-shmobile/platsmp-apmu.c | |||
@@ -16,7 +16,7 @@ | |||
16 | #include <asm/cacheflush.h> | 16 | #include <asm/cacheflush.h> |
17 | #include <asm/cp15.h> | 17 | #include <asm/cp15.h> |
18 | #include <asm/smp_plat.h> | 18 | #include <asm/smp_plat.h> |
19 | #include <mach/common.h> | 19 | #include "common.h" |
20 | 20 | ||
21 | static struct { | 21 | static struct { |
22 | void __iomem *iomem; | 22 | void __iomem *iomem; |
diff --git a/arch/arm/mach-shmobile/platsmp-scu.c b/arch/arm/mach-shmobile/platsmp-scu.c index 673ad6e80869..64663110ab6c 100644 --- a/arch/arm/mach-shmobile/platsmp-scu.c +++ b/arch/arm/mach-shmobile/platsmp-scu.c | |||
@@ -15,7 +15,7 @@ | |||
15 | #include <asm/cacheflush.h> | 15 | #include <asm/cacheflush.h> |
16 | #include <asm/smp_plat.h> | 16 | #include <asm/smp_plat.h> |
17 | #include <asm/smp_scu.h> | 17 | #include <asm/smp_scu.h> |
18 | #include <mach/common.h> | 18 | #include "common.h" |
19 | 19 | ||
20 | static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb, | 20 | static int shmobile_smp_scu_notifier_call(struct notifier_block *nfb, |
21 | unsigned long action, void *hcpu) | 21 | unsigned long action, void *hcpu) |
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c index 9ebc246b8d7d..3923e09e966d 100644 --- a/arch/arm/mach-shmobile/platsmp.c +++ b/arch/arm/mach-shmobile/platsmp.c | |||
@@ -13,7 +13,7 @@ | |||
13 | #include <linux/init.h> | 13 | #include <linux/init.h> |
14 | #include <asm/cacheflush.h> | 14 | #include <asm/cacheflush.h> |
15 | #include <asm/smp_plat.h> | 15 | #include <asm/smp_plat.h> |
16 | #include <mach/common.h> | 16 | #include "common.h" |
17 | 17 | ||
18 | extern unsigned long shmobile_smp_fn[]; | 18 | extern unsigned long shmobile_smp_fn[]; |
19 | extern unsigned long shmobile_smp_arg[]; | 19 | extern unsigned long shmobile_smp_arg[]; |
diff --git a/arch/arm/mach-shmobile/pm-r8a7740.c b/arch/arm/mach-shmobile/pm-r8a7740.c index 40b87aa1d448..a0d44d537fa0 100644 --- a/arch/arm/mach-shmobile/pm-r8a7740.c +++ b/arch/arm/mach-shmobile/pm-r8a7740.c | |||
@@ -10,8 +10,8 @@ | |||
10 | */ | 10 | */ |
11 | #include <linux/console.h> | 11 | #include <linux/console.h> |
12 | #include <linux/suspend.h> | 12 | #include <linux/suspend.h> |
13 | #include <mach/pm-rmobile.h> | 13 | #include "common.h" |
14 | #include <mach/common.h> | 14 | #include "pm-rmobile.h" |
15 | 15 | ||
16 | #ifdef CONFIG_PM | 16 | #ifdef CONFIG_PM |
17 | static int r8a7740_pd_a4s_suspend(void) | 17 | static int r8a7740_pd_a4s_suspend(void) |
diff --git a/arch/arm/mach-shmobile/pm-r8a7779.c b/arch/arm/mach-shmobile/pm-r8a7779.c index d6fe189b2df6..f0f36cb5ffe7 100644 --- a/arch/arm/mach-shmobile/pm-r8a7779.c +++ b/arch/arm/mach-shmobile/pm-r8a7779.c | |||
@@ -13,20 +13,31 @@ | |||
13 | #include <linux/suspend.h> | 13 | #include <linux/suspend.h> |
14 | #include <linux/err.h> | 14 | #include <linux/err.h> |
15 | #include <linux/pm_clock.h> | 15 | #include <linux/pm_clock.h> |
16 | #include <linux/pm_domain.h> | ||
16 | #include <linux/platform_device.h> | 17 | #include <linux/platform_device.h> |
17 | #include <linux/delay.h> | 18 | #include <linux/delay.h> |
18 | #include <linux/irq.h> | 19 | #include <linux/irq.h> |
19 | #include <linux/interrupt.h> | 20 | #include <linux/interrupt.h> |
20 | #include <linux/console.h> | 21 | #include <linux/console.h> |
21 | #include <asm/io.h> | 22 | #include <asm/io.h> |
22 | #include <mach/common.h> | ||
23 | #include <mach/pm-rcar.h> | ||
24 | #include <mach/r8a7779.h> | 23 | #include <mach/r8a7779.h> |
24 | #include "common.h" | ||
25 | #include "pm-rcar.h" | ||
25 | 26 | ||
26 | /* SYSC */ | 27 | /* SYSC */ |
27 | #define SYSCIER 0x0c | 28 | #define SYSCIER 0x0c |
28 | #define SYSCIMR 0x10 | 29 | #define SYSCIMR 0x10 |
29 | 30 | ||
31 | struct r8a7779_pm_domain { | ||
32 | struct generic_pm_domain genpd; | ||
33 | struct rcar_sysc_ch ch; | ||
34 | }; | ||
35 | |||
36 | static inline struct rcar_sysc_ch *to_r8a7779_ch(struct generic_pm_domain *d) | ||
37 | { | ||
38 | return &container_of(d, struct r8a7779_pm_domain, genpd)->ch; | ||
39 | } | ||
40 | |||
30 | #if defined(CONFIG_PM) || defined(CONFIG_SMP) | 41 | #if defined(CONFIG_PM) || defined(CONFIG_SMP) |
31 | 42 | ||
32 | static void __init r8a7779_sysc_init(void) | 43 | static void __init r8a7779_sysc_init(void) |
diff --git a/arch/arm/mach-shmobile/pm-r8a7790.c b/arch/arm/mach-shmobile/pm-r8a7790.c index fc82839e2c2a..8845433a00b3 100644 --- a/arch/arm/mach-shmobile/pm-r8a7790.c +++ b/arch/arm/mach-shmobile/pm-r8a7790.c | |||
@@ -11,9 +11,11 @@ | |||
11 | */ | 11 | */ |
12 | 12 | ||
13 | #include <linux/kernel.h> | 13 | #include <linux/kernel.h> |
14 | |||
14 | #include <asm/io.h> | 15 | #include <asm/io.h> |
15 | #include <mach/pm-rcar.h> | 16 | |
16 | #include <mach/r8a7790.h> | 17 | #include "pm-rcar.h" |
18 | #include "r8a7790.h" | ||
17 | 19 | ||
18 | /* SYSC */ | 20 | /* SYSC */ |
19 | #define SYSCIER 0x0c | 21 | #define SYSCIER 0x0c |
diff --git a/arch/arm/mach-shmobile/pm-rcar.c b/arch/arm/mach-shmobile/pm-rcar.c index 1f465a12d1b1..34b8a5674f85 100644 --- a/arch/arm/mach-shmobile/pm-rcar.c +++ b/arch/arm/mach-shmobile/pm-rcar.c | |||
@@ -13,7 +13,7 @@ | |||
13 | #include <linux/mm.h> | 13 | #include <linux/mm.h> |
14 | #include <linux/spinlock.h> | 14 | #include <linux/spinlock.h> |
15 | #include <asm/io.h> | 15 | #include <asm/io.h> |
16 | #include <mach/pm-rcar.h> | 16 | #include "pm-rcar.h" |
17 | 17 | ||
18 | /* SYSC */ | 18 | /* SYSC */ |
19 | #define SYSCSR 0x00 | 19 | #define SYSCSR 0x00 |
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rcar.h b/arch/arm/mach-shmobile/pm-rcar.h index ef3a1ef628f1..ef3a1ef628f1 100644 --- a/arch/arm/mach-shmobile/include/mach/pm-rcar.h +++ b/arch/arm/mach-shmobile/pm-rcar.h | |||
diff --git a/arch/arm/mach-shmobile/pm-rmobile.c b/arch/arm/mach-shmobile/pm-rmobile.c index f710235aff2f..ebdd16e94a84 100644 --- a/arch/arm/mach-shmobile/pm-rmobile.c +++ b/arch/arm/mach-shmobile/pm-rmobile.c | |||
@@ -17,7 +17,7 @@ | |||
17 | #include <linux/pm.h> | 17 | #include <linux/pm.h> |
18 | #include <linux/pm_clock.h> | 18 | #include <linux/pm_clock.h> |
19 | #include <asm/io.h> | 19 | #include <asm/io.h> |
20 | #include <mach/pm-rmobile.h> | 20 | #include "pm-rmobile.h" |
21 | 21 | ||
22 | /* SYSC */ | 22 | /* SYSC */ |
23 | #define SPDCR IOMEM(0xe6180008) | 23 | #define SPDCR IOMEM(0xe6180008) |
diff --git a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h b/arch/arm/mach-shmobile/pm-rmobile.h index 690553a06887..690553a06887 100644 --- a/arch/arm/mach-shmobile/include/mach/pm-rmobile.h +++ b/arch/arm/mach-shmobile/pm-rmobile.h | |||
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c index 0de75fd394b9..7e5c2676c489 100644 --- a/arch/arm/mach-shmobile/pm-sh7372.c +++ b/arch/arm/mach-shmobile/pm-sh7372.c | |||
@@ -21,13 +21,15 @@ | |||
21 | #include <linux/irq.h> | 21 | #include <linux/irq.h> |
22 | #include <linux/bitrev.h> | 22 | #include <linux/bitrev.h> |
23 | #include <linux/console.h> | 23 | #include <linux/console.h> |
24 | |||
24 | #include <asm/cpuidle.h> | 25 | #include <asm/cpuidle.h> |
25 | #include <asm/io.h> | 26 | #include <asm/io.h> |
26 | #include <asm/tlbflush.h> | 27 | #include <asm/tlbflush.h> |
27 | #include <asm/suspend.h> | 28 | #include <asm/suspend.h> |
28 | #include <mach/common.h> | 29 | |
29 | #include <mach/sh7372.h> | 30 | #include "common.h" |
30 | #include <mach/pm-rmobile.h> | 31 | #include "pm-rmobile.h" |
32 | #include "sh7372.h" | ||
31 | 33 | ||
32 | /* DBG */ | 34 | /* DBG */ |
33 | #define DBGREG1 IOMEM(0xe6100020) | 35 | #define DBGREG1 IOMEM(0xe6100020) |
diff --git a/arch/arm/mach-shmobile/pm-sh73a0.c b/arch/arm/mach-shmobile/pm-sh73a0.c index 99086e98fbbc..a7e466817965 100644 --- a/arch/arm/mach-shmobile/pm-sh73a0.c +++ b/arch/arm/mach-shmobile/pm-sh73a0.c | |||
@@ -9,7 +9,7 @@ | |||
9 | */ | 9 | */ |
10 | 10 | ||
11 | #include <linux/suspend.h> | 11 | #include <linux/suspend.h> |
12 | #include <mach/common.h> | 12 | #include "common.h" |
13 | 13 | ||
14 | #ifdef CONFIG_SUSPEND | 14 | #ifdef CONFIG_SUSPEND |
15 | static int sh73a0_enter_suspend(suspend_state_t suspend_state) | 15 | static int sh73a0_enter_suspend(suspend_state_t suspend_state) |
diff --git a/arch/arm/mach-shmobile/include/mach/r7s72100.h b/arch/arm/mach-shmobile/r7s72100.h index 5f34b20ecd4a..efb723c88dd0 100644 --- a/arch/arm/mach-shmobile/include/mach/r7s72100.h +++ b/arch/arm/mach-shmobile/r7s72100.h | |||
@@ -3,6 +3,5 @@ | |||
3 | 3 | ||
4 | void r7s72100_add_dt_devices(void); | 4 | void r7s72100_add_dt_devices(void); |
5 | void r7s72100_clock_init(void); | 5 | void r7s72100_clock_init(void); |
6 | void r7s72100_init_early(void); | ||
7 | 6 | ||
8 | #endif /* __ASM_R7S72100_H__ */ | 7 | #endif /* __ASM_R7S72100_H__ */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a73a4.h b/arch/arm/mach-shmobile/r8a73a4.h index ce8bdd1d8a8a..ce8bdd1d8a8a 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a73a4.h +++ b/arch/arm/mach-shmobile/r8a73a4.h | |||
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7740.h b/arch/arm/mach-shmobile/r8a7740.h index 5e3c9ec06303..1d1a5fd78b6b 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7740.h +++ b/arch/arm/mach-shmobile/r8a7740.h | |||
@@ -19,8 +19,6 @@ | |||
19 | #ifndef __ASM_R8A7740_H__ | 19 | #ifndef __ASM_R8A7740_H__ |
20 | #define __ASM_R8A7740_H__ | 20 | #define __ASM_R8A7740_H__ |
21 | 21 | ||
22 | #include <mach/pm-rmobile.h> | ||
23 | |||
24 | /* | 22 | /* |
25 | * MD_CKx pin | 23 | * MD_CKx pin |
26 | */ | 24 | */ |
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7778.h b/arch/arm/mach-shmobile/r8a7778.h index f4076a50e970..f4076a50e970 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7778.h +++ b/arch/arm/mach-shmobile/r8a7778.h | |||
diff --git a/arch/arm/mach-shmobile/include/mach/r8a7790.h b/arch/arm/mach-shmobile/r8a7790.h index 0b95babe84ba..459827f1369b 100644 --- a/arch/arm/mach-shmobile/include/mach/r8a7790.h +++ b/arch/arm/mach-shmobile/r8a7790.h | |||
@@ -1,8 +1,6 @@ | |||
1 | #ifndef __ASM_R8A7790_H__ | 1 | #ifndef __ASM_R8A7790_H__ |
2 | #define __ASM_R8A7790_H__ | 2 | #define __ASM_R8A7790_H__ |
3 | 3 | ||
4 | #include <mach/rcar-gen2.h> | ||
5 | |||
6 | /* DMA slave IDs */ | 4 | /* DMA slave IDs */ |
7 | enum { | 5 | enum { |
8 | RCAR_DMA_SLAVE_INVALID, | 6 | RCAR_DMA_SLAVE_INVALID, |
@@ -33,7 +31,6 @@ void r8a7790_add_dt_devices(void); | |||
33 | void r8a7790_clock_init(void); | 31 | void r8a7790_clock_init(void); |
34 | void r8a7790_pinmux_init(void); | 32 | void r8a7790_pinmux_init(void); |
35 | void r8a7790_pm_init(void); | 33 | void r8a7790_pm_init(void); |
36 | void r8a7790_init_early(void); | ||
37 | extern struct smp_operations r8a7790_smp_ops; | 34 | extern struct smp_operations r8a7790_smp_ops; |
38 | 35 | ||
39 | #endif /* __ASM_R8A7790_H__ */ | 36 | #endif /* __ASM_R8A7790_H__ */ |
diff --git a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h b/arch/arm/mach-shmobile/rcar-gen2.h index 43f606eb2d82..43f606eb2d82 100644 --- a/arch/arm/mach-shmobile/include/mach/rcar-gen2.h +++ b/arch/arm/mach-shmobile/rcar-gen2.h | |||
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c index d953ff6e78a2..b06a9e8f59a5 100644 --- a/arch/arm/mach-shmobile/setup-emev2.c +++ b/arch/arm/mach-shmobile/setup-emev2.c | |||
@@ -16,14 +16,13 @@ | |||
16 | * along with this program; if not, write to the Free Software | 16 | * along with this program; if not, write to the Free Software |
17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
18 | */ | 18 | */ |
19 | #include <linux/clk-provider.h> | ||
20 | #include <linux/kernel.h> | 19 | #include <linux/kernel.h> |
21 | #include <linux/init.h> | 20 | #include <linux/init.h> |
22 | #include <linux/of_platform.h> | 21 | #include <linux/mm.h> |
23 | #include <mach/common.h> | ||
24 | #include <asm/mach-types.h> | 22 | #include <asm/mach-types.h> |
25 | #include <asm/mach/arch.h> | 23 | #include <asm/mach/arch.h> |
26 | #include <asm/mach/map.h> | 24 | #include <asm/mach/map.h> |
25 | #include "common.h" | ||
27 | 26 | ||
28 | static struct map_desc emev2_io_desc[] __initdata = { | 27 | static struct map_desc emev2_io_desc[] __initdata = { |
29 | #ifdef CONFIG_SMP | 28 | #ifdef CONFIG_SMP |
@@ -42,17 +41,6 @@ static void __init emev2_map_io(void) | |||
42 | iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); | 41 | iotable_init(emev2_io_desc, ARRAY_SIZE(emev2_io_desc)); |
43 | } | 42 | } |
44 | 43 | ||
45 | static void __init emev2_init_delay(void) | ||
46 | { | ||
47 | shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */ | ||
48 | } | ||
49 | |||
50 | static void __init emev2_add_standard_devices_dt(void) | ||
51 | { | ||
52 | of_clk_init(NULL); | ||
53 | of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); | ||
54 | } | ||
55 | |||
56 | static const char *emev2_boards_compat_dt[] __initconst = { | 44 | static const char *emev2_boards_compat_dt[] __initconst = { |
57 | "renesas,emev2", | 45 | "renesas,emev2", |
58 | NULL, | 46 | NULL, |
@@ -63,8 +51,7 @@ extern struct smp_operations emev2_smp_ops; | |||
63 | DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") | 51 | DT_MACHINE_START(EMEV2_DT, "Generic Emma Mobile EV2 (Flattened Device Tree)") |
64 | .smp = smp_ops(emev2_smp_ops), | 52 | .smp = smp_ops(emev2_smp_ops), |
65 | .map_io = emev2_map_io, | 53 | .map_io = emev2_map_io, |
66 | .init_early = emev2_init_delay, | 54 | .init_early = shmobile_init_delay, |
67 | .init_machine = emev2_add_standard_devices_dt, | ||
68 | .init_late = shmobile_init_late, | 55 | .init_late = shmobile_init_late, |
69 | .dt_compat = emev2_boards_compat_dt, | 56 | .dt_compat = emev2_boards_compat_dt, |
70 | MACHINE_END | 57 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/setup-r7s72100.c b/arch/arm/mach-shmobile/setup-r7s72100.c index 3885a598c66b..f3b3b14ba972 100644 --- a/arch/arm/mach-shmobile/setup-r7s72100.c +++ b/arch/arm/mach-shmobile/setup-r7s72100.c | |||
@@ -22,11 +22,13 @@ | |||
22 | #include <linux/kernel.h> | 22 | #include <linux/kernel.h> |
23 | #include <linux/of_platform.h> | 23 | #include <linux/of_platform.h> |
24 | #include <linux/sh_timer.h> | 24 | #include <linux/sh_timer.h> |
25 | #include <mach/common.h> | 25 | |
26 | #include <mach/irqs.h> | ||
27 | #include <mach/r7s72100.h> | ||
28 | #include <asm/mach/arch.h> | 26 | #include <asm/mach/arch.h> |
29 | 27 | ||
28 | #include "common.h" | ||
29 | #include "irqs.h" | ||
30 | #include "r7s72100.h" | ||
31 | |||
30 | static struct resource mtu2_resources[] __initdata = { | 32 | static struct resource mtu2_resources[] __initdata = { |
31 | DEFINE_RES_MEM(0xfcff0000, 0x400), | 33 | DEFINE_RES_MEM(0xfcff0000, 0x400), |
32 | DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"), | 34 | DEFINE_RES_IRQ_NAMED(gic_iid(139), "tgi0a"), |
@@ -43,11 +45,6 @@ void __init r7s72100_add_dt_devices(void) | |||
43 | r7s72100_register_mtu2(); | 45 | r7s72100_register_mtu2(); |
44 | } | 46 | } |
45 | 47 | ||
46 | void __init r7s72100_init_early(void) | ||
47 | { | ||
48 | shmobile_setup_delay(400, 1, 3); /* Cortex-A9 @ 400MHz */ | ||
49 | } | ||
50 | |||
51 | #ifdef CONFIG_USE_OF | 48 | #ifdef CONFIG_USE_OF |
52 | static const char *r7s72100_boards_compat_dt[] __initdata = { | 49 | static const char *r7s72100_boards_compat_dt[] __initdata = { |
53 | "renesas,r7s72100", | 50 | "renesas,r7s72100", |
@@ -55,7 +52,7 @@ static const char *r7s72100_boards_compat_dt[] __initdata = { | |||
55 | }; | 52 | }; |
56 | 53 | ||
57 | DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") | 54 | DT_MACHINE_START(R7S72100_DT, "Generic R7S72100 (Flattened Device Tree)") |
58 | .init_early = r7s72100_init_early, | 55 | .init_early = shmobile_init_delay, |
59 | .dt_compat = r7s72100_boards_compat_dt, | 56 | .dt_compat = r7s72100_boards_compat_dt, |
60 | MACHINE_END | 57 | MACHINE_END |
61 | #endif /* CONFIG_USE_OF */ | 58 | #endif /* CONFIG_USE_OF */ |
diff --git a/arch/arm/mach-shmobile/setup-r8a73a4.c b/arch/arm/mach-shmobile/setup-r8a73a4.c index aaaaf6e8b706..cc9823246847 100644 --- a/arch/arm/mach-shmobile/setup-r8a73a4.c +++ b/arch/arm/mach-shmobile/setup-r8a73a4.c | |||
@@ -24,12 +24,14 @@ | |||
24 | #include <linux/serial_sci.h> | 24 | #include <linux/serial_sci.h> |
25 | #include <linux/sh_dma.h> | 25 | #include <linux/sh_dma.h> |
26 | #include <linux/sh_timer.h> | 26 | #include <linux/sh_timer.h> |
27 | #include <mach/common.h> | 27 | |
28 | #include <mach/dma-register.h> | ||
29 | #include <mach/irqs.h> | ||
30 | #include <mach/r8a73a4.h> | ||
31 | #include <asm/mach/arch.h> | 28 | #include <asm/mach/arch.h> |
32 | 29 | ||
30 | #include "common.h" | ||
31 | #include "dma-register.h" | ||
32 | #include "irqs.h" | ||
33 | #include "r8a73a4.h" | ||
34 | |||
33 | static const struct resource pfc_resources[] = { | 35 | static const struct resource pfc_resources[] = { |
34 | DEFINE_RES_MEM(0xe6050000, 0x9000), | 36 | DEFINE_RES_MEM(0xe6050000, 0x9000), |
35 | }; | 37 | }; |
diff --git a/arch/arm/mach-shmobile/setup-r8a7740.c b/arch/arm/mach-shmobile/setup-r8a7740.c index 35dec233301e..348af358a239 100644 --- a/arch/arm/mach-shmobile/setup-r8a7740.c +++ b/arch/arm/mach-shmobile/setup-r8a7740.c | |||
@@ -31,16 +31,18 @@ | |||
31 | #include <linux/sh_dma.h> | 31 | #include <linux/sh_dma.h> |
32 | #include <linux/sh_timer.h> | 32 | #include <linux/sh_timer.h> |
33 | #include <linux/platform_data/sh_ipmmu.h> | 33 | #include <linux/platform_data/sh_ipmmu.h> |
34 | #include <mach/dma-register.h> | 34 | |
35 | #include <mach/r8a7740.h> | ||
36 | #include <mach/pm-rmobile.h> | ||
37 | #include <mach/common.h> | ||
38 | #include <mach/irqs.h> | ||
39 | #include <asm/mach-types.h> | 35 | #include <asm/mach-types.h> |
40 | #include <asm/mach/map.h> | 36 | #include <asm/mach/map.h> |
41 | #include <asm/mach/arch.h> | 37 | #include <asm/mach/arch.h> |
42 | #include <asm/mach/time.h> | 38 | #include <asm/mach/time.h> |
43 | 39 | ||
40 | #include "common.h" | ||
41 | #include "dma-register.h" | ||
42 | #include "irqs.h" | ||
43 | #include "pm-rmobile.h" | ||
44 | #include "r8a7740.h" | ||
45 | |||
44 | static struct map_desc r8a7740_io_desc[] __initdata = { | 46 | static struct map_desc r8a7740_io_desc[] __initdata = { |
45 | /* | 47 | /* |
46 | * for CPGA/INTC/PFC | 48 | * for CPGA/INTC/PFC |
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c index 5de7b33295d4..18490af0d0a0 100644 --- a/arch/arm/mach-shmobile/setup-r8a7778.c +++ b/arch/arm/mach-shmobile/setup-r8a7778.c | |||
@@ -37,12 +37,14 @@ | |||
37 | #include <linux/usb/ehci_pdriver.h> | 37 | #include <linux/usb/ehci_pdriver.h> |
38 | #include <linux/usb/ohci_pdriver.h> | 38 | #include <linux/usb/ohci_pdriver.h> |
39 | #include <linux/dma-mapping.h> | 39 | #include <linux/dma-mapping.h> |
40 | #include <mach/irqs.h> | 40 | |
41 | #include <mach/r8a7778.h> | ||
42 | #include <mach/common.h> | ||
43 | #include <asm/mach/arch.h> | 41 | #include <asm/mach/arch.h> |
44 | #include <asm/hardware/cache-l2x0.h> | 42 | #include <asm/hardware/cache-l2x0.h> |
45 | 43 | ||
44 | #include "common.h" | ||
45 | #include "irqs.h" | ||
46 | #include "r8a7778.h" | ||
47 | |||
46 | /* SCIF */ | 48 | /* SCIF */ |
47 | #define R8A7778_SCIF(index, baseaddr, irq) \ | 49 | #define R8A7778_SCIF(index, baseaddr, irq) \ |
48 | static struct plat_sci_port scif##index##_platform_data = { \ | 50 | static struct plat_sci_port scif##index##_platform_data = { \ |
diff --git a/arch/arm/mach-shmobile/setup-r8a7779.c b/arch/arm/mach-shmobile/setup-r8a7779.c index 9c79182d0568..280303cef702 100644 --- a/arch/arm/mach-shmobile/setup-r8a7779.c +++ b/arch/arm/mach-shmobile/setup-r8a7779.c | |||
@@ -40,14 +40,14 @@ | |||
40 | #include <linux/usb/ehci_pdriver.h> | 40 | #include <linux/usb/ehci_pdriver.h> |
41 | #include <linux/usb/ohci_pdriver.h> | 41 | #include <linux/usb/ohci_pdriver.h> |
42 | #include <linux/pm_runtime.h> | 42 | #include <linux/pm_runtime.h> |
43 | #include <mach/irqs.h> | ||
44 | #include <mach/r8a7779.h> | 43 | #include <mach/r8a7779.h> |
45 | #include <mach/common.h> | ||
46 | #include <asm/mach-types.h> | 44 | #include <asm/mach-types.h> |
47 | #include <asm/mach/arch.h> | 45 | #include <asm/mach/arch.h> |
48 | #include <asm/mach/time.h> | 46 | #include <asm/mach/time.h> |
49 | #include <asm/mach/map.h> | 47 | #include <asm/mach/map.h> |
50 | #include <asm/hardware/cache-l2x0.h> | 48 | #include <asm/hardware/cache-l2x0.h> |
49 | #include "common.h" | ||
50 | #include "irqs.h" | ||
51 | 51 | ||
52 | static struct map_desc r8a7779_io_desc[] __initdata = { | 52 | static struct map_desc r8a7779_io_desc[] __initdata = { |
53 | /* 2M entity map for 0xf0000000 (MPCORE) */ | 53 | /* 2M entity map for 0xf0000000 (MPCORE) */ |
diff --git a/arch/arm/mach-shmobile/setup-r8a7790.c b/arch/arm/mach-shmobile/setup-r8a7790.c index 10e6768968f7..240411b42424 100644 --- a/arch/arm/mach-shmobile/setup-r8a7790.c +++ b/arch/arm/mach-shmobile/setup-r8a7790.c | |||
@@ -26,12 +26,15 @@ | |||
26 | #include <linux/serial_sci.h> | 26 | #include <linux/serial_sci.h> |
27 | #include <linux/sh_dma.h> | 27 | #include <linux/sh_dma.h> |
28 | #include <linux/sh_timer.h> | 28 | #include <linux/sh_timer.h> |
29 | #include <mach/common.h> | 29 | |
30 | #include <mach/dma-register.h> | ||
31 | #include <mach/irqs.h> | ||
32 | #include <mach/r8a7790.h> | ||
33 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
34 | 31 | ||
32 | #include "common.h" | ||
33 | #include "dma-register.h" | ||
34 | #include "irqs.h" | ||
35 | #include "r8a7790.h" | ||
36 | #include "rcar-gen2.h" | ||
37 | |||
35 | /* Audio-DMAC */ | 38 | /* Audio-DMAC */ |
36 | #define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \ | 39 | #define AUDIO_DMAC_SLAVE(_id, _addr, t, r) \ |
37 | { \ | 40 | { \ |
@@ -307,13 +310,6 @@ void __init r8a7790_add_standard_devices(void) | |||
307 | r8a7790_register_audio_dmac(1); | 310 | r8a7790_register_audio_dmac(1); |
308 | } | 311 | } |
309 | 312 | ||
310 | void __init r8a7790_init_early(void) | ||
311 | { | ||
312 | #ifndef CONFIG_ARM_ARCH_TIMER | ||
313 | shmobile_setup_delay(1300, 2, 4); /* Cortex-A15 @ 1300MHz */ | ||
314 | #endif | ||
315 | } | ||
316 | |||
317 | #ifdef CONFIG_USE_OF | 313 | #ifdef CONFIG_USE_OF |
318 | 314 | ||
319 | static const char * const r8a7790_boards_compat_dt[] __initconst = { | 315 | static const char * const r8a7790_boards_compat_dt[] __initconst = { |
@@ -323,7 +319,7 @@ static const char * const r8a7790_boards_compat_dt[] __initconst = { | |||
323 | 319 | ||
324 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") | 320 | DT_MACHINE_START(R8A7790_DT, "Generic R8A7790 (Flattened Device Tree)") |
325 | .smp = smp_ops(r8a7790_smp_ops), | 321 | .smp = smp_ops(r8a7790_smp_ops), |
326 | .init_early = r8a7790_init_early, | 322 | .init_early = shmobile_init_delay, |
327 | .init_time = rcar_gen2_timer_init, | 323 | .init_time = rcar_gen2_timer_init, |
328 | .dt_compat = r8a7790_boards_compat_dt, | 324 | .dt_compat = r8a7790_boards_compat_dt, |
329 | MACHINE_END | 325 | MACHINE_END |
diff --git a/arch/arm/mach-shmobile/setup-r8a7791.c b/arch/arm/mach-shmobile/setup-r8a7791.c index fd5443715b8d..004b11a8fd88 100644 --- a/arch/arm/mach-shmobile/setup-r8a7791.c +++ b/arch/arm/mach-shmobile/setup-r8a7791.c | |||
@@ -26,11 +26,11 @@ | |||
26 | #include <linux/platform_data/irq-renesas-irqc.h> | 26 | #include <linux/platform_data/irq-renesas-irqc.h> |
27 | #include <linux/serial_sci.h> | 27 | #include <linux/serial_sci.h> |
28 | #include <linux/sh_timer.h> | 28 | #include <linux/sh_timer.h> |
29 | #include <mach/common.h> | ||
30 | #include <mach/irqs.h> | ||
31 | #include <mach/r8a7791.h> | 29 | #include <mach/r8a7791.h> |
32 | #include <mach/rcar-gen2.h> | ||
33 | #include <asm/mach/arch.h> | 30 | #include <asm/mach/arch.h> |
31 | #include "common.h" | ||
32 | #include "irqs.h" | ||
33 | #include "rcar-gen2.h" | ||
34 | 34 | ||
35 | static const struct resource pfc_resources[] __initconst = { | 35 | static const struct resource pfc_resources[] __initconst = { |
36 | DEFINE_RES_MEM(0xe6060000, 0x250), | 36 | DEFINE_RES_MEM(0xe6060000, 0x250), |
diff --git a/arch/arm/mach-shmobile/setup-rcar-gen2.c b/arch/arm/mach-shmobile/setup-rcar-gen2.c index 542c5a47173f..fdc714ebc4cd 100644 --- a/arch/arm/mach-shmobile/setup-rcar-gen2.c +++ b/arch/arm/mach-shmobile/setup-rcar-gen2.c | |||
@@ -22,9 +22,9 @@ | |||
22 | #include <linux/clocksource.h> | 22 | #include <linux/clocksource.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
25 | #include <mach/common.h> | ||
26 | #include <mach/rcar-gen2.h> | ||
27 | #include <asm/mach/arch.h> | 25 | #include <asm/mach/arch.h> |
26 | #include "common.h" | ||
27 | #include "rcar-gen2.h" | ||
28 | 28 | ||
29 | #define MODEMR 0xe6160060 | 29 | #define MODEMR 0xe6160060 |
30 | 30 | ||
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c index 2a8b9f2a2f54..9cdfcdfd38fc 100644 --- a/arch/arm/mach-shmobile/setup-sh7372.c +++ b/arch/arm/mach-shmobile/setup-sh7372.c | |||
@@ -29,20 +29,22 @@ | |||
29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
30 | #include <linux/serial_sci.h> | 30 | #include <linux/serial_sci.h> |
31 | #include <linux/sh_dma.h> | 31 | #include <linux/sh_dma.h> |
32 | #include <linux/sh_intc.h> | ||
33 | #include <linux/sh_timer.h> | 32 | #include <linux/sh_timer.h> |
34 | #include <linux/pm_domain.h> | 33 | #include <linux/pm_domain.h> |
35 | #include <linux/dma-mapping.h> | 34 | #include <linux/dma-mapping.h> |
36 | #include <linux/platform_data/sh_ipmmu.h> | 35 | #include <linux/platform_data/sh_ipmmu.h> |
37 | #include <mach/dma-register.h> | 36 | |
38 | #include <mach/irqs.h> | ||
39 | #include <mach/sh7372.h> | ||
40 | #include <mach/common.h> | ||
41 | #include <asm/mach/map.h> | 37 | #include <asm/mach/map.h> |
42 | #include <asm/mach-types.h> | 38 | #include <asm/mach-types.h> |
43 | #include <asm/mach/arch.h> | 39 | #include <asm/mach/arch.h> |
44 | #include <asm/mach/time.h> | 40 | #include <asm/mach/time.h> |
45 | 41 | ||
42 | #include "common.h" | ||
43 | #include "dma-register.h" | ||
44 | #include "irqs.h" | ||
45 | #include "pm-rmobile.h" | ||
46 | #include "sh7372.h" | ||
47 | |||
46 | static struct map_desc sh7372_io_desc[] __initdata = { | 48 | static struct map_desc sh7372_io_desc[] __initdata = { |
47 | /* create a 1:1 entity map for 0xe6xxxxxx | 49 | /* create a 1:1 entity map for 0xe6xxxxxx |
48 | * used by CPGA, INTC and PFC. | 50 | * used by CPGA, INTC and PFC. |
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c index ad00724a2269..224882151667 100644 --- a/arch/arm/mach-shmobile/setup-sh73a0.c +++ b/arch/arm/mach-shmobile/setup-sh73a0.c | |||
@@ -29,19 +29,20 @@ | |||
29 | #include <linux/io.h> | 29 | #include <linux/io.h> |
30 | #include <linux/serial_sci.h> | 30 | #include <linux/serial_sci.h> |
31 | #include <linux/sh_dma.h> | 31 | #include <linux/sh_dma.h> |
32 | #include <linux/sh_intc.h> | ||
33 | #include <linux/sh_timer.h> | 32 | #include <linux/sh_timer.h> |
34 | #include <linux/platform_data/sh_ipmmu.h> | 33 | #include <linux/platform_data/sh_ipmmu.h> |
35 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> | 34 | #include <linux/platform_data/irq-renesas-intc-irqpin.h> |
36 | #include <mach/dma-register.h> | 35 | |
37 | #include <mach/irqs.h> | ||
38 | #include <mach/sh73a0.h> | ||
39 | #include <mach/common.h> | ||
40 | #include <asm/mach-types.h> | 36 | #include <asm/mach-types.h> |
41 | #include <asm/mach/map.h> | 37 | #include <asm/mach/map.h> |
42 | #include <asm/mach/arch.h> | 38 | #include <asm/mach/arch.h> |
43 | #include <asm/mach/time.h> | 39 | #include <asm/mach/time.h> |
44 | 40 | ||
41 | #include "common.h" | ||
42 | #include "dma-register.h" | ||
43 | #include "irqs.h" | ||
44 | #include "sh73a0.h" | ||
45 | |||
45 | static struct map_desc sh73a0_io_desc[] __initdata = { | 46 | static struct map_desc sh73a0_io_desc[] __initdata = { |
46 | /* create a 1:1 entity map for 0xe6xxxxxx | 47 | /* create a 1:1 entity map for 0xe6xxxxxx |
47 | * used by CPGA, INTC and PFC. | 48 | * used by CPGA, INTC and PFC. |
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/sh7372.h index 854a9f0ca040..4ad960d5075b 100644 --- a/arch/arm/mach-shmobile/include/mach/sh7372.h +++ b/arch/arm/mach-shmobile/sh7372.h | |||
@@ -11,10 +11,6 @@ | |||
11 | #ifndef __ASM_SH7372_H__ | 11 | #ifndef __ASM_SH7372_H__ |
12 | #define __ASM_SH7372_H__ | 12 | #define __ASM_SH7372_H__ |
13 | 13 | ||
14 | #include <linux/sh_clk.h> | ||
15 | #include <linux/pm_domain.h> | ||
16 | #include <mach/pm-rmobile.h> | ||
17 | |||
18 | /* DMA slave IDs */ | 14 | /* DMA slave IDs */ |
19 | enum { | 15 | enum { |
20 | SHDMA_SLAVE_INVALID, | 16 | SHDMA_SLAVE_INVALID, |
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h index 359b582dc270..359b582dc270 100644 --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h +++ b/arch/arm/mach-shmobile/sh73a0.h | |||
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c index 2dfd748da7f3..6ff1df1df9a7 100644 --- a/arch/arm/mach-shmobile/smp-emev2.c +++ b/arch/arm/mach-shmobile/smp-emev2.c | |||
@@ -23,9 +23,9 @@ | |||
23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
26 | #include <mach/common.h> | ||
27 | #include <asm/smp_plat.h> | 26 | #include <asm/smp_plat.h> |
28 | #include <asm/smp_scu.h> | 27 | #include <asm/smp_scu.h> |
28 | #include "common.h" | ||
29 | 29 | ||
30 | #define EMEV2_SCU_BASE 0x1e000000 | 30 | #define EMEV2_SCU_BASE 0x1e000000 |
31 | #define EMEV2_SMU_BASE 0xe0110000 | 31 | #define EMEV2_SMU_BASE 0xe0110000 |
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c index e7a3201473d0..c230fc0c3fef 100644 --- a/arch/arm/mach-shmobile/smp-r8a7779.c +++ b/arch/arm/mach-shmobile/smp-r8a7779.c | |||
@@ -23,13 +23,13 @@ | |||
23 | #include <linux/spinlock.h> | 23 | #include <linux/spinlock.h> |
24 | #include <linux/io.h> | 24 | #include <linux/io.h> |
25 | #include <linux/delay.h> | 25 | #include <linux/delay.h> |
26 | #include <mach/common.h> | ||
27 | #include <mach/pm-rcar.h> | ||
28 | #include <mach/r8a7779.h> | 26 | #include <mach/r8a7779.h> |
29 | #include <asm/cacheflush.h> | 27 | #include <asm/cacheflush.h> |
30 | #include <asm/smp_plat.h> | 28 | #include <asm/smp_plat.h> |
31 | #include <asm/smp_scu.h> | 29 | #include <asm/smp_scu.h> |
32 | #include <asm/smp_twd.h> | 30 | #include <asm/smp_twd.h> |
31 | #include "common.h" | ||
32 | #include "pm-rcar.h" | ||
33 | 33 | ||
34 | #define AVECR IOMEM(0xfe700040) | 34 | #define AVECR IOMEM(0xfe700040) |
35 | #define R8A7779_SCU_BASE 0xf0000000 | 35 | #define R8A7779_SCU_BASE 0xf0000000 |
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c index 591052799e8f..c256fdfbb5b0 100644 --- a/arch/arm/mach-shmobile/smp-r8a7790.c +++ b/arch/arm/mach-shmobile/smp-r8a7790.c | |||
@@ -17,10 +17,12 @@ | |||
17 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | #include <linux/smp.h> | 18 | #include <linux/smp.h> |
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | |||
20 | #include <asm/smp_plat.h> | 21 | #include <asm/smp_plat.h> |
21 | #include <mach/common.h> | 22 | |
22 | #include <mach/pm-rcar.h> | 23 | #include "common.h" |
23 | #include <mach/r8a7790.h> | 24 | #include "pm-rcar.h" |
25 | #include "r8a7790.h" | ||
24 | 26 | ||
25 | #define RST 0xe6160000 | 27 | #define RST 0xe6160000 |
26 | #define CA15BAR 0x0020 | 28 | #define CA15BAR 0x0020 |
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c index ec979529f30f..2648d68650e4 100644 --- a/arch/arm/mach-shmobile/smp-r8a7791.c +++ b/arch/arm/mach-shmobile/smp-r8a7791.c | |||
@@ -18,9 +18,9 @@ | |||
18 | #include <linux/smp.h> | 18 | #include <linux/smp.h> |
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <asm/smp_plat.h> | 20 | #include <asm/smp_plat.h> |
21 | #include <mach/common.h> | ||
22 | #include <mach/r8a7791.h> | 21 | #include <mach/r8a7791.h> |
23 | #include <mach/rcar-gen2.h> | 22 | #include "common.h" |
23 | #include "rcar-gen2.h" | ||
24 | 24 | ||
25 | #define RST 0xe6160000 | 25 | #define RST 0xe6160000 |
26 | #define CA15BAR 0x0020 | 26 | #define CA15BAR 0x0020 |
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c index 13ba36a6831f..22d8f87b23e9 100644 --- a/arch/arm/mach-shmobile/smp-sh73a0.c +++ b/arch/arm/mach-shmobile/smp-sh73a0.c | |||
@@ -22,11 +22,13 @@ | |||
22 | #include <linux/smp.h> | 22 | #include <linux/smp.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/delay.h> | 24 | #include <linux/delay.h> |
25 | #include <mach/common.h> | 25 | |
26 | #include <mach/sh73a0.h> | ||
27 | #include <asm/smp_plat.h> | 26 | #include <asm/smp_plat.h> |
28 | #include <asm/smp_twd.h> | 27 | #include <asm/smp_twd.h> |
29 | 28 | ||
29 | #include "common.h" | ||
30 | #include "sh73a0.h" | ||
31 | |||
30 | #define WUPCR IOMEM(0xe6151010) | 32 | #define WUPCR IOMEM(0xe6151010) |
31 | #define SRESCR IOMEM(0xe6151018) | 33 | #define SRESCR IOMEM(0xe6151018) |
32 | #define PSTR IOMEM(0xe6151040) | 34 | #define PSTR IOMEM(0xe6151040) |
diff --git a/arch/arm/mach-spear/spear1310.c b/arch/arm/mach-spear/spear1310.c index 824b12a56a42..d9ce4d8000f0 100644 --- a/arch/arm/mach-spear/spear1310.c +++ b/arch/arm/mach-spear/spear1310.c | |||
@@ -42,7 +42,7 @@ static const char * const spear1310_dt_board_compat[] = { | |||
42 | * PHYSICAL VIRTUAL | 42 | * PHYSICAL VIRTUAL |
43 | * 0xD8000000 0xFA000000 | 43 | * 0xD8000000 0xFA000000 |
44 | */ | 44 | */ |
45 | struct map_desc spear1310_io_desc[] __initdata = { | 45 | static struct map_desc spear1310_io_desc[] __initdata = { |
46 | { | 46 | { |
47 | .virtual = VA_SPEAR1310_RAS_GRP1_BASE, | 47 | .virtual = VA_SPEAR1310_RAS_GRP1_BASE, |
48 | .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE), | 48 | .pfn = __phys_to_pfn(SPEAR1310_RAS_GRP1_BASE), |
diff --git a/arch/arm/mach-spear/spear1340.c b/arch/arm/mach-spear/spear1340.c index 7b6bff7154e1..c601799b4aea 100644 --- a/arch/arm/mach-spear/spear1340.c +++ b/arch/arm/mach-spear/spear1340.c | |||
@@ -93,7 +93,7 @@ static int sata_miphy_init(struct device *dev, void __iomem *addr) | |||
93 | return 0; | 93 | return 0; |
94 | } | 94 | } |
95 | 95 | ||
96 | void sata_miphy_exit(struct device *dev) | 96 | static void sata_miphy_exit(struct device *dev) |
97 | { | 97 | { |
98 | writel(0, SPEAR1340_PCIE_SATA_CFG); | 98 | writel(0, SPEAR1340_PCIE_SATA_CFG); |
99 | writel(0, SPEAR1340_PCIE_MIPHY_CFG); | 99 | writel(0, SPEAR1340_PCIE_MIPHY_CFG); |
@@ -107,7 +107,7 @@ void sata_miphy_exit(struct device *dev) | |||
107 | msleep(20); | 107 | msleep(20); |
108 | } | 108 | } |
109 | 109 | ||
110 | int sata_suspend(struct device *dev) | 110 | static int sata_suspend(struct device *dev) |
111 | { | 111 | { |
112 | if (dev->power.power_state.event == PM_EVENT_FREEZE) | 112 | if (dev->power.power_state.event == PM_EVENT_FREEZE) |
113 | return 0; | 113 | return 0; |
@@ -117,7 +117,7 @@ int sata_suspend(struct device *dev) | |||
117 | return 0; | 117 | return 0; |
118 | } | 118 | } |
119 | 119 | ||
120 | int sata_resume(struct device *dev) | 120 | static int sata_resume(struct device *dev) |
121 | { | 121 | { |
122 | if (dev->power.power_state.event == PM_EVENT_THAW) | 122 | if (dev->power.power_state.event == PM_EVENT_THAW) |
123 | return 0; | 123 | return 0; |
diff --git a/arch/arm/mach-spear/spear13xx.c b/arch/arm/mach-spear/spear13xx.c index c9897ea38980..8b56fe61a492 100644 --- a/arch/arm/mach-spear/spear13xx.c +++ b/arch/arm/mach-spear/spear13xx.c | |||
@@ -57,7 +57,7 @@ void __init spear13xx_l2x0_init(void) | |||
57 | * 0xEC000000 0xFC000000 | 57 | * 0xEC000000 0xFC000000 |
58 | * 0xED000000 0xFB000000 | 58 | * 0xED000000 0xFB000000 |
59 | */ | 59 | */ |
60 | struct map_desc spear13xx_io_desc[] __initdata = { | 60 | static struct map_desc spear13xx_io_desc[] __initdata = { |
61 | { | 61 | { |
62 | .virtual = (unsigned long)VA_PERIP_GRP2_BASE, | 62 | .virtual = (unsigned long)VA_PERIP_GRP2_BASE, |
63 | .pfn = __phys_to_pfn(PERIP_GRP2_BASE), | 63 | .pfn = __phys_to_pfn(PERIP_GRP2_BASE), |
diff --git a/arch/arm/mach-sti/platsmp.c b/arch/arm/mach-sti/platsmp.c index fa2c33ffac04..d4b624f8dfcb 100644 --- a/arch/arm/mach-sti/platsmp.c +++ b/arch/arm/mach-sti/platsmp.c | |||
@@ -36,7 +36,7 @@ static void write_pen_release(int val) | |||
36 | 36 | ||
37 | static DEFINE_SPINLOCK(boot_lock); | 37 | static DEFINE_SPINLOCK(boot_lock); |
38 | 38 | ||
39 | void sti_secondary_init(unsigned int cpu) | 39 | static void sti_secondary_init(unsigned int cpu) |
40 | { | 40 | { |
41 | trace_hardirqs_off(); | 41 | trace_hardirqs_off(); |
42 | 42 | ||
@@ -53,7 +53,7 @@ void sti_secondary_init(unsigned int cpu) | |||
53 | spin_unlock(&boot_lock); | 53 | spin_unlock(&boot_lock); |
54 | } | 54 | } |
55 | 55 | ||
56 | int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) | 56 | static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) |
57 | { | 57 | { |
58 | unsigned long timeout; | 58 | unsigned long timeout; |
59 | 59 | ||
@@ -97,7 +97,7 @@ int sti_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
97 | return pen_release != -1 ? -ENOSYS : 0; | 97 | return pen_release != -1 ? -ENOSYS : 0; |
98 | } | 98 | } |
99 | 99 | ||
100 | void __init sti_smp_prepare_cpus(unsigned int max_cpus) | 100 | static void __init sti_smp_prepare_cpus(unsigned int max_cpus) |
101 | { | 101 | { |
102 | void __iomem *scu_base = NULL; | 102 | void __iomem *scu_base = NULL; |
103 | struct device_node *np = of_find_compatible_node( | 103 | struct device_node *np = of_find_compatible_node( |
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile index 6fbfbb77dcd9..e48a74458c25 100644 --- a/arch/arm/mach-tegra/Makefile +++ b/arch/arm/mach-tegra/Makefile | |||
@@ -2,24 +2,18 @@ asflags-y += -march=armv7-a | |||
2 | 2 | ||
3 | obj-y += io.o | 3 | obj-y += io.o |
4 | obj-y += irq.o | 4 | obj-y += irq.o |
5 | obj-y += fuse.o | ||
6 | obj-y += pmc.o | ||
7 | obj-y += flowctrl.o | 5 | obj-y += flowctrl.o |
8 | obj-y += powergate.o | ||
9 | obj-y += apbio.o | ||
10 | obj-y += pm.o | 6 | obj-y += pm.o |
11 | obj-y += reset.o | 7 | obj-y += reset.o |
12 | obj-y += reset-handler.o | 8 | obj-y += reset-handler.o |
13 | obj-y += sleep.o | 9 | obj-y += sleep.o |
14 | obj-y += tegra.o | 10 | obj-y += tegra.o |
15 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o | 11 | obj-$(CONFIG_CPU_IDLE) += cpuidle.o |
16 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_speedo.o | ||
17 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o | 12 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-tegra20.o |
18 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o | 13 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += pm-tegra20.o |
19 | ifeq ($(CONFIG_CPU_IDLE),y) | 14 | ifeq ($(CONFIG_CPU_IDLE),y) |
20 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o | 15 | obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += cpuidle-tegra20.o |
21 | endif | 16 | endif |
22 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_speedo.o | ||
23 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o | 17 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-tegra30.o |
24 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o | 18 | obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pm-tegra30.o |
25 | ifeq ($(CONFIG_CPU_IDLE),y) | 19 | ifeq ($(CONFIG_CPU_IDLE),y) |
@@ -28,7 +22,6 @@ endif | |||
28 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o | 22 | obj-$(CONFIG_SMP) += platsmp.o headsmp.o |
29 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o | 23 | obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o |
30 | 24 | ||
31 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o | ||
32 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o | 25 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o |
33 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o | 26 | obj-$(CONFIG_ARCH_TEGRA_114_SOC) += pm-tegra30.o |
34 | ifeq ($(CONFIG_CPU_IDLE),y) | 27 | ifeq ($(CONFIG_CPU_IDLE),y) |
diff --git a/arch/arm/mach-tegra/apbio.c b/arch/arm/mach-tegra/apbio.c deleted file mode 100644 index bc471973cf04..000000000000 --- a/arch/arm/mach-tegra/apbio.c +++ /dev/null | |||
@@ -1,206 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 NVIDIA Corporation. | ||
3 | * Copyright (C) 2010 Google, Inc. | ||
4 | * | ||
5 | * This software is licensed under the terms of the GNU General Public | ||
6 | * License version 2, as published by the Free Software Foundation, and | ||
7 | * may be copied, distributed, and modified under those terms. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #include <linux/kernel.h> | ||
17 | #include <linux/io.h> | ||
18 | #include <linux/of.h> | ||
19 | #include <linux/dmaengine.h> | ||
20 | #include <linux/dma-mapping.h> | ||
21 | #include <linux/spinlock.h> | ||
22 | #include <linux/completion.h> | ||
23 | #include <linux/sched.h> | ||
24 | #include <linux/mutex.h> | ||
25 | |||
26 | #include "apbio.h" | ||
27 | #include "iomap.h" | ||
28 | |||
29 | #if defined(CONFIG_TEGRA20_APB_DMA) | ||
30 | static DEFINE_MUTEX(tegra_apb_dma_lock); | ||
31 | static u32 *tegra_apb_bb; | ||
32 | static dma_addr_t tegra_apb_bb_phys; | ||
33 | static DECLARE_COMPLETION(tegra_apb_wait); | ||
34 | |||
35 | static u32 tegra_apb_readl_direct(unsigned long offset); | ||
36 | static void tegra_apb_writel_direct(u32 value, unsigned long offset); | ||
37 | |||
38 | static struct dma_chan *tegra_apb_dma_chan; | ||
39 | static struct dma_slave_config dma_sconfig; | ||
40 | |||
41 | static bool tegra_apb_dma_init(void) | ||
42 | { | ||
43 | dma_cap_mask_t mask; | ||
44 | |||
45 | mutex_lock(&tegra_apb_dma_lock); | ||
46 | |||
47 | /* Check to see if we raced to setup */ | ||
48 | if (tegra_apb_dma_chan) | ||
49 | goto skip_init; | ||
50 | |||
51 | dma_cap_zero(mask); | ||
52 | dma_cap_set(DMA_SLAVE, mask); | ||
53 | tegra_apb_dma_chan = dma_request_channel(mask, NULL, NULL); | ||
54 | if (!tegra_apb_dma_chan) { | ||
55 | /* | ||
56 | * This is common until the device is probed, so don't | ||
57 | * shout about it. | ||
58 | */ | ||
59 | pr_debug("%s: can not allocate dma channel\n", __func__); | ||
60 | goto err_dma_alloc; | ||
61 | } | ||
62 | |||
63 | tegra_apb_bb = dma_alloc_coherent(NULL, sizeof(u32), | ||
64 | &tegra_apb_bb_phys, GFP_KERNEL); | ||
65 | if (!tegra_apb_bb) { | ||
66 | pr_err("%s: can not allocate bounce buffer\n", __func__); | ||
67 | goto err_buff_alloc; | ||
68 | } | ||
69 | |||
70 | dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
71 | dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; | ||
72 | dma_sconfig.src_maxburst = 1; | ||
73 | dma_sconfig.dst_maxburst = 1; | ||
74 | |||
75 | skip_init: | ||
76 | mutex_unlock(&tegra_apb_dma_lock); | ||
77 | return true; | ||
78 | |||
79 | err_buff_alloc: | ||
80 | dma_release_channel(tegra_apb_dma_chan); | ||
81 | tegra_apb_dma_chan = NULL; | ||
82 | |||
83 | err_dma_alloc: | ||
84 | mutex_unlock(&tegra_apb_dma_lock); | ||
85 | return false; | ||
86 | } | ||
87 | |||
88 | static void apb_dma_complete(void *args) | ||
89 | { | ||
90 | complete(&tegra_apb_wait); | ||
91 | } | ||
92 | |||
93 | static int do_dma_transfer(unsigned long apb_add, | ||
94 | enum dma_transfer_direction dir) | ||
95 | { | ||
96 | struct dma_async_tx_descriptor *dma_desc; | ||
97 | int ret; | ||
98 | |||
99 | if (dir == DMA_DEV_TO_MEM) | ||
100 | dma_sconfig.src_addr = apb_add; | ||
101 | else | ||
102 | dma_sconfig.dst_addr = apb_add; | ||
103 | |||
104 | ret = dmaengine_slave_config(tegra_apb_dma_chan, &dma_sconfig); | ||
105 | if (ret) | ||
106 | return ret; | ||
107 | |||
108 | dma_desc = dmaengine_prep_slave_single(tegra_apb_dma_chan, | ||
109 | tegra_apb_bb_phys, sizeof(u32), dir, | ||
110 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | ||
111 | if (!dma_desc) | ||
112 | return -EINVAL; | ||
113 | |||
114 | dma_desc->callback = apb_dma_complete; | ||
115 | dma_desc->callback_param = NULL; | ||
116 | |||
117 | reinit_completion(&tegra_apb_wait); | ||
118 | |||
119 | dmaengine_submit(dma_desc); | ||
120 | dma_async_issue_pending(tegra_apb_dma_chan); | ||
121 | ret = wait_for_completion_timeout(&tegra_apb_wait, | ||
122 | msecs_to_jiffies(50)); | ||
123 | |||
124 | if (WARN(ret == 0, "apb read dma timed out")) { | ||
125 | dmaengine_terminate_all(tegra_apb_dma_chan); | ||
126 | return -EFAULT; | ||
127 | } | ||
128 | return 0; | ||
129 | } | ||
130 | |||
131 | static u32 tegra_apb_readl_using_dma(unsigned long offset) | ||
132 | { | ||
133 | int ret; | ||
134 | |||
135 | if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) | ||
136 | return tegra_apb_readl_direct(offset); | ||
137 | |||
138 | mutex_lock(&tegra_apb_dma_lock); | ||
139 | ret = do_dma_transfer(offset, DMA_DEV_TO_MEM); | ||
140 | if (ret < 0) { | ||
141 | pr_err("error in reading offset 0x%08lx using dma\n", offset); | ||
142 | *(u32 *)tegra_apb_bb = 0; | ||
143 | } | ||
144 | mutex_unlock(&tegra_apb_dma_lock); | ||
145 | return *((u32 *)tegra_apb_bb); | ||
146 | } | ||
147 | |||
148 | static void tegra_apb_writel_using_dma(u32 value, unsigned long offset) | ||
149 | { | ||
150 | int ret; | ||
151 | |||
152 | if (!tegra_apb_dma_chan && !tegra_apb_dma_init()) { | ||
153 | tegra_apb_writel_direct(value, offset); | ||
154 | return; | ||
155 | } | ||
156 | |||
157 | mutex_lock(&tegra_apb_dma_lock); | ||
158 | *((u32 *)tegra_apb_bb) = value; | ||
159 | ret = do_dma_transfer(offset, DMA_MEM_TO_DEV); | ||
160 | if (ret < 0) | ||
161 | pr_err("error in writing offset 0x%08lx using dma\n", offset); | ||
162 | mutex_unlock(&tegra_apb_dma_lock); | ||
163 | } | ||
164 | #else | ||
165 | #define tegra_apb_readl_using_dma tegra_apb_readl_direct | ||
166 | #define tegra_apb_writel_using_dma tegra_apb_writel_direct | ||
167 | #endif | ||
168 | |||
169 | typedef u32 (*apbio_read_fptr)(unsigned long offset); | ||
170 | typedef void (*apbio_write_fptr)(u32 value, unsigned long offset); | ||
171 | |||
172 | static apbio_read_fptr apbio_read; | ||
173 | static apbio_write_fptr apbio_write; | ||
174 | |||
175 | static u32 tegra_apb_readl_direct(unsigned long offset) | ||
176 | { | ||
177 | return readl(IO_ADDRESS(offset)); | ||
178 | } | ||
179 | |||
180 | static void tegra_apb_writel_direct(u32 value, unsigned long offset) | ||
181 | { | ||
182 | writel(value, IO_ADDRESS(offset)); | ||
183 | } | ||
184 | |||
185 | void tegra_apb_io_init(void) | ||
186 | { | ||
187 | /* Need to use dma only when it is Tegra20 based platform */ | ||
188 | if (of_machine_is_compatible("nvidia,tegra20") || | ||
189 | !of_have_populated_dt()) { | ||
190 | apbio_read = tegra_apb_readl_using_dma; | ||
191 | apbio_write = tegra_apb_writel_using_dma; | ||
192 | } else { | ||
193 | apbio_read = tegra_apb_readl_direct; | ||
194 | apbio_write = tegra_apb_writel_direct; | ||
195 | } | ||
196 | } | ||
197 | |||
198 | u32 tegra_apb_readl(unsigned long offset) | ||
199 | { | ||
200 | return apbio_read(offset); | ||
201 | } | ||
202 | |||
203 | void tegra_apb_writel(u32 value, unsigned long offset) | ||
204 | { | ||
205 | apbio_write(value, offset); | ||
206 | } | ||
diff --git a/arch/arm/mach-tegra/apbio.h b/arch/arm/mach-tegra/apbio.h deleted file mode 100644 index f05d71c303c7..000000000000 --- a/arch/arm/mach-tegra/apbio.h +++ /dev/null | |||
@@ -1,22 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 NVIDIA Corporation. | ||
3 | * Copyright (C) 2010 Google, Inc. | ||
4 | * | ||
5 | * This software is licensed under the terms of the GNU General Public | ||
6 | * License version 2, as published by the Free Software Foundation, and | ||
7 | * may be copied, distributed, and modified under those terms. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | */ | ||
15 | |||
16 | #ifndef __MACH_TEGRA_APBIO_H | ||
17 | #define __MACH_TEGRA_APBIO_H | ||
18 | |||
19 | void tegra_apb_io_init(void); | ||
20 | u32 tegra_apb_readl(unsigned long offset); | ||
21 | void tegra_apb_writel(u32 value, unsigned long offset); | ||
22 | #endif | ||
diff --git a/arch/arm/mach-tegra/board-paz00.c b/arch/arm/mach-tegra/board-paz00.c index 9c6029ba526f..bb4782a32713 100644 --- a/arch/arm/mach-tegra/board-paz00.c +++ b/arch/arm/mach-tegra/board-paz00.c | |||
@@ -17,9 +17,10 @@ | |||
17 | * | 17 | * |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #include <linux/platform_device.h> | ||
21 | #include <linux/gpio/driver.h> | 20 | #include <linux/gpio/driver.h> |
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/rfkill-gpio.h> | 22 | #include <linux/rfkill-gpio.h> |
23 | |||
23 | #include "board.h" | 24 | #include "board.h" |
24 | 25 | ||
25 | static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { | 26 | static struct rfkill_gpio_platform_data wifi_rfkill_platform_data = { |
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h index bcf5dbf69d58..da90c89296b9 100644 --- a/arch/arm/mach-tegra/board.h +++ b/arch/arm/mach-tegra/board.h | |||
@@ -28,13 +28,6 @@ | |||
28 | void __init tegra_map_common_io(void); | 28 | void __init tegra_map_common_io(void); |
29 | void __init tegra_init_irq(void); | 29 | void __init tegra_init_irq(void); |
30 | 30 | ||
31 | int __init tegra_powergate_init(void); | ||
32 | #if defined(CONFIG_ARCH_TEGRA_2x_SOC) && defined(CONFIG_DEBUG_FS) | ||
33 | int __init tegra_powergate_debugfs_init(void); | ||
34 | #else | ||
35 | static inline int tegra_powergate_debugfs_init(void) { return 0; } | ||
36 | #endif | ||
37 | |||
38 | void __init tegra_paz00_wifikill_init(void); | 31 | void __init tegra_paz00_wifikill_init(void); |
39 | 32 | ||
40 | #endif | 33 | #endif |
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c index b5fb7c110c64..e3ebdce3e71f 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra114.c +++ b/arch/arm/mach-tegra/cpuidle-tegra114.c | |||
@@ -14,16 +14,16 @@ | |||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/kernel.h> | 17 | #include <asm/firmware.h> |
18 | #include <linux/module.h> | 18 | #include <linux/clockchips.h> |
19 | #include <linux/cpuidle.h> | 19 | #include <linux/cpuidle.h> |
20 | #include <linux/cpu_pm.h> | 20 | #include <linux/cpu_pm.h> |
21 | #include <linux/clockchips.h> | 21 | #include <linux/kernel.h> |
22 | #include <asm/firmware.h> | 22 | #include <linux/module.h> |
23 | 23 | ||
24 | #include <asm/cpuidle.h> | 24 | #include <asm/cpuidle.h> |
25 | #include <asm/suspend.h> | ||
26 | #include <asm/smp_plat.h> | 25 | #include <asm/smp_plat.h> |
26 | #include <asm/suspend.h> | ||
27 | 27 | ||
28 | #include "pm.h" | 28 | #include "pm.h" |
29 | #include "sleep.h" | 29 | #include "sleep.h" |
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c index b82dcaee2ef4..b30bf5cba65b 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra20.c +++ b/arch/arm/mach-tegra/cpuidle-tegra20.c | |||
@@ -19,23 +19,23 @@ | |||
19 | * more details. | 19 | * more details. |
20 | */ | 20 | */ |
21 | 21 | ||
22 | #include <linux/kernel.h> | 22 | #include <linux/clk/tegra.h> |
23 | #include <linux/module.h> | 23 | #include <linux/clockchips.h> |
24 | #include <linux/cpuidle.h> | 24 | #include <linux/cpuidle.h> |
25 | #include <linux/cpu_pm.h> | 25 | #include <linux/cpu_pm.h> |
26 | #include <linux/clockchips.h> | 26 | #include <linux/kernel.h> |
27 | #include <linux/clk/tegra.h> | 27 | #include <linux/module.h> |
28 | 28 | ||
29 | #include <asm/cpuidle.h> | 29 | #include <asm/cpuidle.h> |
30 | #include <asm/proc-fns.h> | 30 | #include <asm/proc-fns.h> |
31 | #include <asm/suspend.h> | ||
32 | #include <asm/smp_plat.h> | 31 | #include <asm/smp_plat.h> |
32 | #include <asm/suspend.h> | ||
33 | 33 | ||
34 | #include "pm.h" | 34 | #include "flowctrl.h" |
35 | #include "sleep.h" | ||
36 | #include "iomap.h" | 35 | #include "iomap.h" |
37 | #include "irq.h" | 36 | #include "irq.h" |
38 | #include "flowctrl.h" | 37 | #include "pm.h" |
38 | #include "sleep.h" | ||
39 | 39 | ||
40 | #ifdef CONFIG_PM_SLEEP | 40 | #ifdef CONFIG_PM_SLEEP |
41 | static bool abort_flag; | 41 | static bool abort_flag; |
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c index ed2a2a7bae4d..35561274f6cf 100644 --- a/arch/arm/mach-tegra/cpuidle-tegra30.c +++ b/arch/arm/mach-tegra/cpuidle-tegra30.c | |||
@@ -19,17 +19,17 @@ | |||
19 | * more details. | 19 | * more details. |
20 | */ | 20 | */ |
21 | 21 | ||
22 | #include <linux/kernel.h> | 22 | #include <linux/clk/tegra.h> |
23 | #include <linux/module.h> | 23 | #include <linux/clockchips.h> |
24 | #include <linux/cpuidle.h> | 24 | #include <linux/cpuidle.h> |
25 | #include <linux/cpu_pm.h> | 25 | #include <linux/cpu_pm.h> |
26 | #include <linux/clockchips.h> | 26 | #include <linux/kernel.h> |
27 | #include <linux/clk/tegra.h> | 27 | #include <linux/module.h> |
28 | 28 | ||
29 | #include <asm/cpuidle.h> | 29 | #include <asm/cpuidle.h> |
30 | #include <asm/proc-fns.h> | 30 | #include <asm/proc-fns.h> |
31 | #include <asm/suspend.h> | ||
32 | #include <asm/smp_plat.h> | 31 | #include <asm/smp_plat.h> |
32 | #include <asm/suspend.h> | ||
33 | 33 | ||
34 | #include "pm.h" | 34 | #include "pm.h" |
35 | #include "sleep.h" | 35 | #include "sleep.h" |
diff --git a/arch/arm/mach-tegra/cpuidle.c b/arch/arm/mach-tegra/cpuidle.c index 7bc5d8d667fe..316563141add 100644 --- a/arch/arm/mach-tegra/cpuidle.c +++ b/arch/arm/mach-tegra/cpuidle.c | |||
@@ -24,12 +24,13 @@ | |||
24 | #include <linux/kernel.h> | 24 | #include <linux/kernel.h> |
25 | #include <linux/module.h> | 25 | #include <linux/module.h> |
26 | 26 | ||
27 | #include "fuse.h" | 27 | #include <soc/tegra/fuse.h> |
28 | |||
28 | #include "cpuidle.h" | 29 | #include "cpuidle.h" |
29 | 30 | ||
30 | void __init tegra_cpuidle_init(void) | 31 | void __init tegra_cpuidle_init(void) |
31 | { | 32 | { |
32 | switch (tegra_chip_id) { | 33 | switch (tegra_get_chip_id()) { |
33 | case TEGRA20: | 34 | case TEGRA20: |
34 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | 35 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
35 | tegra20_cpuidle_init(); | 36 | tegra20_cpuidle_init(); |
@@ -49,7 +50,7 @@ void __init tegra_cpuidle_init(void) | |||
49 | 50 | ||
50 | void tegra_cpuidle_pcie_irqs_in_use(void) | 51 | void tegra_cpuidle_pcie_irqs_in_use(void) |
51 | { | 52 | { |
52 | switch (tegra_chip_id) { | 53 | switch (tegra_get_chip_id()) { |
53 | case TEGRA20: | 54 | case TEGRA20: |
54 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | 55 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
55 | tegra20_cpuidle_pcie_irqs_in_use(); | 56 | tegra20_cpuidle_pcie_irqs_in_use(); |
diff --git a/arch/arm/mach-tegra/flowctrl.c b/arch/arm/mach-tegra/flowctrl.c index ce8ab8abf061..ec55d1de1b55 100644 --- a/arch/arm/mach-tegra/flowctrl.c +++ b/arch/arm/mach-tegra/flowctrl.c | |||
@@ -18,14 +18,15 @@ | |||
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/cpumask.h> | ||
21 | #include <linux/init.h> | 22 | #include <linux/init.h> |
22 | #include <linux/kernel.h> | ||
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/cpumask.h> | 24 | #include <linux/kernel.h> |
25 | |||
26 | #include <soc/tegra/fuse.h> | ||
25 | 27 | ||
26 | #include "flowctrl.h" | 28 | #include "flowctrl.h" |
27 | #include "iomap.h" | 29 | #include "iomap.h" |
28 | #include "fuse.h" | ||
29 | 30 | ||
30 | static u8 flowctrl_offset_halt_cpu[] = { | 31 | static u8 flowctrl_offset_halt_cpu[] = { |
31 | FLOW_CTRL_HALT_CPU0_EVENTS, | 32 | FLOW_CTRL_HALT_CPU0_EVENTS, |
@@ -76,7 +77,7 @@ void flowctrl_cpu_suspend_enter(unsigned int cpuid) | |||
76 | int i; | 77 | int i; |
77 | 78 | ||
78 | reg = flowctrl_read_cpu_csr(cpuid); | 79 | reg = flowctrl_read_cpu_csr(cpuid); |
79 | switch (tegra_chip_id) { | 80 | switch (tegra_get_chip_id()) { |
80 | case TEGRA20: | 81 | case TEGRA20: |
81 | /* clear wfe bitmap */ | 82 | /* clear wfe bitmap */ |
82 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; | 83 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; |
@@ -117,7 +118,7 @@ void flowctrl_cpu_suspend_exit(unsigned int cpuid) | |||
117 | 118 | ||
118 | /* Disable powergating via flow controller for CPU0 */ | 119 | /* Disable powergating via flow controller for CPU0 */ |
119 | reg = flowctrl_read_cpu_csr(cpuid); | 120 | reg = flowctrl_read_cpu_csr(cpuid); |
120 | switch (tegra_chip_id) { | 121 | switch (tegra_get_chip_id()) { |
121 | case TEGRA20: | 122 | case TEGRA20: |
122 | /* clear wfe bitmap */ | 123 | /* clear wfe bitmap */ |
123 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; | 124 | reg &= ~TEGRA20_FLOW_CTRL_CSR_WFE_BITMAP; |
diff --git a/arch/arm/mach-tegra/fuse.c b/arch/arm/mach-tegra/fuse.c deleted file mode 100644 index c9ac23b385be..000000000000 --- a/arch/arm/mach-tegra/fuse.c +++ /dev/null | |||
@@ -1,252 +0,0 @@ | |||
1 | /* | ||
2 | * arch/arm/mach-tegra/fuse.c | ||
3 | * | ||
4 | * Copyright (C) 2010 Google, Inc. | ||
5 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
6 | * | ||
7 | * Author: | ||
8 | * Colin Cross <ccross@android.com> | ||
9 | * | ||
10 | * This software is licensed under the terms of the GNU General Public | ||
11 | * License version 2, as published by the Free Software Foundation, and | ||
12 | * may be copied, distributed, and modified under those terms. | ||
13 | * | ||
14 | * This program is distributed in the hope that it will be useful, | ||
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
17 | * GNU General Public License for more details. | ||
18 | * | ||
19 | */ | ||
20 | |||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/io.h> | ||
23 | #include <linux/export.h> | ||
24 | #include <linux/random.h> | ||
25 | #include <linux/clk.h> | ||
26 | #include <linux/tegra-soc.h> | ||
27 | |||
28 | #include "fuse.h" | ||
29 | #include "iomap.h" | ||
30 | #include "apbio.h" | ||
31 | |||
32 | /* Tegra20 only */ | ||
33 | #define FUSE_UID_LOW 0x108 | ||
34 | #define FUSE_UID_HIGH 0x10c | ||
35 | |||
36 | /* Tegra30 and later */ | ||
37 | #define FUSE_VENDOR_CODE 0x200 | ||
38 | #define FUSE_FAB_CODE 0x204 | ||
39 | #define FUSE_LOT_CODE_0 0x208 | ||
40 | #define FUSE_LOT_CODE_1 0x20c | ||
41 | #define FUSE_WAFER_ID 0x210 | ||
42 | #define FUSE_X_COORDINATE 0x214 | ||
43 | #define FUSE_Y_COORDINATE 0x218 | ||
44 | |||
45 | #define FUSE_SKU_INFO 0x110 | ||
46 | |||
47 | #define TEGRA20_FUSE_SPARE_BIT 0x200 | ||
48 | #define TEGRA30_FUSE_SPARE_BIT 0x244 | ||
49 | |||
50 | int tegra_sku_id; | ||
51 | int tegra_cpu_process_id; | ||
52 | int tegra_core_process_id; | ||
53 | int tegra_chip_id; | ||
54 | int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ | ||
55 | int tegra_soc_speedo_id; | ||
56 | enum tegra_revision tegra_revision; | ||
57 | |||
58 | static struct clk *fuse_clk; | ||
59 | static int tegra_fuse_spare_bit; | ||
60 | static void (*tegra_init_speedo_data)(void); | ||
61 | |||
62 | /* The BCT to use at boot is specified by board straps that can be read | ||
63 | * through a APB misc register and decoded. 2 bits, i.e. 4 possible BCTs. | ||
64 | */ | ||
65 | int tegra_bct_strapping; | ||
66 | |||
67 | #define STRAP_OPT 0x008 | ||
68 | #define GMI_AD0 (1 << 4) | ||
69 | #define GMI_AD1 (1 << 5) | ||
70 | #define RAM_ID_MASK (GMI_AD0 | GMI_AD1) | ||
71 | #define RAM_CODE_SHIFT 4 | ||
72 | |||
73 | static const char *tegra_revision_name[TEGRA_REVISION_MAX] = { | ||
74 | [TEGRA_REVISION_UNKNOWN] = "unknown", | ||
75 | [TEGRA_REVISION_A01] = "A01", | ||
76 | [TEGRA_REVISION_A02] = "A02", | ||
77 | [TEGRA_REVISION_A03] = "A03", | ||
78 | [TEGRA_REVISION_A03p] = "A03 prime", | ||
79 | [TEGRA_REVISION_A04] = "A04", | ||
80 | }; | ||
81 | |||
82 | static void tegra_fuse_enable_clk(void) | ||
83 | { | ||
84 | if (IS_ERR(fuse_clk)) | ||
85 | fuse_clk = clk_get_sys(NULL, "fuse"); | ||
86 | if (IS_ERR(fuse_clk)) | ||
87 | return; | ||
88 | clk_prepare_enable(fuse_clk); | ||
89 | } | ||
90 | |||
91 | static void tegra_fuse_disable_clk(void) | ||
92 | { | ||
93 | if (IS_ERR(fuse_clk)) | ||
94 | return; | ||
95 | clk_disable_unprepare(fuse_clk); | ||
96 | } | ||
97 | |||
98 | u32 tegra_fuse_readl(unsigned long offset) | ||
99 | { | ||
100 | return tegra_apb_readl(TEGRA_FUSE_BASE + offset); | ||
101 | } | ||
102 | |||
103 | bool tegra_spare_fuse(int bit) | ||
104 | { | ||
105 | bool ret; | ||
106 | |||
107 | tegra_fuse_enable_clk(); | ||
108 | |||
109 | ret = tegra_fuse_readl(tegra_fuse_spare_bit + bit * 4); | ||
110 | |||
111 | tegra_fuse_disable_clk(); | ||
112 | |||
113 | return ret; | ||
114 | } | ||
115 | |||
116 | static enum tegra_revision tegra_get_revision(u32 id) | ||
117 | { | ||
118 | u32 minor_rev = (id >> 16) & 0xf; | ||
119 | |||
120 | switch (minor_rev) { | ||
121 | case 1: | ||
122 | return TEGRA_REVISION_A01; | ||
123 | case 2: | ||
124 | return TEGRA_REVISION_A02; | ||
125 | case 3: | ||
126 | if (tegra_chip_id == TEGRA20 && | ||
127 | (tegra_spare_fuse(18) || tegra_spare_fuse(19))) | ||
128 | return TEGRA_REVISION_A03p; | ||
129 | else | ||
130 | return TEGRA_REVISION_A03; | ||
131 | case 4: | ||
132 | return TEGRA_REVISION_A04; | ||
133 | default: | ||
134 | return TEGRA_REVISION_UNKNOWN; | ||
135 | } | ||
136 | } | ||
137 | |||
138 | static void tegra_get_process_id(void) | ||
139 | { | ||
140 | u32 reg; | ||
141 | |||
142 | tegra_fuse_enable_clk(); | ||
143 | |||
144 | reg = tegra_fuse_readl(tegra_fuse_spare_bit); | ||
145 | tegra_cpu_process_id = (reg >> 6) & 3; | ||
146 | reg = tegra_fuse_readl(tegra_fuse_spare_bit); | ||
147 | tegra_core_process_id = (reg >> 12) & 3; | ||
148 | |||
149 | tegra_fuse_disable_clk(); | ||
150 | } | ||
151 | |||
152 | u32 tegra_read_chipid(void) | ||
153 | { | ||
154 | return readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804); | ||
155 | } | ||
156 | |||
157 | static void __init tegra20_fuse_init_randomness(void) | ||
158 | { | ||
159 | u32 randomness[2]; | ||
160 | |||
161 | randomness[0] = tegra_fuse_readl(FUSE_UID_LOW); | ||
162 | randomness[1] = tegra_fuse_readl(FUSE_UID_HIGH); | ||
163 | |||
164 | add_device_randomness(randomness, sizeof(randomness)); | ||
165 | } | ||
166 | |||
167 | /* Applies to Tegra30 or later */ | ||
168 | static void __init tegra30_fuse_init_randomness(void) | ||
169 | { | ||
170 | u32 randomness[7]; | ||
171 | |||
172 | randomness[0] = tegra_fuse_readl(FUSE_VENDOR_CODE); | ||
173 | randomness[1] = tegra_fuse_readl(FUSE_FAB_CODE); | ||
174 | randomness[2] = tegra_fuse_readl(FUSE_LOT_CODE_0); | ||
175 | randomness[3] = tegra_fuse_readl(FUSE_LOT_CODE_1); | ||
176 | randomness[4] = tegra_fuse_readl(FUSE_WAFER_ID); | ||
177 | randomness[5] = tegra_fuse_readl(FUSE_X_COORDINATE); | ||
178 | randomness[6] = tegra_fuse_readl(FUSE_Y_COORDINATE); | ||
179 | |||
180 | add_device_randomness(randomness, sizeof(randomness)); | ||
181 | } | ||
182 | |||
183 | void __init tegra_init_fuse(void) | ||
184 | { | ||
185 | u32 id; | ||
186 | u32 randomness[5]; | ||
187 | |||
188 | u32 reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); | ||
189 | reg |= 1 << 28; | ||
190 | writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x48)); | ||
191 | |||
192 | /* | ||
193 | * Enable FUSE clock. This needs to be hardcoded because the clock | ||
194 | * subsystem is not active during early boot. | ||
195 | */ | ||
196 | reg = readl(IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14)); | ||
197 | reg |= 1 << 7; | ||
198 | writel(reg, IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x14)); | ||
199 | fuse_clk = ERR_PTR(-EINVAL); | ||
200 | |||
201 | reg = tegra_fuse_readl(FUSE_SKU_INFO); | ||
202 | randomness[0] = reg; | ||
203 | tegra_sku_id = reg & 0xFF; | ||
204 | |||
205 | reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); | ||
206 | randomness[1] = reg; | ||
207 | tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; | ||
208 | |||
209 | id = tegra_read_chipid(); | ||
210 | randomness[2] = id; | ||
211 | tegra_chip_id = (id >> 8) & 0xff; | ||
212 | |||
213 | switch (tegra_chip_id) { | ||
214 | case TEGRA20: | ||
215 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; | ||
216 | tegra_init_speedo_data = &tegra20_init_speedo_data; | ||
217 | break; | ||
218 | case TEGRA30: | ||
219 | tegra_fuse_spare_bit = TEGRA30_FUSE_SPARE_BIT; | ||
220 | tegra_init_speedo_data = &tegra30_init_speedo_data; | ||
221 | break; | ||
222 | case TEGRA114: | ||
223 | tegra_init_speedo_data = &tegra114_init_speedo_data; | ||
224 | break; | ||
225 | default: | ||
226 | pr_warn("Tegra: unknown chip id %d\n", tegra_chip_id); | ||
227 | tegra_fuse_spare_bit = TEGRA20_FUSE_SPARE_BIT; | ||
228 | tegra_init_speedo_data = &tegra_get_process_id; | ||
229 | } | ||
230 | |||
231 | tegra_revision = tegra_get_revision(id); | ||
232 | tegra_init_speedo_data(); | ||
233 | randomness[3] = (tegra_cpu_process_id << 16) | tegra_core_process_id; | ||
234 | randomness[4] = (tegra_cpu_speedo_id << 16) | tegra_soc_speedo_id; | ||
235 | |||
236 | add_device_randomness(randomness, sizeof(randomness)); | ||
237 | switch (tegra_chip_id) { | ||
238 | case TEGRA20: | ||
239 | tegra20_fuse_init_randomness(); | ||
240 | break; | ||
241 | case TEGRA30: | ||
242 | case TEGRA114: | ||
243 | default: | ||
244 | tegra30_fuse_init_randomness(); | ||
245 | break; | ||
246 | } | ||
247 | |||
248 | pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", | ||
249 | tegra_revision_name[tegra_revision], | ||
250 | tegra_sku_id, tegra_cpu_process_id, | ||
251 | tegra_core_process_id); | ||
252 | } | ||
diff --git a/arch/arm/mach-tegra/fuse.h b/arch/arm/mach-tegra/fuse.h deleted file mode 100644 index c01d04785d67..000000000000 --- a/arch/arm/mach-tegra/fuse.h +++ /dev/null | |||
@@ -1,79 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2010 Google, Inc. | ||
3 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
4 | * | ||
5 | * Author: | ||
6 | * Colin Cross <ccross@android.com> | ||
7 | * | ||
8 | * This software is licensed under the terms of the GNU General Public | ||
9 | * License version 2, as published by the Free Software Foundation, and | ||
10 | * may be copied, distributed, and modified under those terms. | ||
11 | * | ||
12 | * This program is distributed in the hope that it will be useful, | ||
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
15 | * GNU General Public License for more details. | ||
16 | * | ||
17 | */ | ||
18 | |||
19 | #ifndef __MACH_TEGRA_FUSE_H | ||
20 | #define __MACH_TEGRA_FUSE_H | ||
21 | |||
22 | #define SKU_ID_T20 8 | ||
23 | #define SKU_ID_T25SE 20 | ||
24 | #define SKU_ID_AP25 23 | ||
25 | #define SKU_ID_T25 24 | ||
26 | #define SKU_ID_AP25E 27 | ||
27 | #define SKU_ID_T25E 28 | ||
28 | |||
29 | #define TEGRA20 0x20 | ||
30 | #define TEGRA30 0x30 | ||
31 | #define TEGRA114 0x35 | ||
32 | #define TEGRA124 0x40 | ||
33 | |||
34 | #ifndef __ASSEMBLY__ | ||
35 | enum tegra_revision { | ||
36 | TEGRA_REVISION_UNKNOWN = 0, | ||
37 | TEGRA_REVISION_A01, | ||
38 | TEGRA_REVISION_A02, | ||
39 | TEGRA_REVISION_A03, | ||
40 | TEGRA_REVISION_A03p, | ||
41 | TEGRA_REVISION_A04, | ||
42 | TEGRA_REVISION_MAX, | ||
43 | }; | ||
44 | |||
45 | extern int tegra_sku_id; | ||
46 | extern int tegra_cpu_process_id; | ||
47 | extern int tegra_core_process_id; | ||
48 | extern int tegra_chip_id; | ||
49 | extern int tegra_cpu_speedo_id; /* only exist in Tegra30 and later */ | ||
50 | extern int tegra_soc_speedo_id; | ||
51 | extern enum tegra_revision tegra_revision; | ||
52 | |||
53 | extern int tegra_bct_strapping; | ||
54 | |||
55 | unsigned long long tegra_chip_uid(void); | ||
56 | void tegra_init_fuse(void); | ||
57 | bool tegra_spare_fuse(int bit); | ||
58 | u32 tegra_fuse_readl(unsigned long offset); | ||
59 | |||
60 | #ifdef CONFIG_ARCH_TEGRA_2x_SOC | ||
61 | void tegra20_init_speedo_data(void); | ||
62 | #else | ||
63 | static inline void tegra20_init_speedo_data(void) {} | ||
64 | #endif | ||
65 | |||
66 | #ifdef CONFIG_ARCH_TEGRA_3x_SOC | ||
67 | void tegra30_init_speedo_data(void); | ||
68 | #else | ||
69 | static inline void tegra30_init_speedo_data(void) {} | ||
70 | #endif | ||
71 | |||
72 | #ifdef CONFIG_ARCH_TEGRA_114_SOC | ||
73 | void tegra114_init_speedo_data(void); | ||
74 | #else | ||
75 | static inline void tegra114_init_speedo_data(void) {} | ||
76 | #endif | ||
77 | #endif /* __ASSEMBLY__ */ | ||
78 | |||
79 | #endif | ||
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c index ff26af26bd0c..6fc71f1534b0 100644 --- a/arch/arm/mach-tegra/hotplug.c +++ b/arch/arm/mach-tegra/hotplug.c | |||
@@ -7,13 +7,16 @@ | |||
7 | * it under the terms of the GNU General Public License version 2 as | 7 | * it under the terms of the GNU General Public License version 2 as |
8 | * published by the Free Software Foundation. | 8 | * published by the Free Software Foundation. |
9 | */ | 9 | */ |
10 | |||
11 | #include <linux/clk/tegra.h> | ||
10 | #include <linux/kernel.h> | 12 | #include <linux/kernel.h> |
11 | #include <linux/smp.h> | 13 | #include <linux/smp.h> |
12 | #include <linux/clk/tegra.h> | 14 | |
15 | #include <soc/tegra/common.h> | ||
16 | #include <soc/tegra/fuse.h> | ||
13 | 17 | ||
14 | #include <asm/smp_plat.h> | 18 | #include <asm/smp_plat.h> |
15 | 19 | ||
16 | #include "fuse.h" | ||
17 | #include "sleep.h" | 20 | #include "sleep.h" |
18 | 21 | ||
19 | static void (*tegra_hotplug_shutdown)(void); | 22 | static void (*tegra_hotplug_shutdown)(void); |
@@ -36,6 +39,11 @@ int tegra_cpu_kill(unsigned cpu) | |||
36 | */ | 39 | */ |
37 | void __ref tegra_cpu_die(unsigned int cpu) | 40 | void __ref tegra_cpu_die(unsigned int cpu) |
38 | { | 41 | { |
42 | if (!tegra_hotplug_shutdown) { | ||
43 | WARN(1, "hotplug is not yet initialized\n"); | ||
44 | return; | ||
45 | } | ||
46 | |||
39 | /* Clean L1 data cache */ | 47 | /* Clean L1 data cache */ |
40 | tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); | 48 | tegra_disable_clean_inv_dcache(TEGRA_FLUSH_CACHE_LOUIS); |
41 | 49 | ||
@@ -46,17 +54,23 @@ void __ref tegra_cpu_die(unsigned int cpu) | |||
46 | BUG(); | 54 | BUG(); |
47 | } | 55 | } |
48 | 56 | ||
49 | void __init tegra_hotplug_init(void) | 57 | static int __init tegra_hotplug_init(void) |
50 | { | 58 | { |
51 | if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) | 59 | if (!IS_ENABLED(CONFIG_HOTPLUG_CPU)) |
52 | return; | 60 | return 0; |
53 | 61 | ||
54 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20) | 62 | if (!soc_is_tegra()) |
63 | return 0; | ||
64 | |||
65 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20) | ||
55 | tegra_hotplug_shutdown = tegra20_hotplug_shutdown; | 66 | tegra_hotplug_shutdown = tegra20_hotplug_shutdown; |
56 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) | 67 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30) |
57 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | 68 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; |
58 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) | 69 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114) |
59 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | 70 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; |
60 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124) | 71 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124) |
61 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; | 72 | tegra_hotplug_shutdown = tegra30_hotplug_shutdown; |
73 | |||
74 | return 0; | ||
62 | } | 75 | } |
76 | pure_initcall(tegra_hotplug_init); | ||
diff --git a/arch/arm/mach-tegra/io.c b/arch/arm/mach-tegra/io.c index bb9c9c29d181..352de159d2c5 100644 --- a/arch/arm/mach-tegra/io.c +++ b/arch/arm/mach-tegra/io.c | |||
@@ -18,14 +18,14 @@ | |||
18 | * | 18 | * |
19 | */ | 19 | */ |
20 | 20 | ||
21 | #include <linux/kernel.h> | ||
22 | #include <linux/module.h> | ||
23 | #include <linux/init.h> | 21 | #include <linux/init.h> |
24 | #include <linux/mm.h> | ||
25 | #include <linux/io.h> | 22 | #include <linux/io.h> |
23 | #include <linux/kernel.h> | ||
24 | #include <linux/mm.h> | ||
25 | #include <linux/module.h> | ||
26 | 26 | ||
27 | #include <asm/page.h> | ||
28 | #include <asm/mach/map.h> | 27 | #include <asm/mach/map.h> |
28 | #include <asm/page.h> | ||
29 | 29 | ||
30 | #include "board.h" | 30 | #include "board.h" |
31 | #include "iomap.h" | 31 | #include "iomap.h" |
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c index 1a74d562dca1..da7be13aecce 100644 --- a/arch/arm/mach-tegra/irq.c +++ b/arch/arm/mach-tegra/irq.c | |||
@@ -17,14 +17,14 @@ | |||
17 | * | 17 | * |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/cpu_pm.h> | 20 | #include <linux/cpu_pm.h> |
22 | #include <linux/interrupt.h> | 21 | #include <linux/interrupt.h> |
23 | #include <linux/irq.h> | ||
24 | #include <linux/io.h> | 22 | #include <linux/io.h> |
25 | #include <linux/of.h> | ||
26 | #include <linux/of_address.h> | ||
27 | #include <linux/irqchip/arm-gic.h> | 23 | #include <linux/irqchip/arm-gic.h> |
24 | #include <linux/irq.h> | ||
25 | #include <linux/kernel.h> | ||
26 | #include <linux/of_address.h> | ||
27 | #include <linux/of.h> | ||
28 | #include <linux/syscore_ops.h> | 28 | #include <linux/syscore_ops.h> |
29 | 29 | ||
30 | #include "board.h" | 30 | #include "board.h" |
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c index 929d1046e2b4..b45086666648 100644 --- a/arch/arm/mach-tegra/platsmp.c +++ b/arch/arm/mach-tegra/platsmp.c | |||
@@ -11,27 +11,28 @@ | |||
11 | * it under the terms of the GNU General Public License version 2 as | 11 | * it under the terms of the GNU General Public License version 2 as |
12 | * published by the Free Software Foundation. | 12 | * published by the Free Software Foundation. |
13 | */ | 13 | */ |
14 | #include <linux/init.h> | 14 | |
15 | #include <linux/errno.h> | 15 | #include <linux/clk/tegra.h> |
16 | #include <linux/delay.h> | 16 | #include <linux/delay.h> |
17 | #include <linux/device.h> | 17 | #include <linux/device.h> |
18 | #include <linux/errno.h> | ||
19 | #include <linux/init.h> | ||
20 | #include <linux/io.h> | ||
18 | #include <linux/jiffies.h> | 21 | #include <linux/jiffies.h> |
19 | #include <linux/smp.h> | 22 | #include <linux/smp.h> |
20 | #include <linux/io.h> | 23 | |
21 | #include <linux/clk/tegra.h> | 24 | #include <soc/tegra/fuse.h> |
25 | #include <soc/tegra/pmc.h> | ||
22 | 26 | ||
23 | #include <asm/cacheflush.h> | 27 | #include <asm/cacheflush.h> |
24 | #include <asm/mach-types.h> | 28 | #include <asm/mach-types.h> |
25 | #include <asm/smp_scu.h> | ||
26 | #include <asm/smp_plat.h> | 29 | #include <asm/smp_plat.h> |
27 | 30 | #include <asm/smp_scu.h> | |
28 | #include "fuse.h" | ||
29 | #include "flowctrl.h" | ||
30 | #include "reset.h" | ||
31 | #include "pmc.h" | ||
32 | 31 | ||
33 | #include "common.h" | 32 | #include "common.h" |
33 | #include "flowctrl.h" | ||
34 | #include "iomap.h" | 34 | #include "iomap.h" |
35 | #include "reset.h" | ||
35 | 36 | ||
36 | static cpumask_t tegra_cpu_init_mask; | 37 | static cpumask_t tegra_cpu_init_mask; |
37 | 38 | ||
@@ -170,13 +171,13 @@ static int tegra114_boot_secondary(unsigned int cpu, struct task_struct *idle) | |||
170 | static int tegra_boot_secondary(unsigned int cpu, | 171 | static int tegra_boot_secondary(unsigned int cpu, |
171 | struct task_struct *idle) | 172 | struct task_struct *idle) |
172 | { | 173 | { |
173 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20) | 174 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_get_chip_id() == TEGRA20) |
174 | return tegra20_boot_secondary(cpu, idle); | 175 | return tegra20_boot_secondary(cpu, idle); |
175 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30) | 176 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_get_chip_id() == TEGRA30) |
176 | return tegra30_boot_secondary(cpu, idle); | 177 | return tegra30_boot_secondary(cpu, idle); |
177 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_chip_id == TEGRA114) | 178 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_114_SOC) && tegra_get_chip_id() == TEGRA114) |
178 | return tegra114_boot_secondary(cpu, idle); | 179 | return tegra114_boot_secondary(cpu, idle); |
179 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_chip_id == TEGRA124) | 180 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_124_SOC) && tegra_get_chip_id() == TEGRA124) |
180 | return tegra114_boot_secondary(cpu, idle); | 181 | return tegra114_boot_secondary(cpu, idle); |
181 | 182 | ||
182 | return -EINVAL; | 183 | return -EINVAL; |
diff --git a/arch/arm/mach-tegra/pm-tegra20.c b/arch/arm/mach-tegra/pm-tegra20.c index d65e1d786400..39ac2b723f2e 100644 --- a/arch/arm/mach-tegra/pm-tegra20.c +++ b/arch/arm/mach-tegra/pm-tegra20.c | |||
@@ -13,6 +13,7 @@ | |||
13 | * You should have received a copy of the GNU General Public License | 13 | * You should have received a copy of the GNU General Public License |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | |||
16 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
17 | 18 | ||
18 | #include "pm.h" | 19 | #include "pm.h" |
diff --git a/arch/arm/mach-tegra/pm-tegra30.c b/arch/arm/mach-tegra/pm-tegra30.c index 8fa326d6ff1a..46cc19de9916 100644 --- a/arch/arm/mach-tegra/pm-tegra30.c +++ b/arch/arm/mach-tegra/pm-tegra30.c | |||
@@ -13,6 +13,7 @@ | |||
13 | * You should have received a copy of the GNU General Public License | 13 | * You should have received a copy of the GNU General Public License |
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | |||
16 | #include <linux/kernel.h> | 17 | #include <linux/kernel.h> |
17 | 18 | ||
18 | #include "pm.h" | 19 | #include "pm.h" |
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c index f55b05a29b55..b0f48a3946fa 100644 --- a/arch/arm/mach-tegra/pm.c +++ b/arch/arm/mach-tegra/pm.c | |||
@@ -16,30 +16,32 @@ | |||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/kernel.h> | 19 | #include <linux/clk/tegra.h> |
20 | #include <linux/spinlock.h> | ||
21 | #include <linux/io.h> | ||
22 | #include <linux/cpumask.h> | 20 | #include <linux/cpumask.h> |
23 | #include <linux/delay.h> | ||
24 | #include <linux/cpu_pm.h> | 21 | #include <linux/cpu_pm.h> |
25 | #include <linux/suspend.h> | 22 | #include <linux/delay.h> |
26 | #include <linux/err.h> | 23 | #include <linux/err.h> |
24 | #include <linux/io.h> | ||
25 | #include <linux/kernel.h> | ||
27 | #include <linux/slab.h> | 26 | #include <linux/slab.h> |
28 | #include <linux/clk/tegra.h> | 27 | #include <linux/spinlock.h> |
28 | #include <linux/suspend.h> | ||
29 | |||
30 | #include <soc/tegra/fuse.h> | ||
31 | #include <soc/tegra/pm.h> | ||
32 | #include <soc/tegra/pmc.h> | ||
29 | 33 | ||
30 | #include <asm/smp_plat.h> | ||
31 | #include <asm/cacheflush.h> | 34 | #include <asm/cacheflush.h> |
32 | #include <asm/suspend.h> | ||
33 | #include <asm/idmap.h> | 35 | #include <asm/idmap.h> |
34 | #include <asm/proc-fns.h> | 36 | #include <asm/proc-fns.h> |
37 | #include <asm/smp_plat.h> | ||
38 | #include <asm/suspend.h> | ||
35 | #include <asm/tlbflush.h> | 39 | #include <asm/tlbflush.h> |
36 | 40 | ||
37 | #include "iomap.h" | ||
38 | #include "reset.h" | ||
39 | #include "flowctrl.h" | 41 | #include "flowctrl.h" |
40 | #include "fuse.h" | 42 | #include "iomap.h" |
41 | #include "pm.h" | 43 | #include "pm.h" |
42 | #include "pmc.h" | 44 | #include "reset.h" |
43 | #include "sleep.h" | 45 | #include "sleep.h" |
44 | 46 | ||
45 | #ifdef CONFIG_PM_SLEEP | 47 | #ifdef CONFIG_PM_SLEEP |
@@ -53,7 +55,7 @@ static int (*tegra_sleep_func)(unsigned long v2p); | |||
53 | 55 | ||
54 | static void tegra_tear_down_cpu_init(void) | 56 | static void tegra_tear_down_cpu_init(void) |
55 | { | 57 | { |
56 | switch (tegra_chip_id) { | 58 | switch (tegra_get_chip_id()) { |
57 | case TEGRA20: | 59 | case TEGRA20: |
58 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | 60 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
59 | tegra_tear_down_cpu = tegra20_tear_down_cpu; | 61 | tegra_tear_down_cpu = tegra20_tear_down_cpu; |
@@ -143,7 +145,7 @@ bool tegra_set_cpu_in_lp2(void) | |||
143 | 145 | ||
144 | if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) | 146 | if ((phy_cpu_id == 0) && cpumask_equal(cpu_lp2_mask, cpu_online_mask)) |
145 | last_cpu = true; | 147 | last_cpu = true; |
146 | else if (tegra_chip_id == TEGRA20 && phy_cpu_id == 1) | 148 | else if (tegra_get_chip_id() == TEGRA20 && phy_cpu_id == 1) |
147 | tegra20_cpu_set_resettable_soon(); | 149 | tegra20_cpu_set_resettable_soon(); |
148 | 150 | ||
149 | spin_unlock(&tegra_lp2_lock); | 151 | spin_unlock(&tegra_lp2_lock); |
@@ -166,9 +168,29 @@ static int tegra_sleep_cpu(unsigned long v2p) | |||
166 | return 0; | 168 | return 0; |
167 | } | 169 | } |
168 | 170 | ||
171 | static void tegra_pm_set(enum tegra_suspend_mode mode) | ||
172 | { | ||
173 | u32 value; | ||
174 | |||
175 | switch (tegra_get_chip_id()) { | ||
176 | case TEGRA20: | ||
177 | case TEGRA30: | ||
178 | break; | ||
179 | default: | ||
180 | /* Turn off CRAIL */ | ||
181 | value = flowctrl_read_cpu_csr(0); | ||
182 | value &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; | ||
183 | value |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; | ||
184 | flowctrl_write_cpu_csr(0, value); | ||
185 | break; | ||
186 | } | ||
187 | |||
188 | tegra_pmc_enter_suspend_mode(mode); | ||
189 | } | ||
190 | |||
169 | void tegra_idle_lp2_last(void) | 191 | void tegra_idle_lp2_last(void) |
170 | { | 192 | { |
171 | tegra_pmc_pm_set(TEGRA_SUSPEND_LP2); | 193 | tegra_pm_set(TEGRA_SUSPEND_LP2); |
172 | 194 | ||
173 | cpu_cluster_pm_enter(); | 195 | cpu_cluster_pm_enter(); |
174 | suspend_cpu_complex(); | 196 | suspend_cpu_complex(); |
@@ -212,7 +234,7 @@ static int tegra_sleep_core(unsigned long v2p) | |||
212 | */ | 234 | */ |
213 | static bool tegra_lp1_iram_hook(void) | 235 | static bool tegra_lp1_iram_hook(void) |
214 | { | 236 | { |
215 | switch (tegra_chip_id) { | 237 | switch (tegra_get_chip_id()) { |
216 | case TEGRA20: | 238 | case TEGRA20: |
217 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | 239 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
218 | tegra20_lp1_iram_hook(); | 240 | tegra20_lp1_iram_hook(); |
@@ -242,7 +264,7 @@ static bool tegra_lp1_iram_hook(void) | |||
242 | 264 | ||
243 | static bool tegra_sleep_core_init(void) | 265 | static bool tegra_sleep_core_init(void) |
244 | { | 266 | { |
245 | switch (tegra_chip_id) { | 267 | switch (tegra_get_chip_id()) { |
246 | case TEGRA20: | 268 | case TEGRA20: |
247 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) | 269 | if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) |
248 | tegra20_sleep_core_init(); | 270 | tegra20_sleep_core_init(); |
@@ -267,8 +289,6 @@ static bool tegra_sleep_core_init(void) | |||
267 | 289 | ||
268 | static void tegra_suspend_enter_lp1(void) | 290 | static void tegra_suspend_enter_lp1(void) |
269 | { | 291 | { |
270 | tegra_pmc_suspend(); | ||
271 | |||
272 | /* copy the reset vector & SDRAM shutdown code into IRAM */ | 292 | /* copy the reset vector & SDRAM shutdown code into IRAM */ |
273 | memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), | 293 | memcpy(iram_save_addr, IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), |
274 | iram_save_size); | 294 | iram_save_size); |
@@ -280,8 +300,6 @@ static void tegra_suspend_enter_lp1(void) | |||
280 | 300 | ||
281 | static void tegra_suspend_exit_lp1(void) | 301 | static void tegra_suspend_exit_lp1(void) |
282 | { | 302 | { |
283 | tegra_pmc_resume(); | ||
284 | |||
285 | /* restore IRAM */ | 303 | /* restore IRAM */ |
286 | memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, | 304 | memcpy(IO_ADDRESS(TEGRA_IRAM_LPx_RESUME_AREA), iram_save_addr, |
287 | iram_save_size); | 305 | iram_save_size); |
@@ -306,7 +324,7 @@ static int tegra_suspend_enter(suspend_state_t state) | |||
306 | 324 | ||
307 | pr_info("Entering suspend state %s\n", lp_state[mode]); | 325 | pr_info("Entering suspend state %s\n", lp_state[mode]); |
308 | 326 | ||
309 | tegra_pmc_pm_set(mode); | 327 | tegra_pm_set(mode); |
310 | 328 | ||
311 | local_fiq_disable(); | 329 | local_fiq_disable(); |
312 | 330 | ||
@@ -354,7 +372,6 @@ void __init tegra_init_suspend(void) | |||
354 | return; | 372 | return; |
355 | 373 | ||
356 | tegra_tear_down_cpu_init(); | 374 | tegra_tear_down_cpu_init(); |
357 | tegra_pmc_suspend_init(); | ||
358 | 375 | ||
359 | if (mode >= TEGRA_SUSPEND_LP1) { | 376 | if (mode >= TEGRA_SUSPEND_LP1) { |
360 | if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { | 377 | if (!tegra_lp1_iram_hook() || !tegra_sleep_core_init()) { |
diff --git a/arch/arm/mach-tegra/pm.h b/arch/arm/mach-tegra/pm.h index f4a89698e5b0..83bc87583446 100644 --- a/arch/arm/mach-tegra/pm.h +++ b/arch/arm/mach-tegra/pm.h | |||
@@ -21,12 +21,11 @@ | |||
21 | #ifndef _MACH_TEGRA_PM_H_ | 21 | #ifndef _MACH_TEGRA_PM_H_ |
22 | #define _MACH_TEGRA_PM_H_ | 22 | #define _MACH_TEGRA_PM_H_ |
23 | 23 | ||
24 | #include "pmc.h" | ||
25 | |||
26 | struct tegra_lp1_iram { | 24 | struct tegra_lp1_iram { |
27 | void *start_addr; | 25 | void *start_addr; |
28 | void *end_addr; | 26 | void *end_addr; |
29 | }; | 27 | }; |
28 | |||
30 | extern struct tegra_lp1_iram tegra_lp1_iram; | 29 | extern struct tegra_lp1_iram tegra_lp1_iram; |
31 | extern void (*tegra_sleep_core_finish)(unsigned long v2p); | 30 | extern void (*tegra_sleep_core_finish)(unsigned long v2p); |
32 | 31 | ||
@@ -42,15 +41,8 @@ void tegra_idle_lp2_last(void); | |||
42 | extern void (*tegra_tear_down_cpu)(void); | 41 | extern void (*tegra_tear_down_cpu)(void); |
43 | 42 | ||
44 | #ifdef CONFIG_PM_SLEEP | 43 | #ifdef CONFIG_PM_SLEEP |
45 | enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
46 | enum tegra_suspend_mode mode); | ||
47 | void tegra_init_suspend(void); | 44 | void tegra_init_suspend(void); |
48 | #else | 45 | #else |
49 | static inline enum tegra_suspend_mode tegra_pm_validate_suspend_mode( | ||
50 | enum tegra_suspend_mode mode) | ||
51 | { | ||
52 | return TEGRA_SUSPEND_NONE; | ||
53 | } | ||
54 | static inline void tegra_init_suspend(void) {} | 46 | static inline void tegra_init_suspend(void) {} |
55 | #endif | 47 | #endif |
56 | 48 | ||
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c deleted file mode 100644 index 7c7123e7557b..000000000000 --- a/arch/arm/mach-tegra/pmc.c +++ /dev/null | |||
@@ -1,413 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #include <linux/kernel.h> | ||
19 | #include <linux/clk.h> | ||
20 | #include <linux/io.h> | ||
21 | #include <linux/of.h> | ||
22 | #include <linux/of_address.h> | ||
23 | #include <linux/tegra-powergate.h> | ||
24 | |||
25 | #include "flowctrl.h" | ||
26 | #include "fuse.h" | ||
27 | #include "pm.h" | ||
28 | #include "pmc.h" | ||
29 | #include "sleep.h" | ||
30 | |||
31 | #define TEGRA_POWER_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */ | ||
32 | #define TEGRA_POWER_SYSCLK_OE (1 << 11) /* system clock enable */ | ||
33 | #define TEGRA_POWER_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */ | ||
34 | #define TEGRA_POWER_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */ | ||
35 | #define TEGRA_POWER_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */ | ||
36 | |||
37 | #define PMC_CTRL 0x0 | ||
38 | #define PMC_CTRL_INTR_LOW (1 << 17) | ||
39 | #define PMC_PWRGATE_TOGGLE 0x30 | ||
40 | #define PMC_PWRGATE_TOGGLE_START (1 << 8) | ||
41 | #define PMC_REMOVE_CLAMPING 0x34 | ||
42 | #define PMC_PWRGATE_STATUS 0x38 | ||
43 | |||
44 | #define PMC_SCRATCH0 0x50 | ||
45 | #define PMC_SCRATCH0_MODE_RECOVERY (1 << 31) | ||
46 | #define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30) | ||
47 | #define PMC_SCRATCH0_MODE_RCM (1 << 1) | ||
48 | #define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \ | ||
49 | PMC_SCRATCH0_MODE_BOOTLOADER | \ | ||
50 | PMC_SCRATCH0_MODE_RCM) | ||
51 | |||
52 | #define PMC_CPUPWRGOOD_TIMER 0xc8 | ||
53 | #define PMC_CPUPWROFF_TIMER 0xcc | ||
54 | |||
55 | static u8 tegra_cpu_domains[] = { | ||
56 | 0xFF, /* not available for CPU0 */ | ||
57 | TEGRA_POWERGATE_CPU1, | ||
58 | TEGRA_POWERGATE_CPU2, | ||
59 | TEGRA_POWERGATE_CPU3, | ||
60 | }; | ||
61 | static DEFINE_SPINLOCK(tegra_powergate_lock); | ||
62 | |||
63 | static void __iomem *tegra_pmc_base; | ||
64 | static bool tegra_pmc_invert_interrupt; | ||
65 | static struct clk *tegra_pclk; | ||
66 | |||
67 | struct pmc_pm_data { | ||
68 | u32 cpu_good_time; /* CPU power good time in uS */ | ||
69 | u32 cpu_off_time; /* CPU power off time in uS */ | ||
70 | u32 core_osc_time; /* Core power good osc time in uS */ | ||
71 | u32 core_pmu_time; /* Core power good pmu time in uS */ | ||
72 | u32 core_off_time; /* Core power off time in uS */ | ||
73 | bool corereq_high; /* Core power request active-high */ | ||
74 | bool sysclkreq_high; /* System clock request active-high */ | ||
75 | bool combined_req; /* Combined pwr req for CPU & Core */ | ||
76 | bool cpu_pwr_good_en; /* CPU power good signal is enabled */ | ||
77 | u32 lp0_vec_phy_addr; /* The phy addr of LP0 warm boot code */ | ||
78 | u32 lp0_vec_size; /* The size of LP0 warm boot code */ | ||
79 | enum tegra_suspend_mode suspend_mode; | ||
80 | }; | ||
81 | static struct pmc_pm_data pmc_pm_data; | ||
82 | |||
83 | static inline u32 tegra_pmc_readl(u32 reg) | ||
84 | { | ||
85 | return readl(tegra_pmc_base + reg); | ||
86 | } | ||
87 | |||
88 | static inline void tegra_pmc_writel(u32 val, u32 reg) | ||
89 | { | ||
90 | writel(val, tegra_pmc_base + reg); | ||
91 | } | ||
92 | |||
93 | static int tegra_pmc_get_cpu_powerdomain_id(int cpuid) | ||
94 | { | ||
95 | if (cpuid <= 0 || cpuid >= num_possible_cpus()) | ||
96 | return -EINVAL; | ||
97 | return tegra_cpu_domains[cpuid]; | ||
98 | } | ||
99 | |||
100 | static bool tegra_pmc_powergate_is_powered(int id) | ||
101 | { | ||
102 | return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1; | ||
103 | } | ||
104 | |||
105 | static int tegra_pmc_powergate_set(int id, bool new_state) | ||
106 | { | ||
107 | bool old_state; | ||
108 | unsigned long flags; | ||
109 | |||
110 | spin_lock_irqsave(&tegra_powergate_lock, flags); | ||
111 | |||
112 | old_state = tegra_pmc_powergate_is_powered(id); | ||
113 | WARN_ON(old_state == new_state); | ||
114 | |||
115 | tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE); | ||
116 | |||
117 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); | ||
118 | |||
119 | return 0; | ||
120 | } | ||
121 | |||
122 | static int tegra_pmc_powergate_remove_clamping(int id) | ||
123 | { | ||
124 | u32 mask; | ||
125 | |||
126 | /* | ||
127 | * Tegra has a bug where PCIE and VDE clamping masks are | ||
128 | * swapped relatively to the partition ids. | ||
129 | */ | ||
130 | if (id == TEGRA_POWERGATE_VDEC) | ||
131 | mask = (1 << TEGRA_POWERGATE_PCIE); | ||
132 | else if (id == TEGRA_POWERGATE_PCIE) | ||
133 | mask = (1 << TEGRA_POWERGATE_VDEC); | ||
134 | else | ||
135 | mask = (1 << id); | ||
136 | |||
137 | tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING); | ||
138 | |||
139 | return 0; | ||
140 | } | ||
141 | |||
142 | bool tegra_pmc_cpu_is_powered(int cpuid) | ||
143 | { | ||
144 | int id; | ||
145 | |||
146 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
147 | if (id < 0) | ||
148 | return false; | ||
149 | return tegra_pmc_powergate_is_powered(id); | ||
150 | } | ||
151 | |||
152 | int tegra_pmc_cpu_power_on(int cpuid) | ||
153 | { | ||
154 | int id; | ||
155 | |||
156 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
157 | if (id < 0) | ||
158 | return id; | ||
159 | return tegra_pmc_powergate_set(id, true); | ||
160 | } | ||
161 | |||
162 | int tegra_pmc_cpu_remove_clamping(int cpuid) | ||
163 | { | ||
164 | int id; | ||
165 | |||
166 | id = tegra_pmc_get_cpu_powerdomain_id(cpuid); | ||
167 | if (id < 0) | ||
168 | return id; | ||
169 | return tegra_pmc_powergate_remove_clamping(id); | ||
170 | } | ||
171 | |||
172 | void tegra_pmc_restart(enum reboot_mode mode, const char *cmd) | ||
173 | { | ||
174 | u32 val; | ||
175 | |||
176 | val = tegra_pmc_readl(PMC_SCRATCH0); | ||
177 | val &= ~PMC_SCRATCH0_MODE_MASK; | ||
178 | |||
179 | if (cmd) { | ||
180 | if (strcmp(cmd, "recovery") == 0) | ||
181 | val |= PMC_SCRATCH0_MODE_RECOVERY; | ||
182 | |||
183 | if (strcmp(cmd, "bootloader") == 0) | ||
184 | val |= PMC_SCRATCH0_MODE_BOOTLOADER; | ||
185 | |||
186 | if (strcmp(cmd, "forced-recovery") == 0) | ||
187 | val |= PMC_SCRATCH0_MODE_RCM; | ||
188 | } | ||
189 | |||
190 | tegra_pmc_writel(val, PMC_SCRATCH0); | ||
191 | |||
192 | val = tegra_pmc_readl(0); | ||
193 | val |= 0x10; | ||
194 | tegra_pmc_writel(val, 0); | ||
195 | } | ||
196 | |||
197 | #ifdef CONFIG_PM_SLEEP | ||
198 | static void set_power_timers(u32 us_on, u32 us_off, unsigned long rate) | ||
199 | { | ||
200 | unsigned long long ticks; | ||
201 | unsigned long long pclk; | ||
202 | static unsigned long tegra_last_pclk; | ||
203 | |||
204 | if (WARN_ON_ONCE(rate <= 0)) | ||
205 | pclk = 100000000; | ||
206 | else | ||
207 | pclk = rate; | ||
208 | |||
209 | if ((rate != tegra_last_pclk)) { | ||
210 | ticks = (us_on * pclk) + 999999ull; | ||
211 | do_div(ticks, 1000000); | ||
212 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWRGOOD_TIMER); | ||
213 | |||
214 | ticks = (us_off * pclk) + 999999ull; | ||
215 | do_div(ticks, 1000000); | ||
216 | tegra_pmc_writel((unsigned long)ticks, PMC_CPUPWROFF_TIMER); | ||
217 | wmb(); | ||
218 | } | ||
219 | tegra_last_pclk = pclk; | ||
220 | } | ||
221 | |||
222 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void) | ||
223 | { | ||
224 | return pmc_pm_data.suspend_mode; | ||
225 | } | ||
226 | |||
227 | void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode) | ||
228 | { | ||
229 | if (mode < TEGRA_SUSPEND_NONE || mode >= TEGRA_MAX_SUSPEND_MODE) | ||
230 | return; | ||
231 | |||
232 | pmc_pm_data.suspend_mode = mode; | ||
233 | } | ||
234 | |||
235 | void tegra_pmc_suspend(void) | ||
236 | { | ||
237 | tegra_pmc_writel(virt_to_phys(tegra_resume), PMC_SCRATCH41); | ||
238 | } | ||
239 | |||
240 | void tegra_pmc_resume(void) | ||
241 | { | ||
242 | tegra_pmc_writel(0x0, PMC_SCRATCH41); | ||
243 | } | ||
244 | |||
245 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode) | ||
246 | { | ||
247 | u32 reg, csr_reg; | ||
248 | unsigned long rate = 0; | ||
249 | |||
250 | reg = tegra_pmc_readl(PMC_CTRL); | ||
251 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
252 | reg &= ~TEGRA_POWER_EFFECT_LP0; | ||
253 | |||
254 | switch (tegra_chip_id) { | ||
255 | case TEGRA20: | ||
256 | case TEGRA30: | ||
257 | break; | ||
258 | default: | ||
259 | /* Turn off CRAIL */ | ||
260 | csr_reg = flowctrl_read_cpu_csr(0); | ||
261 | csr_reg &= ~FLOW_CTRL_CSR_ENABLE_EXT_MASK; | ||
262 | csr_reg |= FLOW_CTRL_CSR_ENABLE_EXT_CRAIL; | ||
263 | flowctrl_write_cpu_csr(0, csr_reg); | ||
264 | break; | ||
265 | } | ||
266 | |||
267 | switch (mode) { | ||
268 | case TEGRA_SUSPEND_LP1: | ||
269 | rate = 32768; | ||
270 | break; | ||
271 | case TEGRA_SUSPEND_LP2: | ||
272 | rate = clk_get_rate(tegra_pclk); | ||
273 | break; | ||
274 | default: | ||
275 | break; | ||
276 | } | ||
277 | |||
278 | set_power_timers(pmc_pm_data.cpu_good_time, pmc_pm_data.cpu_off_time, | ||
279 | rate); | ||
280 | |||
281 | tegra_pmc_writel(reg, PMC_CTRL); | ||
282 | } | ||
283 | |||
284 | void tegra_pmc_suspend_init(void) | ||
285 | { | ||
286 | u32 reg; | ||
287 | |||
288 | /* Always enable CPU power request */ | ||
289 | reg = tegra_pmc_readl(PMC_CTRL); | ||
290 | reg |= TEGRA_POWER_CPU_PWRREQ_OE; | ||
291 | tegra_pmc_writel(reg, PMC_CTRL); | ||
292 | |||
293 | reg = tegra_pmc_readl(PMC_CTRL); | ||
294 | |||
295 | if (!pmc_pm_data.sysclkreq_high) | ||
296 | reg |= TEGRA_POWER_SYSCLK_POLARITY; | ||
297 | else | ||
298 | reg &= ~TEGRA_POWER_SYSCLK_POLARITY; | ||
299 | |||
300 | /* configure the output polarity while the request is tristated */ | ||
301 | tegra_pmc_writel(reg, PMC_CTRL); | ||
302 | |||
303 | /* now enable the request */ | ||
304 | reg |= TEGRA_POWER_SYSCLK_OE; | ||
305 | tegra_pmc_writel(reg, PMC_CTRL); | ||
306 | } | ||
307 | #endif | ||
308 | |||
309 | static const struct of_device_id matches[] __initconst = { | ||
310 | { .compatible = "nvidia,tegra124-pmc" }, | ||
311 | { .compatible = "nvidia,tegra114-pmc" }, | ||
312 | { .compatible = "nvidia,tegra30-pmc" }, | ||
313 | { .compatible = "nvidia,tegra20-pmc" }, | ||
314 | { } | ||
315 | }; | ||
316 | |||
317 | void __init tegra_pmc_init_irq(void) | ||
318 | { | ||
319 | struct device_node *np; | ||
320 | u32 val; | ||
321 | |||
322 | np = of_find_matching_node(NULL, matches); | ||
323 | BUG_ON(!np); | ||
324 | |||
325 | tegra_pmc_base = of_iomap(np, 0); | ||
326 | |||
327 | tegra_pmc_invert_interrupt = of_property_read_bool(np, | ||
328 | "nvidia,invert-interrupt"); | ||
329 | |||
330 | val = tegra_pmc_readl(PMC_CTRL); | ||
331 | if (tegra_pmc_invert_interrupt) | ||
332 | val |= PMC_CTRL_INTR_LOW; | ||
333 | else | ||
334 | val &= ~PMC_CTRL_INTR_LOW; | ||
335 | tegra_pmc_writel(val, PMC_CTRL); | ||
336 | } | ||
337 | |||
338 | void __init tegra_pmc_init(void) | ||
339 | { | ||
340 | struct device_node *np; | ||
341 | u32 prop; | ||
342 | enum tegra_suspend_mode suspend_mode; | ||
343 | u32 core_good_time[2] = {0, 0}; | ||
344 | u32 lp0_vec[2] = {0, 0}; | ||
345 | |||
346 | np = of_find_matching_node(NULL, matches); | ||
347 | BUG_ON(!np); | ||
348 | |||
349 | tegra_pclk = of_clk_get_by_name(np, "pclk"); | ||
350 | WARN_ON(IS_ERR(tegra_pclk)); | ||
351 | |||
352 | /* Grabbing the power management configurations */ | ||
353 | if (of_property_read_u32(np, "nvidia,suspend-mode", &prop)) { | ||
354 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
355 | } else { | ||
356 | switch (prop) { | ||
357 | case 0: | ||
358 | suspend_mode = TEGRA_SUSPEND_LP0; | ||
359 | break; | ||
360 | case 1: | ||
361 | suspend_mode = TEGRA_SUSPEND_LP1; | ||
362 | break; | ||
363 | case 2: | ||
364 | suspend_mode = TEGRA_SUSPEND_LP2; | ||
365 | break; | ||
366 | default: | ||
367 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
368 | break; | ||
369 | } | ||
370 | } | ||
371 | suspend_mode = tegra_pm_validate_suspend_mode(suspend_mode); | ||
372 | |||
373 | if (of_property_read_u32(np, "nvidia,cpu-pwr-good-time", &prop)) | ||
374 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
375 | pmc_pm_data.cpu_good_time = prop; | ||
376 | |||
377 | if (of_property_read_u32(np, "nvidia,cpu-pwr-off-time", &prop)) | ||
378 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
379 | pmc_pm_data.cpu_off_time = prop; | ||
380 | |||
381 | if (of_property_read_u32_array(np, "nvidia,core-pwr-good-time", | ||
382 | core_good_time, ARRAY_SIZE(core_good_time))) | ||
383 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
384 | pmc_pm_data.core_osc_time = core_good_time[0]; | ||
385 | pmc_pm_data.core_pmu_time = core_good_time[1]; | ||
386 | |||
387 | if (of_property_read_u32(np, "nvidia,core-pwr-off-time", | ||
388 | &prop)) | ||
389 | suspend_mode = TEGRA_SUSPEND_NONE; | ||
390 | pmc_pm_data.core_off_time = prop; | ||
391 | |||
392 | pmc_pm_data.corereq_high = of_property_read_bool(np, | ||
393 | "nvidia,core-power-req-active-high"); | ||
394 | |||
395 | pmc_pm_data.sysclkreq_high = of_property_read_bool(np, | ||
396 | "nvidia,sys-clock-req-active-high"); | ||
397 | |||
398 | pmc_pm_data.combined_req = of_property_read_bool(np, | ||
399 | "nvidia,combined-power-req"); | ||
400 | |||
401 | pmc_pm_data.cpu_pwr_good_en = of_property_read_bool(np, | ||
402 | "nvidia,cpu-pwr-good-en"); | ||
403 | |||
404 | if (of_property_read_u32_array(np, "nvidia,lp0-vec", lp0_vec, | ||
405 | ARRAY_SIZE(lp0_vec))) | ||
406 | if (suspend_mode == TEGRA_SUSPEND_LP0) | ||
407 | suspend_mode = TEGRA_SUSPEND_LP1; | ||
408 | |||
409 | pmc_pm_data.lp0_vec_phy_addr = lp0_vec[0]; | ||
410 | pmc_pm_data.lp0_vec_size = lp0_vec[1]; | ||
411 | |||
412 | pmc_pm_data.suspend_mode = suspend_mode; | ||
413 | } | ||
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h deleted file mode 100644 index 59e19c344298..000000000000 --- a/arch/arm/mach-tegra/pmc.h +++ /dev/null | |||
@@ -1,49 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | * | ||
16 | */ | ||
17 | |||
18 | #ifndef __MACH_TEGRA_PMC_H | ||
19 | #define __MACH_TEGRA_PMC_H | ||
20 | |||
21 | #include <linux/reboot.h> | ||
22 | |||
23 | enum tegra_suspend_mode { | ||
24 | TEGRA_SUSPEND_NONE = 0, | ||
25 | TEGRA_SUSPEND_LP2, /* CPU voltage off */ | ||
26 | TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */ | ||
27 | TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */ | ||
28 | TEGRA_MAX_SUSPEND_MODE, | ||
29 | }; | ||
30 | |||
31 | #ifdef CONFIG_PM_SLEEP | ||
32 | enum tegra_suspend_mode tegra_pmc_get_suspend_mode(void); | ||
33 | void tegra_pmc_set_suspend_mode(enum tegra_suspend_mode mode); | ||
34 | void tegra_pmc_suspend(void); | ||
35 | void tegra_pmc_resume(void); | ||
36 | void tegra_pmc_pm_set(enum tegra_suspend_mode mode); | ||
37 | void tegra_pmc_suspend_init(void); | ||
38 | #endif | ||
39 | |||
40 | bool tegra_pmc_cpu_is_powered(int cpuid); | ||
41 | int tegra_pmc_cpu_power_on(int cpuid); | ||
42 | int tegra_pmc_cpu_remove_clamping(int cpuid); | ||
43 | |||
44 | void tegra_pmc_restart(enum reboot_mode mode, const char *cmd); | ||
45 | |||
46 | void tegra_pmc_init_irq(void); | ||
47 | void tegra_pmc_init(void); | ||
48 | |||
49 | #endif | ||
diff --git a/arch/arm/mach-tegra/powergate.c b/arch/arm/mach-tegra/powergate.c deleted file mode 100644 index 4cefc5cd6bed..000000000000 --- a/arch/arm/mach-tegra/powergate.c +++ /dev/null | |||
@@ -1,515 +0,0 @@ | |||
1 | /* | ||
2 | * drivers/powergate/tegra-powergate.c | ||
3 | * | ||
4 | * Copyright (c) 2010 Google, Inc | ||
5 | * | ||
6 | * Author: | ||
7 | * Colin Cross <ccross@google.com> | ||
8 | * | ||
9 | * This software is licensed under the terms of the GNU General Public | ||
10 | * License version 2, as published by the Free Software Foundation, and | ||
11 | * may be copied, distributed, and modified under those terms. | ||
12 | * | ||
13 | * This program is distributed in the hope that it will be useful, | ||
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
16 | * GNU General Public License for more details. | ||
17 | * | ||
18 | */ | ||
19 | |||
20 | #include <linux/kernel.h> | ||
21 | #include <linux/clk.h> | ||
22 | #include <linux/debugfs.h> | ||
23 | #include <linux/delay.h> | ||
24 | #include <linux/err.h> | ||
25 | #include <linux/export.h> | ||
26 | #include <linux/init.h> | ||
27 | #include <linux/io.h> | ||
28 | #include <linux/reset.h> | ||
29 | #include <linux/seq_file.h> | ||
30 | #include <linux/spinlock.h> | ||
31 | #include <linux/clk/tegra.h> | ||
32 | #include <linux/tegra-powergate.h> | ||
33 | |||
34 | #include "fuse.h" | ||
35 | #include "iomap.h" | ||
36 | |||
37 | #define DPD_SAMPLE 0x020 | ||
38 | #define DPD_SAMPLE_ENABLE (1 << 0) | ||
39 | #define DPD_SAMPLE_DISABLE (0 << 0) | ||
40 | |||
41 | #define PWRGATE_TOGGLE 0x30 | ||
42 | #define PWRGATE_TOGGLE_START (1 << 8) | ||
43 | |||
44 | #define REMOVE_CLAMPING 0x34 | ||
45 | |||
46 | #define PWRGATE_STATUS 0x38 | ||
47 | |||
48 | #define IO_DPD_REQ 0x1b8 | ||
49 | #define IO_DPD_REQ_CODE_IDLE (0 << 30) | ||
50 | #define IO_DPD_REQ_CODE_OFF (1 << 30) | ||
51 | #define IO_DPD_REQ_CODE_ON (2 << 30) | ||
52 | #define IO_DPD_REQ_CODE_MASK (3 << 30) | ||
53 | |||
54 | #define IO_DPD_STATUS 0x1bc | ||
55 | #define IO_DPD2_REQ 0x1c0 | ||
56 | #define IO_DPD2_STATUS 0x1c4 | ||
57 | #define SEL_DPD_TIM 0x1c8 | ||
58 | |||
59 | #define GPU_RG_CNTRL 0x2d4 | ||
60 | |||
61 | static int tegra_num_powerdomains; | ||
62 | static int tegra_num_cpu_domains; | ||
63 | static const u8 *tegra_cpu_domains; | ||
64 | |||
65 | static const u8 tegra30_cpu_domains[] = { | ||
66 | TEGRA_POWERGATE_CPU, | ||
67 | TEGRA_POWERGATE_CPU1, | ||
68 | TEGRA_POWERGATE_CPU2, | ||
69 | TEGRA_POWERGATE_CPU3, | ||
70 | }; | ||
71 | |||
72 | static const u8 tegra114_cpu_domains[] = { | ||
73 | TEGRA_POWERGATE_CPU0, | ||
74 | TEGRA_POWERGATE_CPU1, | ||
75 | TEGRA_POWERGATE_CPU2, | ||
76 | TEGRA_POWERGATE_CPU3, | ||
77 | }; | ||
78 | |||
79 | static const u8 tegra124_cpu_domains[] = { | ||
80 | TEGRA_POWERGATE_CPU0, | ||
81 | TEGRA_POWERGATE_CPU1, | ||
82 | TEGRA_POWERGATE_CPU2, | ||
83 | TEGRA_POWERGATE_CPU3, | ||
84 | }; | ||
85 | |||
86 | static DEFINE_SPINLOCK(tegra_powergate_lock); | ||
87 | |||
88 | static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); | ||
89 | |||
90 | static u32 pmc_read(unsigned long reg) | ||
91 | { | ||
92 | return readl(pmc + reg); | ||
93 | } | ||
94 | |||
95 | static void pmc_write(u32 val, unsigned long reg) | ||
96 | { | ||
97 | writel(val, pmc + reg); | ||
98 | } | ||
99 | |||
100 | static int tegra_powergate_set(int id, bool new_state) | ||
101 | { | ||
102 | bool status; | ||
103 | unsigned long flags; | ||
104 | |||
105 | spin_lock_irqsave(&tegra_powergate_lock, flags); | ||
106 | |||
107 | status = pmc_read(PWRGATE_STATUS) & (1 << id); | ||
108 | |||
109 | if (status == new_state) { | ||
110 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); | ||
111 | return 0; | ||
112 | } | ||
113 | |||
114 | pmc_write(PWRGATE_TOGGLE_START | id, PWRGATE_TOGGLE); | ||
115 | |||
116 | spin_unlock_irqrestore(&tegra_powergate_lock, flags); | ||
117 | |||
118 | return 0; | ||
119 | } | ||
120 | |||
121 | int tegra_powergate_power_on(int id) | ||
122 | { | ||
123 | if (id < 0 || id >= tegra_num_powerdomains) | ||
124 | return -EINVAL; | ||
125 | |||
126 | return tegra_powergate_set(id, true); | ||
127 | } | ||
128 | |||
129 | int tegra_powergate_power_off(int id) | ||
130 | { | ||
131 | if (id < 0 || id >= tegra_num_powerdomains) | ||
132 | return -EINVAL; | ||
133 | |||
134 | return tegra_powergate_set(id, false); | ||
135 | } | ||
136 | EXPORT_SYMBOL(tegra_powergate_power_off); | ||
137 | |||
138 | int tegra_powergate_is_powered(int id) | ||
139 | { | ||
140 | u32 status; | ||
141 | |||
142 | if (id < 0 || id >= tegra_num_powerdomains) | ||
143 | return -EINVAL; | ||
144 | |||
145 | status = pmc_read(PWRGATE_STATUS) & (1 << id); | ||
146 | return !!status; | ||
147 | } | ||
148 | |||
149 | int tegra_powergate_remove_clamping(int id) | ||
150 | { | ||
151 | u32 mask; | ||
152 | |||
153 | if (id < 0 || id >= tegra_num_powerdomains) | ||
154 | return -EINVAL; | ||
155 | |||
156 | /* | ||
157 | * The Tegra124 GPU has a separate register (with different semantics) | ||
158 | * to remove clamps. | ||
159 | */ | ||
160 | if (tegra_chip_id == TEGRA124) { | ||
161 | if (id == TEGRA_POWERGATE_3D) { | ||
162 | pmc_write(0, GPU_RG_CNTRL); | ||
163 | return 0; | ||
164 | } | ||
165 | } | ||
166 | |||
167 | /* | ||
168 | * Tegra 2 has a bug where PCIE and VDE clamping masks are | ||
169 | * swapped relatively to the partition ids | ||
170 | */ | ||
171 | if (id == TEGRA_POWERGATE_VDEC) | ||
172 | mask = (1 << TEGRA_POWERGATE_PCIE); | ||
173 | else if (id == TEGRA_POWERGATE_PCIE) | ||
174 | mask = (1 << TEGRA_POWERGATE_VDEC); | ||
175 | else | ||
176 | mask = (1 << id); | ||
177 | |||
178 | pmc_write(mask, REMOVE_CLAMPING); | ||
179 | |||
180 | return 0; | ||
181 | } | ||
182 | EXPORT_SYMBOL(tegra_powergate_remove_clamping); | ||
183 | |||
184 | /* Must be called with clk disabled, and returns with clk enabled */ | ||
185 | int tegra_powergate_sequence_power_up(int id, struct clk *clk, | ||
186 | struct reset_control *rst) | ||
187 | { | ||
188 | int ret; | ||
189 | |||
190 | reset_control_assert(rst); | ||
191 | |||
192 | ret = tegra_powergate_power_on(id); | ||
193 | if (ret) | ||
194 | goto err_power; | ||
195 | |||
196 | ret = clk_prepare_enable(clk); | ||
197 | if (ret) | ||
198 | goto err_clk; | ||
199 | |||
200 | udelay(10); | ||
201 | |||
202 | ret = tegra_powergate_remove_clamping(id); | ||
203 | if (ret) | ||
204 | goto err_clamp; | ||
205 | |||
206 | udelay(10); | ||
207 | reset_control_deassert(rst); | ||
208 | |||
209 | return 0; | ||
210 | |||
211 | err_clamp: | ||
212 | clk_disable_unprepare(clk); | ||
213 | err_clk: | ||
214 | tegra_powergate_power_off(id); | ||
215 | err_power: | ||
216 | return ret; | ||
217 | } | ||
218 | EXPORT_SYMBOL(tegra_powergate_sequence_power_up); | ||
219 | |||
220 | int tegra_cpu_powergate_id(int cpuid) | ||
221 | { | ||
222 | if (cpuid > 0 && cpuid < tegra_num_cpu_domains) | ||
223 | return tegra_cpu_domains[cpuid]; | ||
224 | |||
225 | return -EINVAL; | ||
226 | } | ||
227 | |||
228 | int __init tegra_powergate_init(void) | ||
229 | { | ||
230 | switch (tegra_chip_id) { | ||
231 | case TEGRA20: | ||
232 | tegra_num_powerdomains = 7; | ||
233 | break; | ||
234 | case TEGRA30: | ||
235 | tegra_num_powerdomains = 14; | ||
236 | tegra_num_cpu_domains = 4; | ||
237 | tegra_cpu_domains = tegra30_cpu_domains; | ||
238 | break; | ||
239 | case TEGRA114: | ||
240 | tegra_num_powerdomains = 23; | ||
241 | tegra_num_cpu_domains = 4; | ||
242 | tegra_cpu_domains = tegra114_cpu_domains; | ||
243 | break; | ||
244 | case TEGRA124: | ||
245 | tegra_num_powerdomains = 25; | ||
246 | tegra_num_cpu_domains = 4; | ||
247 | tegra_cpu_domains = tegra124_cpu_domains; | ||
248 | break; | ||
249 | default: | ||
250 | /* Unknown Tegra variant. Disable powergating */ | ||
251 | tegra_num_powerdomains = 0; | ||
252 | break; | ||
253 | } | ||
254 | |||
255 | return 0; | ||
256 | } | ||
257 | |||
258 | #ifdef CONFIG_DEBUG_FS | ||
259 | |||
260 | static const char * const *powergate_name; | ||
261 | |||
262 | static const char * const powergate_name_t20[] = { | ||
263 | [TEGRA_POWERGATE_CPU] = "cpu", | ||
264 | [TEGRA_POWERGATE_3D] = "3d", | ||
265 | [TEGRA_POWERGATE_VENC] = "venc", | ||
266 | [TEGRA_POWERGATE_VDEC] = "vdec", | ||
267 | [TEGRA_POWERGATE_PCIE] = "pcie", | ||
268 | [TEGRA_POWERGATE_L2] = "l2", | ||
269 | [TEGRA_POWERGATE_MPE] = "mpe", | ||
270 | }; | ||
271 | |||
272 | static const char * const powergate_name_t30[] = { | ||
273 | [TEGRA_POWERGATE_CPU] = "cpu0", | ||
274 | [TEGRA_POWERGATE_3D] = "3d0", | ||
275 | [TEGRA_POWERGATE_VENC] = "venc", | ||
276 | [TEGRA_POWERGATE_VDEC] = "vdec", | ||
277 | [TEGRA_POWERGATE_PCIE] = "pcie", | ||
278 | [TEGRA_POWERGATE_L2] = "l2", | ||
279 | [TEGRA_POWERGATE_MPE] = "mpe", | ||
280 | [TEGRA_POWERGATE_HEG] = "heg", | ||
281 | [TEGRA_POWERGATE_SATA] = "sata", | ||
282 | [TEGRA_POWERGATE_CPU1] = "cpu1", | ||
283 | [TEGRA_POWERGATE_CPU2] = "cpu2", | ||
284 | [TEGRA_POWERGATE_CPU3] = "cpu3", | ||
285 | [TEGRA_POWERGATE_CELP] = "celp", | ||
286 | [TEGRA_POWERGATE_3D1] = "3d1", | ||
287 | }; | ||
288 | |||
289 | static const char * const powergate_name_t114[] = { | ||
290 | [TEGRA_POWERGATE_CPU] = "crail", | ||
291 | [TEGRA_POWERGATE_3D] = "3d", | ||
292 | [TEGRA_POWERGATE_VENC] = "venc", | ||
293 | [TEGRA_POWERGATE_VDEC] = "vdec", | ||
294 | [TEGRA_POWERGATE_MPE] = "mpe", | ||
295 | [TEGRA_POWERGATE_HEG] = "heg", | ||
296 | [TEGRA_POWERGATE_CPU1] = "cpu1", | ||
297 | [TEGRA_POWERGATE_CPU2] = "cpu2", | ||
298 | [TEGRA_POWERGATE_CPU3] = "cpu3", | ||
299 | [TEGRA_POWERGATE_CELP] = "celp", | ||
300 | [TEGRA_POWERGATE_CPU0] = "cpu0", | ||
301 | [TEGRA_POWERGATE_C0NC] = "c0nc", | ||
302 | [TEGRA_POWERGATE_C1NC] = "c1nc", | ||
303 | [TEGRA_POWERGATE_DIS] = "dis", | ||
304 | [TEGRA_POWERGATE_DISB] = "disb", | ||
305 | [TEGRA_POWERGATE_XUSBA] = "xusba", | ||
306 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | ||
307 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | ||
308 | }; | ||
309 | |||
310 | static const char * const powergate_name_t124[] = { | ||
311 | [TEGRA_POWERGATE_CPU] = "crail", | ||
312 | [TEGRA_POWERGATE_3D] = "3d", | ||
313 | [TEGRA_POWERGATE_VENC] = "venc", | ||
314 | [TEGRA_POWERGATE_PCIE] = "pcie", | ||
315 | [TEGRA_POWERGATE_VDEC] = "vdec", | ||
316 | [TEGRA_POWERGATE_L2] = "l2", | ||
317 | [TEGRA_POWERGATE_MPE] = "mpe", | ||
318 | [TEGRA_POWERGATE_HEG] = "heg", | ||
319 | [TEGRA_POWERGATE_SATA] = "sata", | ||
320 | [TEGRA_POWERGATE_CPU1] = "cpu1", | ||
321 | [TEGRA_POWERGATE_CPU2] = "cpu2", | ||
322 | [TEGRA_POWERGATE_CPU3] = "cpu3", | ||
323 | [TEGRA_POWERGATE_CELP] = "celp", | ||
324 | [TEGRA_POWERGATE_CPU0] = "cpu0", | ||
325 | [TEGRA_POWERGATE_C0NC] = "c0nc", | ||
326 | [TEGRA_POWERGATE_C1NC] = "c1nc", | ||
327 | [TEGRA_POWERGATE_SOR] = "sor", | ||
328 | [TEGRA_POWERGATE_DIS] = "dis", | ||
329 | [TEGRA_POWERGATE_DISB] = "disb", | ||
330 | [TEGRA_POWERGATE_XUSBA] = "xusba", | ||
331 | [TEGRA_POWERGATE_XUSBB] = "xusbb", | ||
332 | [TEGRA_POWERGATE_XUSBC] = "xusbc", | ||
333 | [TEGRA_POWERGATE_VIC] = "vic", | ||
334 | [TEGRA_POWERGATE_IRAM] = "iram", | ||
335 | }; | ||
336 | |||
337 | static int powergate_show(struct seq_file *s, void *data) | ||
338 | { | ||
339 | int i; | ||
340 | |||
341 | seq_printf(s, " powergate powered\n"); | ||
342 | seq_printf(s, "------------------\n"); | ||
343 | |||
344 | for (i = 0; i < tegra_num_powerdomains; i++) { | ||
345 | if (!powergate_name[i]) | ||
346 | continue; | ||
347 | |||
348 | seq_printf(s, " %9s %7s\n", powergate_name[i], | ||
349 | tegra_powergate_is_powered(i) ? "yes" : "no"); | ||
350 | } | ||
351 | |||
352 | return 0; | ||
353 | } | ||
354 | |||
355 | static int powergate_open(struct inode *inode, struct file *file) | ||
356 | { | ||
357 | return single_open(file, powergate_show, inode->i_private); | ||
358 | } | ||
359 | |||
360 | static const struct file_operations powergate_fops = { | ||
361 | .open = powergate_open, | ||
362 | .read = seq_read, | ||
363 | .llseek = seq_lseek, | ||
364 | .release = single_release, | ||
365 | }; | ||
366 | |||
367 | int __init tegra_powergate_debugfs_init(void) | ||
368 | { | ||
369 | struct dentry *d; | ||
370 | |||
371 | switch (tegra_chip_id) { | ||
372 | case TEGRA20: | ||
373 | powergate_name = powergate_name_t20; | ||
374 | break; | ||
375 | case TEGRA30: | ||
376 | powergate_name = powergate_name_t30; | ||
377 | break; | ||
378 | case TEGRA114: | ||
379 | powergate_name = powergate_name_t114; | ||
380 | break; | ||
381 | case TEGRA124: | ||
382 | powergate_name = powergate_name_t124; | ||
383 | break; | ||
384 | } | ||
385 | |||
386 | if (powergate_name) { | ||
387 | d = debugfs_create_file("powergate", S_IRUGO, NULL, NULL, | ||
388 | &powergate_fops); | ||
389 | if (!d) | ||
390 | return -ENOMEM; | ||
391 | } | ||
392 | |||
393 | return 0; | ||
394 | } | ||
395 | |||
396 | #endif | ||
397 | |||
398 | static int tegra_io_rail_prepare(int id, unsigned long *request, | ||
399 | unsigned long *status, unsigned int *bit) | ||
400 | { | ||
401 | unsigned long rate, value; | ||
402 | struct clk *clk; | ||
403 | |||
404 | *bit = id % 32; | ||
405 | |||
406 | /* | ||
407 | * There are two sets of 30 bits to select IO rails, but bits 30 and | ||
408 | * 31 are control bits rather than IO rail selection bits. | ||
409 | */ | ||
410 | if (id > 63 || *bit == 30 || *bit == 31) | ||
411 | return -EINVAL; | ||
412 | |||
413 | if (id < 32) { | ||
414 | *status = IO_DPD_STATUS; | ||
415 | *request = IO_DPD_REQ; | ||
416 | } else { | ||
417 | *status = IO_DPD2_STATUS; | ||
418 | *request = IO_DPD2_REQ; | ||
419 | } | ||
420 | |||
421 | clk = clk_get_sys(NULL, "pclk"); | ||
422 | if (IS_ERR(clk)) | ||
423 | return PTR_ERR(clk); | ||
424 | |||
425 | rate = clk_get_rate(clk); | ||
426 | clk_put(clk); | ||
427 | |||
428 | pmc_write(DPD_SAMPLE_ENABLE, DPD_SAMPLE); | ||
429 | |||
430 | /* must be at least 200 ns, in APB (PCLK) clock cycles */ | ||
431 | value = DIV_ROUND_UP(1000000000, rate); | ||
432 | value = DIV_ROUND_UP(200, value); | ||
433 | pmc_write(value, SEL_DPD_TIM); | ||
434 | |||
435 | return 0; | ||
436 | } | ||
437 | |||
438 | static int tegra_io_rail_poll(unsigned long offset, unsigned long mask, | ||
439 | unsigned long val, unsigned long timeout) | ||
440 | { | ||
441 | unsigned long value; | ||
442 | |||
443 | timeout = jiffies + msecs_to_jiffies(timeout); | ||
444 | |||
445 | while (time_after(timeout, jiffies)) { | ||
446 | value = pmc_read(offset); | ||
447 | if ((value & mask) == val) | ||
448 | return 0; | ||
449 | |||
450 | usleep_range(250, 1000); | ||
451 | } | ||
452 | |||
453 | return -ETIMEDOUT; | ||
454 | } | ||
455 | |||
456 | static void tegra_io_rail_unprepare(void) | ||
457 | { | ||
458 | pmc_write(DPD_SAMPLE_DISABLE, DPD_SAMPLE); | ||
459 | } | ||
460 | |||
461 | int tegra_io_rail_power_on(int id) | ||
462 | { | ||
463 | unsigned long request, status, value; | ||
464 | unsigned int bit, mask; | ||
465 | int err; | ||
466 | |||
467 | err = tegra_io_rail_prepare(id, &request, &status, &bit); | ||
468 | if (err < 0) | ||
469 | return err; | ||
470 | |||
471 | mask = 1 << bit; | ||
472 | |||
473 | value = pmc_read(request); | ||
474 | value |= mask; | ||
475 | value &= ~IO_DPD_REQ_CODE_MASK; | ||
476 | value |= IO_DPD_REQ_CODE_OFF; | ||
477 | pmc_write(value, request); | ||
478 | |||
479 | err = tegra_io_rail_poll(status, mask, 0, 250); | ||
480 | if (err < 0) | ||
481 | return err; | ||
482 | |||
483 | tegra_io_rail_unprepare(); | ||
484 | |||
485 | return 0; | ||
486 | } | ||
487 | EXPORT_SYMBOL(tegra_io_rail_power_on); | ||
488 | |||
489 | int tegra_io_rail_power_off(int id) | ||
490 | { | ||
491 | unsigned long request, status, value; | ||
492 | unsigned int bit, mask; | ||
493 | int err; | ||
494 | |||
495 | err = tegra_io_rail_prepare(id, &request, &status, &bit); | ||
496 | if (err < 0) | ||
497 | return err; | ||
498 | |||
499 | mask = 1 << bit; | ||
500 | |||
501 | value = pmc_read(request); | ||
502 | value |= mask; | ||
503 | value &= ~IO_DPD_REQ_CODE_MASK; | ||
504 | value |= IO_DPD_REQ_CODE_ON; | ||
505 | pmc_write(value, request); | ||
506 | |||
507 | err = tegra_io_rail_poll(status, mask, mask, 250); | ||
508 | if (err < 0) | ||
509 | return err; | ||
510 | |||
511 | tegra_io_rail_unprepare(); | ||
512 | |||
513 | return 0; | ||
514 | } | ||
515 | EXPORT_SYMBOL(tegra_io_rail_power_off); | ||
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S index 578d4d1ad648..7b2baab0f0bd 100644 --- a/arch/arm/mach-tegra/reset-handler.S +++ b/arch/arm/mach-tegra/reset-handler.S | |||
@@ -14,14 +14,15 @@ | |||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/linkage.h> | ||
18 | #include <linux/init.h> | 17 | #include <linux/init.h> |
18 | #include <linux/linkage.h> | ||
19 | |||
20 | #include <soc/tegra/fuse.h> | ||
19 | 21 | ||
20 | #include <asm/cache.h> | ||
21 | #include <asm/asm-offsets.h> | 22 | #include <asm/asm-offsets.h> |
23 | #include <asm/cache.h> | ||
22 | 24 | ||
23 | #include "flowctrl.h" | 25 | #include "flowctrl.h" |
24 | #include "fuse.h" | ||
25 | #include "iomap.h" | 26 | #include "iomap.h" |
26 | #include "reset.h" | 27 | #include "reset.h" |
27 | #include "sleep.h" | 28 | #include "sleep.h" |
diff --git a/arch/arm/mach-tegra/reset.c b/arch/arm/mach-tegra/reset.c index 146fe8e0ae7c..894c5c472184 100644 --- a/arch/arm/mach-tegra/reset.c +++ b/arch/arm/mach-tegra/reset.c | |||
@@ -14,20 +14,21 @@ | |||
14 | * | 14 | * |
15 | */ | 15 | */ |
16 | 16 | ||
17 | #include <linux/bitops.h> | ||
18 | #include <linux/cpumask.h> | ||
17 | #include <linux/init.h> | 19 | #include <linux/init.h> |
18 | #include <linux/io.h> | 20 | #include <linux/io.h> |
19 | #include <linux/cpumask.h> | 21 | |
20 | #include <linux/bitops.h> | 22 | #include <soc/tegra/fuse.h> |
21 | 23 | ||
22 | #include <asm/cacheflush.h> | 24 | #include <asm/cacheflush.h> |
23 | #include <asm/hardware/cache-l2x0.h> | ||
24 | #include <asm/firmware.h> | 25 | #include <asm/firmware.h> |
26 | #include <asm/hardware/cache-l2x0.h> | ||
25 | 27 | ||
26 | #include "iomap.h" | 28 | #include "iomap.h" |
27 | #include "irammap.h" | 29 | #include "irammap.h" |
28 | #include "reset.h" | 30 | #include "reset.h" |
29 | #include "sleep.h" | 31 | #include "sleep.h" |
30 | #include "fuse.h" | ||
31 | 32 | ||
32 | #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \ | 33 | #define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \ |
33 | TEGRA_IRAM_RESET_HANDLER_OFFSET) | 34 | TEGRA_IRAM_RESET_HANDLER_OFFSET) |
@@ -53,12 +54,10 @@ static void __init tegra_cpu_reset_handler_set(const u32 reset_address) | |||
53 | * Prevent further modifications to the physical reset vector. | 54 | * Prevent further modifications to the physical reset vector. |
54 | * NOTE: Has no effect on chips prior to Tegra30. | 55 | * NOTE: Has no effect on chips prior to Tegra30. |
55 | */ | 56 | */ |
56 | if (tegra_chip_id != TEGRA20) { | 57 | reg = readl(sb_ctrl); |
57 | reg = readl(sb_ctrl); | 58 | reg |= 2; |
58 | reg |= 2; | 59 | writel(reg, sb_ctrl); |
59 | writel(reg, sb_ctrl); | 60 | wmb(); |
60 | wmb(); | ||
61 | } | ||
62 | } | 61 | } |
63 | 62 | ||
64 | static void __init tegra_cpu_reset_handler_enable(void) | 63 | static void __init tegra_cpu_reset_handler_enable(void) |
diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S index 09cad9b071de..5d8d13aeab93 100644 --- a/arch/arm/mach-tegra/sleep-tegra30.S +++ b/arch/arm/mach-tegra/sleep-tegra30.S | |||
@@ -16,14 +16,15 @@ | |||
16 | 16 | ||
17 | #include <linux/linkage.h> | 17 | #include <linux/linkage.h> |
18 | 18 | ||
19 | #include <asm/assembler.h> | 19 | #include <soc/tegra/fuse.h> |
20 | |||
20 | #include <asm/asm-offsets.h> | 21 | #include <asm/asm-offsets.h> |
22 | #include <asm/assembler.h> | ||
21 | #include <asm/cache.h> | 23 | #include <asm/cache.h> |
22 | 24 | ||
25 | #include "flowctrl.h" | ||
23 | #include "irammap.h" | 26 | #include "irammap.h" |
24 | #include "fuse.h" | ||
25 | #include "sleep.h" | 27 | #include "sleep.h" |
26 | #include "flowctrl.h" | ||
27 | 28 | ||
28 | #define EMC_CFG 0xc | 29 | #define EMC_CFG 0xc |
29 | #define EMC_ADR_CFG 0x10 | 30 | #define EMC_ADR_CFG 0x10 |
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h index 339fe42cd6fb..92d46ec1361a 100644 --- a/arch/arm/mach-tegra/sleep.h +++ b/arch/arm/mach-tegra/sleep.h | |||
@@ -130,9 +130,6 @@ void tegra_disable_clean_inv_dcache(u32 flag); | |||
130 | #ifdef CONFIG_HOTPLUG_CPU | 130 | #ifdef CONFIG_HOTPLUG_CPU |
131 | void tegra20_hotplug_shutdown(void); | 131 | void tegra20_hotplug_shutdown(void); |
132 | void tegra30_hotplug_shutdown(void); | 132 | void tegra30_hotplug_shutdown(void); |
133 | void tegra_hotplug_init(void); | ||
134 | #else | ||
135 | static inline void tegra_hotplug_init(void) {} | ||
136 | #endif | 133 | #endif |
137 | 134 | ||
138 | void tegra20_cpu_shutdown(int cpu); | 135 | void tegra20_cpu_shutdown(int cpu); |
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c index 15ac9fcc96b1..5ef5173dec83 100644 --- a/arch/arm/mach-tegra/tegra.c +++ b/arch/arm/mach-tegra/tegra.c | |||
@@ -16,40 +16,40 @@ | |||
16 | * | 16 | * |
17 | */ | 17 | */ |
18 | 18 | ||
19 | #include <linux/kernel.h> | ||
20 | #include <linux/init.h> | ||
21 | #include <linux/platform_device.h> | ||
22 | #include <linux/serial_8250.h> | ||
23 | #include <linux/clk.h> | 19 | #include <linux/clk.h> |
20 | #include <linux/clk/tegra.h> | ||
24 | #include <linux/dma-mapping.h> | 21 | #include <linux/dma-mapping.h> |
22 | #include <linux/init.h> | ||
23 | #include <linux/io.h> | ||
24 | #include <linux/irqchip.h> | ||
25 | #include <linux/irqdomain.h> | 25 | #include <linux/irqdomain.h> |
26 | #include <linux/of.h> | 26 | #include <linux/kernel.h> |
27 | #include <linux/of_address.h> | 27 | #include <linux/of_address.h> |
28 | #include <linux/of_fdt.h> | 28 | #include <linux/of_fdt.h> |
29 | #include <linux/of.h> | ||
29 | #include <linux/of_platform.h> | 30 | #include <linux/of_platform.h> |
30 | #include <linux/pda_power.h> | 31 | #include <linux/pda_power.h> |
31 | #include <linux/io.h> | 32 | #include <linux/platform_device.h> |
33 | #include <linux/serial_8250.h> | ||
32 | #include <linux/slab.h> | 34 | #include <linux/slab.h> |
33 | #include <linux/sys_soc.h> | 35 | #include <linux/sys_soc.h> |
34 | #include <linux/usb/tegra_usb_phy.h> | 36 | #include <linux/usb/tegra_usb_phy.h> |
35 | #include <linux/clk/tegra.h> | 37 | |
36 | #include <linux/irqchip.h> | 38 | #include <soc/tegra/fuse.h> |
39 | #include <soc/tegra/pmc.h> | ||
37 | 40 | ||
38 | #include <asm/hardware/cache-l2x0.h> | 41 | #include <asm/hardware/cache-l2x0.h> |
39 | #include <asm/mach-types.h> | ||
40 | #include <asm/mach/arch.h> | 42 | #include <asm/mach/arch.h> |
41 | #include <asm/mach/time.h> | 43 | #include <asm/mach/time.h> |
44 | #include <asm/mach-types.h> | ||
42 | #include <asm/setup.h> | 45 | #include <asm/setup.h> |
43 | #include <asm/trusted_foundations.h> | 46 | #include <asm/trusted_foundations.h> |
44 | 47 | ||
45 | #include "apbio.h" | ||
46 | #include "board.h" | 48 | #include "board.h" |
47 | #include "common.h" | 49 | #include "common.h" |
48 | #include "cpuidle.h" | 50 | #include "cpuidle.h" |
49 | #include "fuse.h" | ||
50 | #include "iomap.h" | 51 | #include "iomap.h" |
51 | #include "irq.h" | 52 | #include "irq.h" |
52 | #include "pmc.h" | ||
53 | #include "pm.h" | 53 | #include "pm.h" |
54 | #include "reset.h" | 54 | #include "reset.h" |
55 | #include "sleep.h" | 55 | #include "sleep.h" |
@@ -73,16 +73,11 @@ u32 tegra_uart_config[3] = { | |||
73 | static void __init tegra_init_early(void) | 73 | static void __init tegra_init_early(void) |
74 | { | 74 | { |
75 | of_register_trusted_foundations(); | 75 | of_register_trusted_foundations(); |
76 | tegra_apb_io_init(); | ||
77 | tegra_init_fuse(); | ||
78 | tegra_cpu_reset_handler_init(); | 76 | tegra_cpu_reset_handler_init(); |
79 | tegra_powergate_init(); | ||
80 | tegra_hotplug_init(); | ||
81 | } | 77 | } |
82 | 78 | ||
83 | static void __init tegra_dt_init_irq(void) | 79 | static void __init tegra_dt_init_irq(void) |
84 | { | 80 | { |
85 | tegra_pmc_init_irq(); | ||
86 | tegra_init_irq(); | 81 | tegra_init_irq(); |
87 | irqchip_init(); | 82 | irqchip_init(); |
88 | tegra_legacy_irq_syscore_init(); | 83 | tegra_legacy_irq_syscore_init(); |
@@ -94,8 +89,6 @@ static void __init tegra_dt_init(void) | |||
94 | struct soc_device *soc_dev; | 89 | struct soc_device *soc_dev; |
95 | struct device *parent = NULL; | 90 | struct device *parent = NULL; |
96 | 91 | ||
97 | tegra_pmc_init(); | ||
98 | |||
99 | tegra_clocks_apply_init_table(); | 92 | tegra_clocks_apply_init_table(); |
100 | 93 | ||
101 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); | 94 | soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL); |
@@ -103,8 +96,9 @@ static void __init tegra_dt_init(void) | |||
103 | goto out; | 96 | goto out; |
104 | 97 | ||
105 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); | 98 | soc_dev_attr->family = kasprintf(GFP_KERNEL, "Tegra"); |
106 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", tegra_revision); | 99 | soc_dev_attr->revision = kasprintf(GFP_KERNEL, "%d", |
107 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%d", tegra_chip_id); | 100 | tegra_sku_info.revision); |
101 | soc_dev_attr->soc_id = kasprintf(GFP_KERNEL, "%u", tegra_get_chip_id()); | ||
108 | 102 | ||
109 | soc_dev = soc_device_register(soc_dev_attr); | 103 | soc_dev = soc_device_register(soc_dev_attr); |
110 | if (IS_ERR(soc_dev)) { | 104 | if (IS_ERR(soc_dev)) { |
@@ -144,7 +138,6 @@ static void __init tegra_dt_init_late(void) | |||
144 | 138 | ||
145 | tegra_init_suspend(); | 139 | tegra_init_suspend(); |
146 | tegra_cpuidle_init(); | 140 | tegra_cpuidle_init(); |
147 | tegra_powergate_debugfs_init(); | ||
148 | 141 | ||
149 | for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { | 142 | for (i = 0; i < ARRAY_SIZE(board_init_funcs); i++) { |
150 | if (of_machine_is_compatible(board_init_funcs[i].machine)) { | 143 | if (of_machine_is_compatible(board_init_funcs[i].machine)) { |
diff --git a/arch/arm/mach-tegra/tegra114_speedo.c b/arch/arm/mach-tegra/tegra114_speedo.c deleted file mode 100644 index 5218d4853cd3..000000000000 --- a/arch/arm/mach-tegra/tegra114_speedo.c +++ /dev/null | |||
@@ -1,104 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/bug.h> | ||
19 | |||
20 | #include "fuse.h" | ||
21 | |||
22 | #define CORE_PROCESS_CORNERS_NUM 2 | ||
23 | #define CPU_PROCESS_CORNERS_NUM 2 | ||
24 | |||
25 | enum { | ||
26 | THRESHOLD_INDEX_0, | ||
27 | THRESHOLD_INDEX_1, | ||
28 | THRESHOLD_INDEX_COUNT, | ||
29 | }; | ||
30 | |||
31 | static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { | ||
32 | {1123, UINT_MAX}, | ||
33 | {0, UINT_MAX}, | ||
34 | }; | ||
35 | |||
36 | static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { | ||
37 | {1695, UINT_MAX}, | ||
38 | {0, UINT_MAX}, | ||
39 | }; | ||
40 | |||
41 | static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold) | ||
42 | { | ||
43 | u32 tmp; | ||
44 | |||
45 | switch (sku) { | ||
46 | case 0x00: | ||
47 | case 0x10: | ||
48 | case 0x05: | ||
49 | case 0x06: | ||
50 | tegra_cpu_speedo_id = 1; | ||
51 | tegra_soc_speedo_id = 0; | ||
52 | *threshold = THRESHOLD_INDEX_0; | ||
53 | break; | ||
54 | |||
55 | case 0x03: | ||
56 | case 0x04: | ||
57 | tegra_cpu_speedo_id = 2; | ||
58 | tegra_soc_speedo_id = 1; | ||
59 | *threshold = THRESHOLD_INDEX_1; | ||
60 | break; | ||
61 | |||
62 | default: | ||
63 | pr_err("Tegra114 Unknown SKU %d\n", sku); | ||
64 | tegra_cpu_speedo_id = 0; | ||
65 | tegra_soc_speedo_id = 0; | ||
66 | *threshold = THRESHOLD_INDEX_0; | ||
67 | break; | ||
68 | } | ||
69 | |||
70 | if (rev == TEGRA_REVISION_A01) { | ||
71 | tmp = tegra_fuse_readl(0x270) << 1; | ||
72 | tmp |= tegra_fuse_readl(0x26c); | ||
73 | if (!tmp) | ||
74 | tegra_cpu_speedo_id = 0; | ||
75 | } | ||
76 | } | ||
77 | |||
78 | void tegra114_init_speedo_data(void) | ||
79 | { | ||
80 | u32 cpu_speedo_val; | ||
81 | u32 core_speedo_val; | ||
82 | int threshold; | ||
83 | int i; | ||
84 | |||
85 | BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != | ||
86 | THRESHOLD_INDEX_COUNT); | ||
87 | BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != | ||
88 | THRESHOLD_INDEX_COUNT); | ||
89 | |||
90 | rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold); | ||
91 | |||
92 | cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024; | ||
93 | core_speedo_val = tegra_fuse_readl(0x134); | ||
94 | |||
95 | for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) | ||
96 | if (cpu_speedo_val < cpu_process_speedos[threshold][i]) | ||
97 | break; | ||
98 | tegra_cpu_process_id = i; | ||
99 | |||
100 | for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) | ||
101 | if (core_speedo_val < core_process_speedos[threshold][i]) | ||
102 | break; | ||
103 | tegra_core_process_id = i; | ||
104 | } | ||
diff --git a/arch/arm/mach-tegra/tegra20_speedo.c b/arch/arm/mach-tegra/tegra20_speedo.c deleted file mode 100644 index fa6eb570623f..000000000000 --- a/arch/arm/mach-tegra/tegra20_speedo.c +++ /dev/null | |||
@@ -1,109 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/bug.h> | ||
19 | |||
20 | #include "fuse.h" | ||
21 | |||
22 | #define CPU_SPEEDO_LSBIT 20 | ||
23 | #define CPU_SPEEDO_MSBIT 29 | ||
24 | #define CPU_SPEEDO_REDUND_LSBIT 30 | ||
25 | #define CPU_SPEEDO_REDUND_MSBIT 39 | ||
26 | #define CPU_SPEEDO_REDUND_OFFS (CPU_SPEEDO_REDUND_MSBIT - CPU_SPEEDO_MSBIT) | ||
27 | |||
28 | #define CORE_SPEEDO_LSBIT 40 | ||
29 | #define CORE_SPEEDO_MSBIT 47 | ||
30 | #define CORE_SPEEDO_REDUND_LSBIT 48 | ||
31 | #define CORE_SPEEDO_REDUND_MSBIT 55 | ||
32 | #define CORE_SPEEDO_REDUND_OFFS (CORE_SPEEDO_REDUND_MSBIT - CORE_SPEEDO_MSBIT) | ||
33 | |||
34 | #define SPEEDO_MULT 4 | ||
35 | |||
36 | #define PROCESS_CORNERS_NUM 4 | ||
37 | |||
38 | #define SPEEDO_ID_SELECT_0(rev) ((rev) <= 2) | ||
39 | #define SPEEDO_ID_SELECT_1(sku) \ | ||
40 | (((sku) != 20) && ((sku) != 23) && ((sku) != 24) && \ | ||
41 | ((sku) != 27) && ((sku) != 28)) | ||
42 | |||
43 | enum { | ||
44 | SPEEDO_ID_0, | ||
45 | SPEEDO_ID_1, | ||
46 | SPEEDO_ID_2, | ||
47 | SPEEDO_ID_COUNT, | ||
48 | }; | ||
49 | |||
50 | static const u32 cpu_process_speedos[][PROCESS_CORNERS_NUM] = { | ||
51 | {315, 366, 420, UINT_MAX}, | ||
52 | {303, 368, 419, UINT_MAX}, | ||
53 | {316, 331, 383, UINT_MAX}, | ||
54 | }; | ||
55 | |||
56 | static const u32 core_process_speedos[][PROCESS_CORNERS_NUM] = { | ||
57 | {165, 195, 224, UINT_MAX}, | ||
58 | {165, 195, 224, UINT_MAX}, | ||
59 | {165, 195, 224, UINT_MAX}, | ||
60 | }; | ||
61 | |||
62 | void tegra20_init_speedo_data(void) | ||
63 | { | ||
64 | u32 reg; | ||
65 | u32 val; | ||
66 | int i; | ||
67 | |||
68 | BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != SPEEDO_ID_COUNT); | ||
69 | BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != SPEEDO_ID_COUNT); | ||
70 | |||
71 | if (SPEEDO_ID_SELECT_0(tegra_revision)) | ||
72 | tegra_soc_speedo_id = SPEEDO_ID_0; | ||
73 | else if (SPEEDO_ID_SELECT_1(tegra_sku_id)) | ||
74 | tegra_soc_speedo_id = SPEEDO_ID_1; | ||
75 | else | ||
76 | tegra_soc_speedo_id = SPEEDO_ID_2; | ||
77 | |||
78 | val = 0; | ||
79 | for (i = CPU_SPEEDO_MSBIT; i >= CPU_SPEEDO_LSBIT; i--) { | ||
80 | reg = tegra_spare_fuse(i) | | ||
81 | tegra_spare_fuse(i + CPU_SPEEDO_REDUND_OFFS); | ||
82 | val = (val << 1) | (reg & 0x1); | ||
83 | } | ||
84 | val = val * SPEEDO_MULT; | ||
85 | pr_debug("%s CPU speedo value %u\n", __func__, val); | ||
86 | |||
87 | for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) { | ||
88 | if (val <= cpu_process_speedos[tegra_soc_speedo_id][i]) | ||
89 | break; | ||
90 | } | ||
91 | tegra_cpu_process_id = i; | ||
92 | |||
93 | val = 0; | ||
94 | for (i = CORE_SPEEDO_MSBIT; i >= CORE_SPEEDO_LSBIT; i--) { | ||
95 | reg = tegra_spare_fuse(i) | | ||
96 | tegra_spare_fuse(i + CORE_SPEEDO_REDUND_OFFS); | ||
97 | val = (val << 1) | (reg & 0x1); | ||
98 | } | ||
99 | val = val * SPEEDO_MULT; | ||
100 | pr_debug("%s Core speedo value %u\n", __func__, val); | ||
101 | |||
102 | for (i = 0; i < (PROCESS_CORNERS_NUM - 1); i++) { | ||
103 | if (val <= core_process_speedos[tegra_soc_speedo_id][i]) | ||
104 | break; | ||
105 | } | ||
106 | tegra_core_process_id = i; | ||
107 | |||
108 | pr_info("Tegra20 Soc Speedo ID %d", tegra_soc_speedo_id); | ||
109 | } | ||
diff --git a/arch/arm/mach-tegra/tegra30_speedo.c b/arch/arm/mach-tegra/tegra30_speedo.c deleted file mode 100644 index 125cb16424a6..000000000000 --- a/arch/arm/mach-tegra/tegra30_speedo.c +++ /dev/null | |||
@@ -1,292 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/kernel.h> | ||
18 | #include <linux/bug.h> | ||
19 | |||
20 | #include "fuse.h" | ||
21 | |||
22 | #define CORE_PROCESS_CORNERS_NUM 1 | ||
23 | #define CPU_PROCESS_CORNERS_NUM 6 | ||
24 | |||
25 | #define FUSE_SPEEDO_CALIB_0 0x114 | ||
26 | #define FUSE_PACKAGE_INFO 0X1FC | ||
27 | #define FUSE_TEST_PROG_VER 0X128 | ||
28 | |||
29 | #define G_SPEEDO_BIT_MINUS1 58 | ||
30 | #define G_SPEEDO_BIT_MINUS1_R 59 | ||
31 | #define G_SPEEDO_BIT_MINUS2 60 | ||
32 | #define G_SPEEDO_BIT_MINUS2_R 61 | ||
33 | #define LP_SPEEDO_BIT_MINUS1 62 | ||
34 | #define LP_SPEEDO_BIT_MINUS1_R 63 | ||
35 | #define LP_SPEEDO_BIT_MINUS2 64 | ||
36 | #define LP_SPEEDO_BIT_MINUS2_R 65 | ||
37 | |||
38 | enum { | ||
39 | THRESHOLD_INDEX_0, | ||
40 | THRESHOLD_INDEX_1, | ||
41 | THRESHOLD_INDEX_2, | ||
42 | THRESHOLD_INDEX_3, | ||
43 | THRESHOLD_INDEX_4, | ||
44 | THRESHOLD_INDEX_5, | ||
45 | THRESHOLD_INDEX_6, | ||
46 | THRESHOLD_INDEX_7, | ||
47 | THRESHOLD_INDEX_8, | ||
48 | THRESHOLD_INDEX_9, | ||
49 | THRESHOLD_INDEX_10, | ||
50 | THRESHOLD_INDEX_11, | ||
51 | THRESHOLD_INDEX_COUNT, | ||
52 | }; | ||
53 | |||
54 | static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = { | ||
55 | {180}, | ||
56 | {170}, | ||
57 | {195}, | ||
58 | {180}, | ||
59 | {168}, | ||
60 | {192}, | ||
61 | {180}, | ||
62 | {170}, | ||
63 | {195}, | ||
64 | {180}, | ||
65 | {180}, | ||
66 | {180}, | ||
67 | }; | ||
68 | |||
69 | static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = { | ||
70 | {306, 338, 360, 376, UINT_MAX}, | ||
71 | {295, 336, 358, 375, UINT_MAX}, | ||
72 | {325, 325, 358, 375, UINT_MAX}, | ||
73 | {325, 325, 358, 375, UINT_MAX}, | ||
74 | {292, 324, 348, 364, UINT_MAX}, | ||
75 | {324, 324, 348, 364, UINT_MAX}, | ||
76 | {324, 324, 348, 364, UINT_MAX}, | ||
77 | {295, 336, 358, 375, UINT_MAX}, | ||
78 | {358, 358, 358, 358, 397, UINT_MAX}, | ||
79 | {364, 364, 364, 364, 397, UINT_MAX}, | ||
80 | {295, 336, 358, 375, 391, UINT_MAX}, | ||
81 | {295, 336, 358, 375, 391, UINT_MAX}, | ||
82 | }; | ||
83 | |||
84 | static int threshold_index; | ||
85 | static int package_id; | ||
86 | |||
87 | static void fuse_speedo_calib(u32 *speedo_g, u32 *speedo_lp) | ||
88 | { | ||
89 | u32 reg; | ||
90 | int ate_ver; | ||
91 | int bit_minus1; | ||
92 | int bit_minus2; | ||
93 | |||
94 | reg = tegra_fuse_readl(FUSE_SPEEDO_CALIB_0); | ||
95 | |||
96 | *speedo_lp = (reg & 0xFFFF) * 4; | ||
97 | *speedo_g = ((reg >> 16) & 0xFFFF) * 4; | ||
98 | |||
99 | ate_ver = tegra_fuse_readl(FUSE_TEST_PROG_VER); | ||
100 | pr_info("%s: ATE prog ver %d.%d\n", __func__, ate_ver/10, ate_ver%10); | ||
101 | |||
102 | if (ate_ver >= 26) { | ||
103 | bit_minus1 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1); | ||
104 | bit_minus1 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS1_R); | ||
105 | bit_minus2 = tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2); | ||
106 | bit_minus2 |= tegra_spare_fuse(LP_SPEEDO_BIT_MINUS2_R); | ||
107 | *speedo_lp |= (bit_minus1 << 1) | bit_minus2; | ||
108 | |||
109 | bit_minus1 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS1); | ||
110 | bit_minus1 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS1_R); | ||
111 | bit_minus2 = tegra_spare_fuse(G_SPEEDO_BIT_MINUS2); | ||
112 | bit_minus2 |= tegra_spare_fuse(G_SPEEDO_BIT_MINUS2_R); | ||
113 | *speedo_g |= (bit_minus1 << 1) | bit_minus2; | ||
114 | } else { | ||
115 | *speedo_lp |= 0x3; | ||
116 | *speedo_g |= 0x3; | ||
117 | } | ||
118 | } | ||
119 | |||
120 | static void rev_sku_to_speedo_ids(int rev, int sku) | ||
121 | { | ||
122 | switch (rev) { | ||
123 | case TEGRA_REVISION_A01: | ||
124 | tegra_cpu_speedo_id = 0; | ||
125 | tegra_soc_speedo_id = 0; | ||
126 | threshold_index = THRESHOLD_INDEX_0; | ||
127 | break; | ||
128 | case TEGRA_REVISION_A02: | ||
129 | case TEGRA_REVISION_A03: | ||
130 | switch (sku) { | ||
131 | case 0x87: | ||
132 | case 0x82: | ||
133 | tegra_cpu_speedo_id = 1; | ||
134 | tegra_soc_speedo_id = 1; | ||
135 | threshold_index = THRESHOLD_INDEX_1; | ||
136 | break; | ||
137 | case 0x81: | ||
138 | switch (package_id) { | ||
139 | case 1: | ||
140 | tegra_cpu_speedo_id = 2; | ||
141 | tegra_soc_speedo_id = 2; | ||
142 | threshold_index = THRESHOLD_INDEX_2; | ||
143 | break; | ||
144 | case 2: | ||
145 | tegra_cpu_speedo_id = 4; | ||
146 | tegra_soc_speedo_id = 1; | ||
147 | threshold_index = THRESHOLD_INDEX_7; | ||
148 | break; | ||
149 | default: | ||
150 | pr_err("Tegra30: Unknown pkg %d\n", package_id); | ||
151 | BUG(); | ||
152 | break; | ||
153 | } | ||
154 | break; | ||
155 | case 0x80: | ||
156 | switch (package_id) { | ||
157 | case 1: | ||
158 | tegra_cpu_speedo_id = 5; | ||
159 | tegra_soc_speedo_id = 2; | ||
160 | threshold_index = THRESHOLD_INDEX_8; | ||
161 | break; | ||
162 | case 2: | ||
163 | tegra_cpu_speedo_id = 6; | ||
164 | tegra_soc_speedo_id = 2; | ||
165 | threshold_index = THRESHOLD_INDEX_9; | ||
166 | break; | ||
167 | default: | ||
168 | pr_err("Tegra30: Unknown pkg %d\n", package_id); | ||
169 | BUG(); | ||
170 | break; | ||
171 | } | ||
172 | break; | ||
173 | case 0x83: | ||
174 | switch (package_id) { | ||
175 | case 1: | ||
176 | tegra_cpu_speedo_id = 7; | ||
177 | tegra_soc_speedo_id = 1; | ||
178 | threshold_index = THRESHOLD_INDEX_10; | ||
179 | break; | ||
180 | case 2: | ||
181 | tegra_cpu_speedo_id = 3; | ||
182 | tegra_soc_speedo_id = 2; | ||
183 | threshold_index = THRESHOLD_INDEX_3; | ||
184 | break; | ||
185 | default: | ||
186 | pr_err("Tegra30: Unknown pkg %d\n", package_id); | ||
187 | BUG(); | ||
188 | break; | ||
189 | } | ||
190 | break; | ||
191 | case 0x8F: | ||
192 | tegra_cpu_speedo_id = 8; | ||
193 | tegra_soc_speedo_id = 1; | ||
194 | threshold_index = THRESHOLD_INDEX_11; | ||
195 | break; | ||
196 | case 0x08: | ||
197 | tegra_cpu_speedo_id = 1; | ||
198 | tegra_soc_speedo_id = 1; | ||
199 | threshold_index = THRESHOLD_INDEX_4; | ||
200 | break; | ||
201 | case 0x02: | ||
202 | tegra_cpu_speedo_id = 2; | ||
203 | tegra_soc_speedo_id = 2; | ||
204 | threshold_index = THRESHOLD_INDEX_5; | ||
205 | break; | ||
206 | case 0x04: | ||
207 | tegra_cpu_speedo_id = 3; | ||
208 | tegra_soc_speedo_id = 2; | ||
209 | threshold_index = THRESHOLD_INDEX_6; | ||
210 | break; | ||
211 | case 0: | ||
212 | switch (package_id) { | ||
213 | case 1: | ||
214 | tegra_cpu_speedo_id = 2; | ||
215 | tegra_soc_speedo_id = 2; | ||
216 | threshold_index = THRESHOLD_INDEX_2; | ||
217 | break; | ||
218 | case 2: | ||
219 | tegra_cpu_speedo_id = 3; | ||
220 | tegra_soc_speedo_id = 2; | ||
221 | threshold_index = THRESHOLD_INDEX_3; | ||
222 | break; | ||
223 | default: | ||
224 | pr_err("Tegra30: Unknown pkg %d\n", package_id); | ||
225 | BUG(); | ||
226 | break; | ||
227 | } | ||
228 | break; | ||
229 | default: | ||
230 | pr_warn("Tegra30: Unknown SKU %d\n", sku); | ||
231 | tegra_cpu_speedo_id = 0; | ||
232 | tegra_soc_speedo_id = 0; | ||
233 | threshold_index = THRESHOLD_INDEX_0; | ||
234 | break; | ||
235 | } | ||
236 | break; | ||
237 | default: | ||
238 | pr_warn("Tegra30: Unknown chip rev %d\n", rev); | ||
239 | tegra_cpu_speedo_id = 0; | ||
240 | tegra_soc_speedo_id = 0; | ||
241 | threshold_index = THRESHOLD_INDEX_0; | ||
242 | break; | ||
243 | } | ||
244 | } | ||
245 | |||
246 | void tegra30_init_speedo_data(void) | ||
247 | { | ||
248 | u32 cpu_speedo_val; | ||
249 | u32 core_speedo_val; | ||
250 | int i; | ||
251 | |||
252 | BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) != | ||
253 | THRESHOLD_INDEX_COUNT); | ||
254 | BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) != | ||
255 | THRESHOLD_INDEX_COUNT); | ||
256 | |||
257 | package_id = tegra_fuse_readl(FUSE_PACKAGE_INFO) & 0x0F; | ||
258 | |||
259 | rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id); | ||
260 | fuse_speedo_calib(&cpu_speedo_val, &core_speedo_val); | ||
261 | pr_debug("%s CPU speedo value %u\n", __func__, cpu_speedo_val); | ||
262 | pr_debug("%s Core speedo value %u\n", __func__, core_speedo_val); | ||
263 | |||
264 | for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++) { | ||
265 | if (cpu_speedo_val < cpu_process_speedos[threshold_index][i]) | ||
266 | break; | ||
267 | } | ||
268 | tegra_cpu_process_id = i - 1; | ||
269 | |||
270 | if (tegra_cpu_process_id == -1) { | ||
271 | pr_warn("Tegra30: CPU speedo value %3d out of range", | ||
272 | cpu_speedo_val); | ||
273 | tegra_cpu_process_id = 0; | ||
274 | tegra_cpu_speedo_id = 1; | ||
275 | } | ||
276 | |||
277 | for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++) { | ||
278 | if (core_speedo_val < core_process_speedos[threshold_index][i]) | ||
279 | break; | ||
280 | } | ||
281 | tegra_core_process_id = i - 1; | ||
282 | |||
283 | if (tegra_core_process_id == -1) { | ||
284 | pr_warn("Tegra30: CORE speedo value %3d out of range", | ||
285 | core_speedo_val); | ||
286 | tegra_core_process_id = 0; | ||
287 | tegra_soc_speedo_id = 1; | ||
288 | } | ||
289 | |||
290 | pr_info("Tegra30: CPU Speedo ID %d, Soc Speedo ID %d", | ||
291 | tegra_cpu_speedo_id, tegra_soc_speedo_id); | ||
292 | } | ||
diff --git a/arch/arm/mach-ux500/board-mop500-regulators.c b/arch/arm/mach-ux500/board-mop500-regulators.c index a4e139aa2441..32d744e91ec2 100644 --- a/arch/arm/mach-ux500/board-mop500-regulators.c +++ b/arch/arm/mach-ux500/board-mop500-regulators.c | |||
@@ -796,7 +796,7 @@ static struct ab8500_regulator_reg_init ab8505_reg_init[] = { | |||
796 | INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX6, 0x00, 0x00), | 796 | INIT_REGULATOR_REGISTER(AB8505_CTRLVAUX6, 0x00, 0x00), |
797 | }; | 797 | }; |
798 | 798 | ||
799 | struct regulator_init_data ab8505_regulators[AB8505_NUM_REGULATORS] = { | 799 | static struct regulator_init_data ab8505_regulators[AB8505_NUM_REGULATORS] = { |
800 | /* supplies to the display/camera */ | 800 | /* supplies to the display/camera */ |
801 | [AB8505_LDO_AUX1] = { | 801 | [AB8505_LDO_AUX1] = { |
802 | .constraints = { | 802 | .constraints = { |
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c index 842ebedbdd1c..e97ee556f92f 100644 --- a/arch/arm/mach-ux500/cache-l2x0.c +++ b/arch/arm/mach-ux500/cache-l2x0.c | |||
@@ -7,17 +7,15 @@ | |||
7 | #include <linux/io.h> | 7 | #include <linux/io.h> |
8 | #include <linux/of.h> | 8 | #include <linux/of.h> |
9 | 9 | ||
10 | #include <asm/cacheflush.h> | ||
11 | #include <asm/hardware/cache-l2x0.h> | 10 | #include <asm/hardware/cache-l2x0.h> |
12 | 11 | ||
13 | #include "db8500-regs.h" | 12 | #include "db8500-regs.h" |
14 | #include "id.h" | 13 | #include "id.h" |
15 | 14 | ||
16 | static void __iomem *l2x0_base; | ||
17 | |||
18 | static int __init ux500_l2x0_unlock(void) | 15 | static int __init ux500_l2x0_unlock(void) |
19 | { | 16 | { |
20 | int i; | 17 | int i; |
18 | void __iomem *l2x0_base = __io_address(U8500_L2CC_BASE); | ||
21 | 19 | ||
22 | /* | 20 | /* |
23 | * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions | 21 | * Unlock Data and Instruction Lock if locked. Ux500 U-Boot versions |
@@ -45,23 +43,15 @@ static void ux500_l2c310_write_sec(unsigned long val, unsigned reg) | |||
45 | 43 | ||
46 | static int __init ux500_l2x0_init(void) | 44 | static int __init ux500_l2x0_init(void) |
47 | { | 45 | { |
48 | if (cpu_is_u8500_family() || cpu_is_ux540_family()) | 46 | /* Multiplatform guard */ |
49 | l2x0_base = __io_address(U8500_L2CC_BASE); | 47 | if (!((cpu_is_u8500_family() || cpu_is_ux540_family()))) |
50 | else | ||
51 | /* Non-Ux500 platform */ | ||
52 | return -ENODEV; | 48 | return -ENODEV; |
53 | 49 | ||
54 | /* Unlock before init */ | 50 | /* Unlock before init */ |
55 | ux500_l2x0_unlock(); | 51 | ux500_l2x0_unlock(); |
56 | |||
57 | outer_cache.write_sec = ux500_l2c310_write_sec; | 52 | outer_cache.write_sec = ux500_l2c310_write_sec; |
58 | 53 | l2x0_of_init(0, ~0); | |
59 | if (of_have_populated_dt()) | ||
60 | l2x0_of_init(0, ~0); | ||
61 | else | ||
62 | l2x0_init(l2x0_base, 0, ~0); | ||
63 | 54 | ||
64 | return 0; | 55 | return 0; |
65 | } | 56 | } |
66 | |||
67 | early_initcall(ux500_l2x0_init); | 57 | early_initcall(ux500_l2x0_init); |
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c index fa308f07fae5..6f63954c8bde 100644 --- a/arch/arm/mach-ux500/cpu-db8500.c +++ b/arch/arm/mach-ux500/cpu-db8500.c | |||
@@ -33,11 +33,11 @@ | |||
33 | #include "db8500-regs.h" | 33 | #include "db8500-regs.h" |
34 | #include "id.h" | 34 | #include "id.h" |
35 | 35 | ||
36 | struct ab8500_platform_data ab8500_platdata = { | 36 | static struct ab8500_platform_data ab8500_platdata = { |
37 | .regulator = &ab8500_regulator_plat_data, | 37 | .regulator = &ab8500_regulator_plat_data, |
38 | }; | 38 | }; |
39 | 39 | ||
40 | struct prcmu_pdata db8500_prcmu_pdata = { | 40 | static struct prcmu_pdata db8500_prcmu_pdata = { |
41 | .ab_platdata = &ab8500_platdata, | 41 | .ab_platdata = &ab8500_platdata, |
42 | .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, | 42 | .version_offset = DB8500_PRCMU_FW_VERSION_OFFSET, |
43 | .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, | 43 | .legacy_offset = DB8500_PRCMU_LEGACY_OFFSET, |
@@ -82,7 +82,7 @@ static struct map_desc u9540_io_desc[] __initdata = { | |||
82 | __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K), | 82 | __IO_DEV_DESC(U8500_PRCMU_TCDM_BASE, SZ_4K + SZ_8K), |
83 | }; | 83 | }; |
84 | 84 | ||
85 | void __init u8500_map_io(void) | 85 | static void __init u8500_map_io(void) |
86 | { | 86 | { |
87 | /* | 87 | /* |
88 | * Map the UARTs early so that the DEBUG_LL stuff continues to work. | 88 | * Map the UARTs early so that the DEBUG_LL stuff continues to work. |
@@ -119,7 +119,7 @@ static irqreturn_t db8500_pmu_handler(int irq, void *dev, irq_handler_t handler) | |||
119 | return ret; | 119 | return ret; |
120 | } | 120 | } |
121 | 121 | ||
122 | struct arm_pmu_platdata db8500_pmu_platdata = { | 122 | static struct arm_pmu_platdata db8500_pmu_platdata = { |
123 | .handle_irq = db8500_pmu_handler, | 123 | .handle_irq = db8500_pmu_handler, |
124 | }; | 124 | }; |
125 | 125 | ||
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c index db16b5a04ad5..dbb2970ee7da 100644 --- a/arch/arm/mach-ux500/cpu.c +++ b/arch/arm/mach-ux500/cpu.c | |||
@@ -125,7 +125,7 @@ static void __init soc_info_populate(struct soc_device_attribute *soc_dev_attr, | |||
125 | soc_dev_attr->revision = ux500_get_revision(); | 125 | soc_dev_attr->revision = ux500_get_revision(); |
126 | } | 126 | } |
127 | 127 | ||
128 | struct device_attribute ux500_soc_attr = | 128 | static const struct device_attribute ux500_soc_attr = |
129 | __ATTR(process, S_IRUGO, ux500_get_process, NULL); | 129 | __ATTR(process, S_IRUGO, ux500_get_process, NULL); |
130 | 130 | ||
131 | struct device * __init ux500_soc_device_init(const char *soc_id) | 131 | struct device * __init ux500_soc_device_init(const char *soc_id) |
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c index 87efda0aa348..ff28d8ad1ed7 100644 --- a/arch/arm/mach-ux500/timer.c +++ b/arch/arm/mach-ux500/timer.c | |||
@@ -16,7 +16,7 @@ | |||
16 | #include "db8500-regs.h" | 16 | #include "db8500-regs.h" |
17 | #include "id.h" | 17 | #include "id.h" |
18 | 18 | ||
19 | const static struct of_device_id prcmu_timer_of_match[] __initconst = { | 19 | static const struct of_device_id prcmu_timer_of_match[] __initconst = { |
20 | { .compatible = "stericsson,db8500-prcmu-timer-4", }, | 20 | { .compatible = "stericsson,db8500-prcmu-timer-4", }, |
21 | { }, | 21 | { }, |
22 | }; | 22 | }; |
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c index be83ba25f81b..08fb8c89f414 100644 --- a/arch/arm/mach-versatile/core.c +++ b/arch/arm/mach-versatile/core.c | |||
@@ -28,6 +28,7 @@ | |||
28 | #include <linux/of_platform.h> | 28 | #include <linux/of_platform.h> |
29 | #include <linux/amba/bus.h> | 29 | #include <linux/amba/bus.h> |
30 | #include <linux/amba/clcd.h> | 30 | #include <linux/amba/clcd.h> |
31 | #include <linux/platform_data/video-clcd-versatile.h> | ||
31 | #include <linux/amba/pl061.h> | 32 | #include <linux/amba/pl061.h> |
32 | #include <linux/amba/mmci.h> | 33 | #include <linux/amba/mmci.h> |
33 | #include <linux/amba/pl022.h> | 34 | #include <linux/amba/pl022.h> |
@@ -53,7 +54,6 @@ | |||
53 | #include <mach/platform.h> | 54 | #include <mach/platform.h> |
54 | #include <asm/hardware/timer-sp.h> | 55 | #include <asm/hardware/timer-sp.h> |
55 | 56 | ||
56 | #include <plat/clcd.h> | ||
57 | #include <plat/sched_clock.h> | 57 | #include <plat/sched_clock.h> |
58 | 58 | ||
59 | #include "core.h" | 59 | #include "core.h" |
diff --git a/arch/arm/mach-vexpress/Kconfig b/arch/arm/mach-vexpress/Kconfig index 1af70329b88d..b2cfba16c4e8 100644 --- a/arch/arm/mach-vexpress/Kconfig +++ b/arch/arm/mach-vexpress/Kconfig | |||
@@ -13,7 +13,6 @@ menuconfig ARCH_VEXPRESS | |||
13 | select ICST | 13 | select ICST |
14 | select NO_IOPORT_MAP | 14 | select NO_IOPORT_MAP |
15 | select PLAT_VERSATILE | 15 | select PLAT_VERSATILE |
16 | select PLAT_VERSATILE_CLCD | ||
17 | select POWER_RESET | 16 | select POWER_RESET |
18 | select POWER_RESET_VEXPRESS | 17 | select POWER_RESET_VEXPRESS |
19 | select POWER_SUPPLY | 18 | select POWER_SUPPLY |
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c index 86150d7a2e7d..27bea049380a 100644 --- a/arch/arm/mach-vexpress/ct-ca9x4.c +++ b/arch/arm/mach-vexpress/ct-ca9x4.c | |||
@@ -8,6 +8,7 @@ | |||
8 | #include <linux/platform_device.h> | 8 | #include <linux/platform_device.h> |
9 | #include <linux/amba/bus.h> | 9 | #include <linux/amba/bus.h> |
10 | #include <linux/amba/clcd.h> | 10 | #include <linux/amba/clcd.h> |
11 | #include <linux/platform_data/video-clcd-versatile.h> | ||
11 | #include <linux/clkdev.h> | 12 | #include <linux/clkdev.h> |
12 | #include <linux/vexpress.h> | 13 | #include <linux/vexpress.h> |
13 | #include <linux/irqchip/arm-gic.h> | 14 | #include <linux/irqchip/arm-gic.h> |
@@ -29,8 +30,6 @@ | |||
29 | #include <mach/motherboard.h> | 30 | #include <mach/motherboard.h> |
30 | #include <mach/irqs.h> | 31 | #include <mach/irqs.h> |
31 | 32 | ||
32 | #include <plat/clcd.h> | ||
33 | |||
34 | static struct map_desc ct_ca9x4_io_desc[] __initdata = { | 33 | static struct map_desc ct_ca9x4_io_desc[] __initdata = { |
35 | { | 34 | { |
36 | .virtual = V2T_PERIPH, | 35 | .virtual = V2T_PERIPH, |
diff --git a/arch/arm/mach-vt8500/vt8500.c b/arch/arm/mach-vt8500/vt8500.c index 4a73464cb11b..2da7be31e7e2 100644 --- a/arch/arm/mach-vt8500/vt8500.c +++ b/arch/arm/mach-vt8500/vt8500.c | |||
@@ -44,7 +44,7 @@ | |||
44 | 44 | ||
45 | static void __iomem *pmc_base; | 45 | static void __iomem *pmc_base; |
46 | 46 | ||
47 | void vt8500_restart(enum reboot_mode mode, const char *cmd) | 47 | static void vt8500_restart(enum reboot_mode mode, const char *cmd) |
48 | { | 48 | { |
49 | if (pmc_base) | 49 | if (pmc_base) |
50 | writel(1, pmc_base + VT8500_PMSR_REG); | 50 | writel(1, pmc_base + VT8500_PMSR_REG); |
@@ -60,7 +60,7 @@ static struct map_desc vt8500_io_desc[] __initdata = { | |||
60 | }, | 60 | }, |
61 | }; | 61 | }; |
62 | 62 | ||
63 | void __init vt8500_map_io(void) | 63 | static void __init vt8500_map_io(void) |
64 | { | 64 | { |
65 | iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc)); | 65 | iotable_init(vt8500_io_desc, ARRAY_SIZE(vt8500_io_desc)); |
66 | } | 66 | } |
@@ -72,7 +72,7 @@ static void vt8500_power_off(void) | |||
72 | asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); | 72 | asm("mcr%? p15, 0, %0, c7, c0, 4" : : "r" (0)); |
73 | } | 73 | } |
74 | 74 | ||
75 | void __init vt8500_init(void) | 75 | static void __init vt8500_init(void) |
76 | { | 76 | { |
77 | struct device_node *np; | 77 | struct device_node *np; |
78 | #if defined(CONFIG_FB_VT8500) || defined(CONFIG_FB_WM8505) | 78 | #if defined(CONFIG_FB_VT8500) || defined(CONFIG_FB_WM8505) |
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig index 301b892d97d9..6910c8669742 100644 --- a/arch/arm/plat-samsung/Kconfig +++ b/arch/arm/plat-samsung/Kconfig | |||
@@ -15,7 +15,7 @@ config PLAT_SAMSUNG | |||
15 | 15 | ||
16 | config PLAT_S5P | 16 | config PLAT_S5P |
17 | bool | 17 | bool |
18 | depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) | 18 | depends on ARCH_S5PV210 |
19 | default y | 19 | default y |
20 | select ARCH_REQUIRE_GPIOLIB | 20 | select ARCH_REQUIRE_GPIOLIB |
21 | select ARM_VIC | 21 | select ARM_VIC |
@@ -29,7 +29,7 @@ config PLAT_S5P | |||
29 | 29 | ||
30 | config SAMSUNG_PM | 30 | config SAMSUNG_PM |
31 | bool | 31 | bool |
32 | depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM) | 32 | depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM) |
33 | default y | 33 | default y |
34 | help | 34 | help |
35 | Base platform power management code for samsung code | 35 | Base platform power management code for samsung code |
@@ -78,14 +78,14 @@ config SAMSUNG_CLKSRC | |||
78 | used by newer systems such as the S3C64XX. | 78 | used by newer systems such as the S3C64XX. |
79 | 79 | ||
80 | config S5P_CLOCK | 80 | config S5P_CLOCK |
81 | def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) | 81 | def_bool ARCH_S5PV210 |
82 | help | 82 | help |
83 | Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs | 83 | Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs |
84 | 84 | ||
85 | # options for IRQ support | 85 | # options for IRQ support |
86 | 86 | ||
87 | config S5P_IRQ | 87 | config S5P_IRQ |
88 | def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) | 88 | def_bool ARCH_S5PV210 |
89 | help | 89 | help |
90 | Support common interrupt part for ARCH_S5P SoCs | 90 | Support common interrupt part for ARCH_S5P SoCs |
91 | 91 | ||
@@ -93,7 +93,6 @@ config S5P_EXT_INT | |||
93 | bool | 93 | bool |
94 | help | 94 | help |
95 | Use the external interrupts (other than GPIO interrupts.) | 95 | Use the external interrupts (other than GPIO interrupts.) |
96 | Note: Do not choose this for S5P6440 and S5P6450. | ||
97 | 96 | ||
98 | config S5P_GPIO_INT | 97 | config S5P_GPIO_INT |
99 | bool | 98 | bool |
@@ -108,22 +107,6 @@ config S5P_GPIO_DRVSTR | |||
108 | Internal configuration to get and set correct GPIO driver strength | 107 | Internal configuration to get and set correct GPIO driver strength |
109 | helper | 108 | helper |
110 | 109 | ||
111 | config SAMSUNG_GPIO_EXTRA | ||
112 | int "Number of additional GPIO pins" | ||
113 | default 128 if SAMSUNG_GPIO_EXTRA128 | ||
114 | default 64 if SAMSUNG_GPIO_EXTRA64 | ||
115 | default 0 | ||
116 | help | ||
117 | Use additional GPIO space in addition to the GPIO's the SOC | ||
118 | provides. This allows expanding the GPIO space for use with | ||
119 | GPIO expanders. | ||
120 | |||
121 | config SAMSUNG_GPIO_EXTRA64 | ||
122 | bool | ||
123 | |||
124 | config SAMSUNG_GPIO_EXTRA128 | ||
125 | bool | ||
126 | |||
127 | config S3C_GPIO_SPACE | 110 | config S3C_GPIO_SPACE |
128 | int "Space between gpio banks" | 111 | int "Space between gpio banks" |
129 | default 0 | 112 | default 0 |
@@ -143,7 +126,7 @@ config S3C_GPIO_TRACK | |||
143 | 126 | ||
144 | config S5P_DEV_UART | 127 | config S5P_DEV_UART |
145 | def_bool y | 128 | def_bool y |
146 | depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) | 129 | depends on ARCH_S5PV210 |
147 | 130 | ||
148 | # ADC driver | 131 | # ADC driver |
149 | 132 | ||
@@ -397,7 +380,7 @@ config SAMSUNG_PM_GPIO | |||
397 | 380 | ||
398 | config SAMSUNG_DMADEV | 381 | config SAMSUNG_DMADEV |
399 | bool "Use legacy Samsung DMA abstraction" | 382 | bool "Use legacy Samsung DMA abstraction" |
400 | depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S5P64X0 || ARCH_S3C64XX | 383 | depends on CPU_S5PV210 || ARCH_S3C64XX |
401 | select DMADEVICES | 384 | select DMADEVICES |
402 | default y | 385 | default y |
403 | help | 386 | help |
@@ -474,7 +457,6 @@ config S5P_PM | |||
474 | bool | 457 | bool |
475 | help | 458 | help |
476 | Common code for power management support on S5P and newer SoCs | 459 | Common code for power management support on S5P and newer SoCs |
477 | Note: Do not select this for S5P6440 and S5P6450. | ||
478 | 460 | ||
479 | config S5P_SLEEP | 461 | config S5P_SLEEP |
480 | bool | 462 | bool |
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c index 79690f2f6d3f..468352633101 100644 --- a/arch/arm/plat-samsung/adc.c +++ b/arch/arm/plat-samsung/adc.c | |||
@@ -43,7 +43,7 @@ enum s3c_cpu_type { | |||
43 | TYPE_ADCV1, /* S3C24XX */ | 43 | TYPE_ADCV1, /* S3C24XX */ |
44 | TYPE_ADCV11, /* S3C2443 */ | 44 | TYPE_ADCV11, /* S3C2443 */ |
45 | TYPE_ADCV12, /* S3C2416, S3C2450 */ | 45 | TYPE_ADCV12, /* S3C2416, S3C2450 */ |
46 | TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */ | 46 | TYPE_ADCV2, /* S3C64XX */ |
47 | TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ | 47 | TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ |
48 | }; | 48 | }; |
49 | 49 | ||
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h index 5a237db9f9eb..d1d4659025bb 100644 --- a/arch/arm/plat-samsung/include/plat/cpu.h +++ b/arch/arm/plat-samsung/include/plat/cpu.h | |||
@@ -33,13 +33,6 @@ extern unsigned long samsung_cpu_id; | |||
33 | #define S3C6410_CPU_ID 0x36410000 | 33 | #define S3C6410_CPU_ID 0x36410000 |
34 | #define S3C64XX_CPU_MASK 0xFFFFF000 | 34 | #define S3C64XX_CPU_MASK 0xFFFFF000 |
35 | 35 | ||
36 | #define S5P6440_CPU_ID 0x56440000 | ||
37 | #define S5P6450_CPU_ID 0x36450000 | ||
38 | #define S5P64XX_CPU_MASK 0xFFFFF000 | ||
39 | |||
40 | #define S5PC100_CPU_ID 0x43100000 | ||
41 | #define S5PC100_CPU_MASK 0xFFFFF000 | ||
42 | |||
43 | #define S5PV210_CPU_ID 0x43110000 | 36 | #define S5PV210_CPU_ID 0x43110000 |
44 | #define S5PV210_CPU_MASK 0xFFFFF000 | 37 | #define S5PV210_CPU_MASK 0xFFFFF000 |
45 | 38 | ||
@@ -54,9 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK) | |||
54 | IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) | 47 | IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) |
55 | IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) | 48 | IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) |
56 | IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) | 49 | IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) |
57 | IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK) | ||
58 | IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK) | ||
59 | IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK) | ||
60 | IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) | 50 | IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) |
61 | 51 | ||
62 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ | 52 | #if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ |
@@ -86,24 +76,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) | |||
86 | # define soc_is_s3c64xx() 0 | 76 | # define soc_is_s3c64xx() 0 |
87 | #endif | 77 | #endif |
88 | 78 | ||
89 | #if defined(CONFIG_CPU_S5P6440) | ||
90 | # define soc_is_s5p6440() is_samsung_s5p6440() | ||
91 | #else | ||
92 | # define soc_is_s5p6440() 0 | ||
93 | #endif | ||
94 | |||
95 | #if defined(CONFIG_CPU_S5P6450) | ||
96 | # define soc_is_s5p6450() is_samsung_s5p6450() | ||
97 | #else | ||
98 | # define soc_is_s5p6450() 0 | ||
99 | #endif | ||
100 | |||
101 | #if defined(CONFIG_CPU_S5PC100) | ||
102 | # define soc_is_s5pc100() is_samsung_s5pc100() | ||
103 | #else | ||
104 | # define soc_is_s5pc100() 0 | ||
105 | #endif | ||
106 | |||
107 | #if defined(CONFIG_CPU_S5PV210) | 79 | #if defined(CONFIG_CPU_S5PV210) |
108 | # define soc_is_s5pv210() is_samsung_s5pv210() | 80 | # define soc_is_s5pv210() is_samsung_s5pv210() |
109 | #else | 81 | #else |
@@ -177,7 +149,6 @@ extern struct bus_type s3c2440_subsys; | |||
177 | extern struct bus_type s3c2442_subsys; | 149 | extern struct bus_type s3c2442_subsys; |
178 | extern struct bus_type s3c2443_subsys; | 150 | extern struct bus_type s3c2443_subsys; |
179 | extern struct bus_type s3c6410_subsys; | 151 | extern struct bus_type s3c6410_subsys; |
180 | extern struct bus_type s5p64x0_subsys; | ||
181 | extern struct bus_type s5pv210_subsys; | 152 | extern struct bus_type s5pv210_subsys; |
182 | 153 | ||
183 | extern void (*s5pc1xx_idle)(void); | 154 | extern void (*s5pc1xx_idle)(void); |
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h index eece188ed188..5f5a28d08c2e 100644 --- a/arch/arm/plat-samsung/include/plat/devs.h +++ b/arch/arm/plat-samsung/include/plat/devs.h | |||
@@ -94,23 +94,6 @@ extern struct platform_device s5p_device_mixer; | |||
94 | extern struct platform_device s5p_device_onenand; | 94 | extern struct platform_device s5p_device_onenand; |
95 | extern struct platform_device s5p_device_sdo; | 95 | extern struct platform_device s5p_device_sdo; |
96 | 96 | ||
97 | extern struct platform_device s5p6440_device_iis; | ||
98 | extern struct platform_device s5p6440_device_pcm; | ||
99 | |||
100 | extern struct platform_device s5p6450_device_iis0; | ||
101 | extern struct platform_device s5p6450_device_iis1; | ||
102 | extern struct platform_device s5p6450_device_iis2; | ||
103 | extern struct platform_device s5p6450_device_pcm0; | ||
104 | |||
105 | |||
106 | extern struct platform_device s5pc100_device_ac97; | ||
107 | extern struct platform_device s5pc100_device_iis0; | ||
108 | extern struct platform_device s5pc100_device_iis1; | ||
109 | extern struct platform_device s5pc100_device_iis2; | ||
110 | extern struct platform_device s5pc100_device_pcm0; | ||
111 | extern struct platform_device s5pc100_device_pcm1; | ||
112 | extern struct platform_device s5pc100_device_spdif; | ||
113 | |||
114 | extern struct platform_device s5pv210_device_ac97; | 97 | extern struct platform_device s5pv210_device_ac97; |
115 | extern struct platform_device s5pv210_device_iis0; | 98 | extern struct platform_device s5pv210_device_iis0; |
116 | extern struct platform_device s5pv210_device_iis1; | 99 | extern struct platform_device s5pv210_device_iis1; |
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h index 9ae507270785..5a0e26afb961 100644 --- a/arch/arm/plat-samsung/include/plat/fb.h +++ b/arch/arm/plat-samsung/include/plat/fb.h | |||
@@ -41,13 +41,6 @@ extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd); | |||
41 | extern void s3c64xx_fb_gpio_setup_24bpp(void); | 41 | extern void s3c64xx_fb_gpio_setup_24bpp(void); |
42 | 42 | ||
43 | /** | 43 | /** |
44 | * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD | ||
45 | * | ||
46 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. | ||
47 | */ | ||
48 | extern void s5pc100_fb_gpio_setup_24bpp(void); | ||
49 | |||
50 | /** | ||
51 | * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD | 44 | * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD |
52 | * | 45 | * |
53 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. | 46 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. |
@@ -61,11 +54,4 @@ extern void s5pv210_fb_gpio_setup_24bpp(void); | |||
61 | */ | 54 | */ |
62 | extern void exynos4_fimd0_gpio_setup_24bpp(void); | 55 | extern void exynos4_fimd0_gpio_setup_24bpp(void); |
63 | 56 | ||
64 | /** | ||
65 | * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD | ||
66 | * | ||
67 | * Initialise the GPIO for an 24bpp LCD display on the RGB interface. | ||
68 | */ | ||
69 | extern void s5p64x0_fb_gpio_setup_24bpp(void); | ||
70 | |||
71 | #endif /* __PLAT_S3C_FB_H */ | 57 | #endif /* __PLAT_S3C_FB_H */ |
diff --git a/arch/arm/plat-samsung/include/plat/gpio-core.h b/arch/arm/plat-samsung/include/plat/gpio-core.h index cf5aae5b0975..6ce11bfdc37e 100644 --- a/arch/arm/plat-samsung/include/plat/gpio-core.h +++ b/arch/arm/plat-samsung/include/plat/gpio-core.h | |||
@@ -14,6 +14,9 @@ | |||
14 | #ifndef __PLAT_SAMSUNG_GPIO_CORE_H | 14 | #ifndef __PLAT_SAMSUNG_GPIO_CORE_H |
15 | #define __PLAT_SAMSUNG_GPIO_CORE_H | 15 | #define __PLAT_SAMSUNG_GPIO_CORE_H |
16 | 16 | ||
17 | /* Bring in machine-local definitions, especially S3C_GPIO_END */ | ||
18 | #include <mach/gpio-samsung.h> | ||
19 | |||
17 | #define GPIOCON_OFF (0x00) | 20 | #define GPIOCON_OFF (0x00) |
18 | #define GPIODAT_OFF (0x04) | 21 | #define GPIODAT_OFF (0x04) |
19 | 22 | ||
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h index 8364b4bea8b8..acacc4b88a39 100644 --- a/arch/arm/plat-samsung/include/plat/s5p-clock.h +++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h | |||
@@ -57,7 +57,7 @@ extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable); | |||
57 | extern int s5p_epll_enable(struct clk *clk, int enable); | 57 | extern int s5p_epll_enable(struct clk *clk, int enable); |
58 | extern unsigned long s5p_epll_get_rate(struct clk *clk); | 58 | extern unsigned long s5p_epll_get_rate(struct clk *clk); |
59 | 59 | ||
60 | /* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */ | 60 | /* SPDIF clk operations common for S5PV210/C110 and Exynos4 */ |
61 | extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate); | 61 | extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate); |
62 | extern unsigned long s5p_spdif_get_rate(struct clk *clk); | 62 | extern unsigned long s5p_spdif_get_rate(struct clk *clk); |
63 | 63 | ||
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h index bf650218b40e..f84b6cbc8745 100644 --- a/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/arch/arm/plat-samsung/include/plat/sdhci.h | |||
@@ -56,9 +56,6 @@ extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | |||
56 | extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | 56 | extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); |
57 | extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | 57 | extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
58 | extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | 58 | extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); |
59 | extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | ||
60 | extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | ||
61 | extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | ||
62 | extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | 59 | extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); |
63 | extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | 60 | extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); |
64 | extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | 61 | extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); |
@@ -68,10 +65,6 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | |||
68 | extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | 65 | extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); |
69 | extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | 66 | extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); |
70 | extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); | 67 | extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); |
71 | extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w); | ||
72 | extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w); | ||
73 | extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | ||
74 | extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w); | ||
75 | 68 | ||
76 | /* S3C2416 SDHCI setup */ | 69 | /* S3C2416 SDHCI setup */ |
77 | 70 | ||
@@ -151,76 +144,6 @@ static inline void s3c6400_default_sdhci2(void) { } | |||
151 | 144 | ||
152 | #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ | 145 | #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ |
153 | 146 | ||
154 | /* S5P64X0 SDHCI setup */ | ||
155 | |||
156 | #ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO | ||
157 | static inline void s5p64x0_default_sdhci0(void) | ||
158 | { | ||
159 | #ifdef CONFIG_S3C_DEV_HSMMC | ||
160 | s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio; | ||
161 | #endif | ||
162 | } | ||
163 | |||
164 | static inline void s5p64x0_default_sdhci1(void) | ||
165 | { | ||
166 | #ifdef CONFIG_S3C_DEV_HSMMC1 | ||
167 | s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio; | ||
168 | #endif | ||
169 | } | ||
170 | |||
171 | static inline void s5p6440_default_sdhci2(void) | ||
172 | { | ||
173 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
174 | s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio; | ||
175 | #endif | ||
176 | } | ||
177 | |||
178 | static inline void s5p6450_default_sdhci2(void) | ||
179 | { | ||
180 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
181 | s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio; | ||
182 | #endif | ||
183 | } | ||
184 | |||
185 | #else | ||
186 | static inline void s5p64x0_default_sdhci0(void) { } | ||
187 | static inline void s5p64x0_default_sdhci1(void) { } | ||
188 | static inline void s5p6440_default_sdhci2(void) { } | ||
189 | static inline void s5p6450_default_sdhci2(void) { } | ||
190 | |||
191 | #endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */ | ||
192 | |||
193 | /* S5PC100 SDHCI setup */ | ||
194 | |||
195 | #ifdef CONFIG_S5PC100_SETUP_SDHCI | ||
196 | static inline void s5pc100_default_sdhci0(void) | ||
197 | { | ||
198 | #ifdef CONFIG_S3C_DEV_HSMMC | ||
199 | s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio; | ||
200 | #endif | ||
201 | } | ||
202 | |||
203 | static inline void s5pc100_default_sdhci1(void) | ||
204 | { | ||
205 | #ifdef CONFIG_S3C_DEV_HSMMC1 | ||
206 | s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio; | ||
207 | #endif | ||
208 | } | ||
209 | |||
210 | static inline void s5pc100_default_sdhci2(void) | ||
211 | { | ||
212 | #ifdef CONFIG_S3C_DEV_HSMMC2 | ||
213 | s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio; | ||
214 | #endif | ||
215 | } | ||
216 | |||
217 | #else | ||
218 | static inline void s5pc100_default_sdhci0(void) { } | ||
219 | static inline void s5pc100_default_sdhci1(void) { } | ||
220 | static inline void s5pc100_default_sdhci2(void) { } | ||
221 | |||
222 | #endif /* CONFIG_S5PC100_SETUP_SDHCI */ | ||
223 | |||
224 | /* S5PV210 SDHCI setup */ | 147 | /* S5PV210 SDHCI setup */ |
225 | 148 | ||
226 | #ifdef CONFIG_S5PV210_SETUP_SDHCI | 149 | #ifdef CONFIG_S5PV210_SETUP_SDHCI |
diff --git a/arch/arm/plat-samsung/pm-gpio.c b/arch/arm/plat-samsung/pm-gpio.c index da268813901b..adc91662f72b 100644 --- a/arch/arm/plat-samsung/pm-gpio.c +++ b/arch/arm/plat-samsung/pm-gpio.c | |||
@@ -19,9 +19,7 @@ | |||
19 | #include <linux/io.h> | 19 | #include <linux/io.h> |
20 | #include <linux/gpio.h> | 20 | #include <linux/gpio.h> |
21 | 21 | ||
22 | #if defined(CONFIG_ARCH_S3C24XX) || defined(CONFIG_ARCH_S3C64XX) | ||
23 | #include <mach/gpio-samsung.h> | 22 | #include <mach/gpio-samsung.h> |
24 | #endif | ||
25 | 23 | ||
26 | #include <plat/gpio-core.h> | 24 | #include <plat/gpio-core.h> |
27 | #include <plat/pm.h> | 25 | #include <plat/pm.h> |
diff --git a/arch/arm/plat-samsung/s5p-irq-eint.c b/arch/arm/plat-samsung/s5p-irq-eint.c index ebee4dc11a94..dcd8c2cbf5bb 100644 --- a/arch/arm/plat-samsung/s5p-irq-eint.c +++ b/arch/arm/plat-samsung/s5p-irq-eint.c | |||
@@ -14,7 +14,6 @@ | |||
14 | #include <linux/irq.h> | 14 | #include <linux/irq.h> |
15 | #include <linux/io.h> | 15 | #include <linux/io.h> |
16 | #include <linux/device.h> | 16 | #include <linux/device.h> |
17 | #include <linux/gpio.h> | ||
18 | #include <linux/irqchip/arm-vic.h> | 17 | #include <linux/irqchip/arm-vic.h> |
19 | #include <linux/of.h> | 18 | #include <linux/of.h> |
20 | 19 | ||
@@ -26,6 +25,7 @@ | |||
26 | 25 | ||
27 | #include <plat/gpio-cfg.h> | 26 | #include <plat/gpio-cfg.h> |
28 | #include <mach/regs-gpio.h> | 27 | #include <mach/regs-gpio.h> |
28 | #include <mach/gpio-samsung.h> | ||
29 | 29 | ||
30 | static inline void s5p_irq_eint_mask(struct irq_data *data) | 30 | static inline void s5p_irq_eint_mask(struct irq_data *data) |
31 | { | 31 | { |
diff --git a/arch/arm/plat-versatile/Kconfig b/arch/arm/plat-versatile/Kconfig index fce41e93b6a4..a301ca2c7d00 100644 --- a/arch/arm/plat-versatile/Kconfig +++ b/arch/arm/plat-versatile/Kconfig | |||
@@ -3,9 +3,6 @@ if PLAT_VERSATILE | |||
3 | config PLAT_VERSATILE_CLOCK | 3 | config PLAT_VERSATILE_CLOCK |
4 | bool | 4 | bool |
5 | 5 | ||
6 | config PLAT_VERSATILE_CLCD | ||
7 | bool | ||
8 | |||
9 | config PLAT_VERSATILE_SCHED_CLOCK | 6 | config PLAT_VERSATILE_SCHED_CLOCK |
10 | def_bool y | 7 | def_bool y |
11 | 8 | ||
diff --git a/arch/arm/plat-versatile/Makefile b/arch/arm/plat-versatile/Makefile index 2e0c472958ae..03c4900ac3f4 100644 --- a/arch/arm/plat-versatile/Makefile +++ b/arch/arm/plat-versatile/Makefile | |||
@@ -1,6 +1,5 @@ | |||
1 | ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include | 1 | ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include |
2 | 2 | ||
3 | obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o | 3 | obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o |
4 | obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o | ||
5 | obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o | 4 | obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o |
6 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o | 5 | obj-$(CONFIG_SMP) += headsmp.o platsmp.o |
diff --git a/arch/arm/plat-versatile/clcd.c b/arch/arm/plat-versatile/clcd.c deleted file mode 100644 index 6628cc27efc5..000000000000 --- a/arch/arm/plat-versatile/clcd.c +++ /dev/null | |||
@@ -1,182 +0,0 @@ | |||
1 | #include <linux/device.h> | ||
2 | #include <linux/dma-mapping.h> | ||
3 | #include <linux/amba/bus.h> | ||
4 | #include <linux/amba/clcd.h> | ||
5 | #include <plat/clcd.h> | ||
6 | |||
7 | static struct clcd_panel vga = { | ||
8 | .mode = { | ||
9 | .name = "VGA", | ||
10 | .refresh = 60, | ||
11 | .xres = 640, | ||
12 | .yres = 480, | ||
13 | .pixclock = 39721, | ||
14 | .left_margin = 40, | ||
15 | .right_margin = 24, | ||
16 | .upper_margin = 32, | ||
17 | .lower_margin = 11, | ||
18 | .hsync_len = 96, | ||
19 | .vsync_len = 2, | ||
20 | .sync = 0, | ||
21 | .vmode = FB_VMODE_NONINTERLACED, | ||
22 | }, | ||
23 | .width = -1, | ||
24 | .height = -1, | ||
25 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
26 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
27 | .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, | ||
28 | .bpp = 16, | ||
29 | }; | ||
30 | |||
31 | static struct clcd_panel xvga = { | ||
32 | .mode = { | ||
33 | .name = "XVGA", | ||
34 | .refresh = 60, | ||
35 | .xres = 1024, | ||
36 | .yres = 768, | ||
37 | .pixclock = 15748, | ||
38 | .left_margin = 152, | ||
39 | .right_margin = 48, | ||
40 | .upper_margin = 23, | ||
41 | .lower_margin = 3, | ||
42 | .hsync_len = 104, | ||
43 | .vsync_len = 4, | ||
44 | .sync = 0, | ||
45 | .vmode = FB_VMODE_NONINTERLACED, | ||
46 | }, | ||
47 | .width = -1, | ||
48 | .height = -1, | ||
49 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
50 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
51 | .caps = CLCD_CAP_5551 | CLCD_CAP_565 | CLCD_CAP_888, | ||
52 | .bpp = 16, | ||
53 | }; | ||
54 | |||
55 | /* Sanyo TM38QV67A02A - 3.8 inch QVGA (320x240) Color TFT */ | ||
56 | static struct clcd_panel sanyo_tm38qv67a02a = { | ||
57 | .mode = { | ||
58 | .name = "Sanyo TM38QV67A02A", | ||
59 | .refresh = 116, | ||
60 | .xres = 320, | ||
61 | .yres = 240, | ||
62 | .pixclock = 100000, | ||
63 | .left_margin = 6, | ||
64 | .right_margin = 6, | ||
65 | .upper_margin = 5, | ||
66 | .lower_margin = 5, | ||
67 | .hsync_len = 6, | ||
68 | .vsync_len = 6, | ||
69 | .sync = 0, | ||
70 | .vmode = FB_VMODE_NONINTERLACED, | ||
71 | }, | ||
72 | .width = -1, | ||
73 | .height = -1, | ||
74 | .tim2 = TIM2_BCD, | ||
75 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
76 | .caps = CLCD_CAP_5551, | ||
77 | .bpp = 16, | ||
78 | }; | ||
79 | |||
80 | static struct clcd_panel sanyo_2_5_in = { | ||
81 | .mode = { | ||
82 | .name = "Sanyo QVGA Portrait", | ||
83 | .refresh = 116, | ||
84 | .xres = 240, | ||
85 | .yres = 320, | ||
86 | .pixclock = 100000, | ||
87 | .left_margin = 20, | ||
88 | .right_margin = 10, | ||
89 | .upper_margin = 2, | ||
90 | .lower_margin = 2, | ||
91 | .hsync_len = 10, | ||
92 | .vsync_len = 2, | ||
93 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
94 | .vmode = FB_VMODE_NONINTERLACED, | ||
95 | }, | ||
96 | .width = -1, | ||
97 | .height = -1, | ||
98 | .tim2 = TIM2_IVS | TIM2_IHS | TIM2_IPC, | ||
99 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
100 | .caps = CLCD_CAP_5551, | ||
101 | .bpp = 16, | ||
102 | }; | ||
103 | |||
104 | /* Epson L2F50113T00 - 2.2 inch 176x220 Color TFT */ | ||
105 | static struct clcd_panel epson_l2f50113t00 = { | ||
106 | .mode = { | ||
107 | .name = "Epson L2F50113T00", | ||
108 | .refresh = 390, | ||
109 | .xres = 176, | ||
110 | .yres = 220, | ||
111 | .pixclock = 62500, | ||
112 | .left_margin = 3, | ||
113 | .right_margin = 2, | ||
114 | .upper_margin = 1, | ||
115 | .lower_margin = 0, | ||
116 | .hsync_len = 3, | ||
117 | .vsync_len = 2, | ||
118 | .sync = 0, | ||
119 | .vmode = FB_VMODE_NONINTERLACED, | ||
120 | }, | ||
121 | .width = -1, | ||
122 | .height = -1, | ||
123 | .tim2 = TIM2_BCD | TIM2_IPC, | ||
124 | .cntl = CNTL_LCDTFT | CNTL_BGR | CNTL_LCDVCOMP(1), | ||
125 | .caps = CLCD_CAP_5551, | ||
126 | .bpp = 16, | ||
127 | }; | ||
128 | |||
129 | static struct clcd_panel *panels[] = { | ||
130 | &vga, | ||
131 | &xvga, | ||
132 | &sanyo_tm38qv67a02a, | ||
133 | &sanyo_2_5_in, | ||
134 | &epson_l2f50113t00, | ||
135 | }; | ||
136 | |||
137 | struct clcd_panel *versatile_clcd_get_panel(const char *name) | ||
138 | { | ||
139 | int i; | ||
140 | |||
141 | for (i = 0; i < ARRAY_SIZE(panels); i++) | ||
142 | if (strcmp(panels[i]->mode.name, name) == 0) | ||
143 | break; | ||
144 | |||
145 | if (i < ARRAY_SIZE(panels)) | ||
146 | return panels[i]; | ||
147 | |||
148 | pr_err("CLCD: couldn't get parameters for panel %s\n", name); | ||
149 | |||
150 | return NULL; | ||
151 | } | ||
152 | |||
153 | int versatile_clcd_setup_dma(struct clcd_fb *fb, unsigned long framesize) | ||
154 | { | ||
155 | dma_addr_t dma; | ||
156 | |||
157 | fb->fb.screen_base = dma_alloc_writecombine(&fb->dev->dev, framesize, | ||
158 | &dma, GFP_KERNEL); | ||
159 | if (!fb->fb.screen_base) { | ||
160 | pr_err("CLCD: unable to map framebuffer\n"); | ||
161 | return -ENOMEM; | ||
162 | } | ||
163 | |||
164 | fb->fb.fix.smem_start = dma; | ||
165 | fb->fb.fix.smem_len = framesize; | ||
166 | |||
167 | return 0; | ||
168 | } | ||
169 | |||
170 | int versatile_clcd_mmap_dma(struct clcd_fb *fb, struct vm_area_struct *vma) | ||
171 | { | ||
172 | return dma_mmap_writecombine(&fb->dev->dev, vma, | ||
173 | fb->fb.screen_base, | ||
174 | fb->fb.fix.smem_start, | ||
175 | fb->fb.fix.smem_len); | ||
176 | } | ||
177 | |||
178 | void versatile_clcd_remove_dma(struct clcd_fb *fb) | ||
179 | { | ||
180 | dma_free_writecombine(&fb->dev->dev, fb->fb.fix.smem_len, | ||
181 | fb->fb.screen_base, fb->fb.fix.smem_start); | ||
182 | } | ||
diff --git a/arch/arm/plat-versatile/include/plat/clcd.h b/arch/arm/plat-versatile/include/plat/clcd.h deleted file mode 100644 index 6bb6a1d2019b..000000000000 --- a/arch/arm/plat-versatile/include/plat/clcd.h +++ /dev/null | |||
@@ -1,9 +0,0 @@ | |||
1 | #ifndef PLAT_CLCD_H | ||
2 | #define PLAT_CLCD_H | ||
3 | |||
4 | struct clcd_panel *versatile_clcd_get_panel(const char *); | ||
5 | int versatile_clcd_setup_dma(struct clcd_fb *, unsigned long); | ||
6 | int versatile_clcd_mmap_dma(struct clcd_fb *, struct vm_area_struct *); | ||
7 | void versatile_clcd_remove_dma(struct clcd_fb *); | ||
8 | |||
9 | #endif | ||