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Diffstat (limited to 'arch/x86/mm/tlb.c')
-rw-r--r--arch/x86/mm/tlb.c13
1 files changed, 6 insertions, 7 deletions
diff --git a/arch/x86/mm/tlb.c b/arch/x86/mm/tlb.c
index 1ab3821f9e26..49d9778376d7 100644
--- a/arch/x86/mm/tlb.c
+++ b/arch/x86/mm/tlb.c
@@ -126,8 +126,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
126 * isn't free. 126 * isn't free.
127 */ 127 */
128#ifdef CONFIG_DEBUG_VM 128#ifdef CONFIG_DEBUG_VM
129 if (WARN_ON_ONCE(__read_cr3() != 129 if (WARN_ON_ONCE(__read_cr3() != build_cr3(real_prev, prev_asid))) {
130 (__sme_pa(real_prev->pgd) | prev_asid))) {
131 /* 130 /*
132 * If we were to BUG here, we'd be very likely to kill 131 * If we were to BUG here, we'd be very likely to kill
133 * the system so hard that we don't see the call trace. 132 * the system so hard that we don't see the call trace.
@@ -172,7 +171,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
172 */ 171 */
173 this_cpu_write(cpu_tlbstate.ctxs[prev_asid].tlb_gen, 172 this_cpu_write(cpu_tlbstate.ctxs[prev_asid].tlb_gen,
174 next_tlb_gen); 173 next_tlb_gen);
175 write_cr3(__sme_pa(next->pgd) | prev_asid); 174 write_cr3(build_cr3(next, prev_asid));
176 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 175 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH,
177 TLB_FLUSH_ALL); 176 TLB_FLUSH_ALL);
178 } 177 }
@@ -192,7 +191,7 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
192 * mapped in the new pgd, we'll double-fault. Forcibly 191 * mapped in the new pgd, we'll double-fault. Forcibly
193 * map it. 192 * map it.
194 */ 193 */
195 unsigned int index = pgd_index(current_stack_pointer()); 194 unsigned int index = pgd_index(current_stack_pointer);
196 pgd_t *pgd = next->pgd + index; 195 pgd_t *pgd = next->pgd + index;
197 196
198 if (unlikely(pgd_none(*pgd))) 197 if (unlikely(pgd_none(*pgd)))
@@ -216,12 +215,12 @@ void switch_mm_irqs_off(struct mm_struct *prev, struct mm_struct *next,
216 if (need_flush) { 215 if (need_flush) {
217 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id); 216 this_cpu_write(cpu_tlbstate.ctxs[new_asid].ctx_id, next->context.ctx_id);
218 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen); 217 this_cpu_write(cpu_tlbstate.ctxs[new_asid].tlb_gen, next_tlb_gen);
219 write_cr3(__sme_pa(next->pgd) | new_asid); 218 write_cr3(build_cr3(next, new_asid));
220 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 219 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH,
221 TLB_FLUSH_ALL); 220 TLB_FLUSH_ALL);
222 } else { 221 } else {
223 /* The new ASID is already up to date. */ 222 /* The new ASID is already up to date. */
224 write_cr3(__sme_pa(next->pgd) | new_asid | CR3_NOFLUSH); 223 write_cr3(build_cr3_noflush(next, new_asid));
225 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0); 224 trace_tlb_flush(TLB_FLUSH_ON_TASK_SWITCH, 0);
226 } 225 }
227 226
@@ -265,7 +264,7 @@ void initialize_tlbstate_and_flush(void)
265 !(cr4_read_shadow() & X86_CR4_PCIDE)); 264 !(cr4_read_shadow() & X86_CR4_PCIDE));
266 265
267 /* Force ASID 0 and force a TLB flush. */ 266 /* Force ASID 0 and force a TLB flush. */
268 write_cr3(cr3 & ~CR3_PCID_MASK); 267 write_cr3(build_cr3(mm, 0));
269 268
270 /* Reinitialize tlbstate. */ 269 /* Reinitialize tlbstate. */
271 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0); 270 this_cpu_write(cpu_tlbstate.loaded_mm_asid, 0);