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-rw-r--r--arch/x86/mm/init.c13
1 files changed, 11 insertions, 2 deletions
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 649da47d3827..553c094b9cd7 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -173,11 +173,11 @@ static void __init probe_page_size_mask(void)
173 173
174 /* Enable PSE if available */ 174 /* Enable PSE if available */
175 if (cpu_has_pse) 175 if (cpu_has_pse)
176 set_in_cr4(X86_CR4_PSE); 176 cr4_set_bits_and_update_boot(X86_CR4_PSE);
177 177
178 /* Enable PGE if available */ 178 /* Enable PGE if available */
179 if (cpu_has_pge) { 179 if (cpu_has_pge) {
180 set_in_cr4(X86_CR4_PGE); 180 cr4_set_bits_and_update_boot(X86_CR4_PGE);
181 __supported_pte_mask |= _PAGE_GLOBAL; 181 __supported_pte_mask |= _PAGE_GLOBAL;
182 } 182 }
183} 183}
@@ -713,6 +713,15 @@ void __init zone_sizes_init(void)
713 free_area_init_nodes(max_zone_pfns); 713 free_area_init_nodes(max_zone_pfns);
714} 714}
715 715
716DEFINE_PER_CPU_SHARED_ALIGNED(struct tlb_state, cpu_tlbstate) = {
717#ifdef CONFIG_SMP
718 .active_mm = &init_mm,
719 .state = 0,
720#endif
721 .cr4 = ~0UL, /* fail hard if we screw up cr4 shadow initialization */
722};
723EXPORT_SYMBOL_GPL(cpu_tlbstate);
724
716void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache) 725void update_cache_mode_entry(unsigned entry, enum page_cache_mode cache)
717{ 726{
718 /* entry 0 MUST be WB (hardwired to speed up translations) */ 727 /* entry 0 MUST be WB (hardwired to speed up translations) */