1 files changed, 19 insertions, 19 deletions

diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index ff4554198981..2efbfb712fb7 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -538,45 +538,45 @@ int mwait_usable(const struct cpuinfo_x86 *c)
         return (edx & MWAIT_EDX_C1);
 }
 
-bool c1e_detected;
-EXPORT_SYMBOL(c1e_detected);
+bool amd_e400_c1e_detected;
+EXPORT_SYMBOL(amd_e400_c1e_detected);
 
-static cpumask_var_t c1e_mask;
+static cpumask_var_t amd_e400_c1e_mask;
 
-void c1e_remove_cpu(int cpu)
+void amd_e400_remove_cpu(int cpu)
 {
-        if (c1e_mask != NULL)
-                cpumask_clear_cpu(cpu, c1e_mask);
+        if (amd_e400_c1e_mask != NULL)
+                cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
 }
 
 /*
- * C1E aware idle routine. We check for C1E active in the interrupt
+ * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
  * pending message MSR. If we detect C1E, then we handle it the same
  * way as C3 power states (local apic timer and TSC stop)
  */
-static void c1e_idle(void)
+static void amd_e400_idle(void)
 {
         if (need_resched())
                 return;
 
-        if (!c1e_detected) {
+        if (!amd_e400_c1e_detected) {
                 u32 lo, hi;
 
                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 
                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
-                        c1e_detected = true;
+                        amd_e400_c1e_detected = true;
                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
                                 mark_tsc_unstable("TSC halt in AMD C1E");
                         printk(KERN_INFO "System has AMD C1E enabled\n");
                 }
         }
 
-        if (c1e_detected) {
+        if (amd_e400_c1e_detected) {
                 int cpu = smp_processor_id();
 
-                if (!cpumask_test_cpu(cpu, c1e_mask)) {
-                        cpumask_set_cpu(cpu, c1e_mask);
+                if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
+                        cpumask_set_cpu(cpu, amd_e400_c1e_mask);
                         /*
                          * Force broadcast so ACPI can not interfere.
                          */
@@ -619,17 +619,17 @@ void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
                 pm_idle = mwait_idle;
         } else if (cpu_has_amd_erratum(amd_erratum_400)) {
                 /* E400: APIC timer interrupt does not wake up CPU from C1e */
-                printk(KERN_INFO "using C1E aware idle routine\n");
-                pm_idle = c1e_idle;
+                printk(KERN_INFO "using AMD E400 aware idle routine\n");
+                pm_idle = amd_e400_idle;
         } else
                 pm_idle = default_idle;
 }
 
-void __init init_c1e_mask(void)
+void __init init_amd_e400_c1e_mask(void)
 {
-        /* If we're using c1e_idle, we need to allocate c1e_mask. */
-        if (pm_idle == c1e_idle)
-                zalloc_cpumask_var(&c1e_mask, GFP_KERNEL);
+        /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
+        if (pm_idle == amd_e400_idle)
+                zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
 }
 
 static int __init idle_setup(char *str)