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-rw-r--r--arch/x86/kernel/cpu/intel.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index b720dacac051..b1af22073e28 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -187,21 +187,6 @@ static void early_init_intel(struct cpuinfo_x86 *c)
187 if (c->x86 == 6 && c->x86_model < 15) 187 if (c->x86 == 6 && c->x86_model < 15)
188 clear_cpu_cap(c, X86_FEATURE_PAT); 188 clear_cpu_cap(c, X86_FEATURE_PAT);
189 189
190#ifdef CONFIG_KMEMCHECK
191 /*
192 * P4s have a "fast strings" feature which causes single-
193 * stepping REP instructions to only generate a #DB on
194 * cache-line boundaries.
195 *
196 * Ingo Molnar reported a Pentium D (model 6) and a Xeon
197 * (model 2) with the same problem.
198 */
199 if (c->x86 == 15)
200 if (msr_clear_bit(MSR_IA32_MISC_ENABLE,
201 MSR_IA32_MISC_ENABLE_FAST_STRING_BIT) > 0)
202 pr_info("kmemcheck: Disabling fast string operations\n");
203#endif
204
205 /* 190 /*
206 * If fast string is not enabled in IA32_MISC_ENABLE for any reason, 191 * If fast string is not enabled in IA32_MISC_ENABLE for any reason,
207 * clear the fast string and enhanced fast string CPU capabilities. 192 * clear the fast string and enhanced fast string CPU capabilities.