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-rw-r--r--arch/tile/kernel/setup.c13
1 files changed, 0 insertions, 13 deletions
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index b79c312ca3cb..128a2d0b8650 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -1046,9 +1046,6 @@ void __cpuinit setup_cpu(int boot)
1046 arch_local_irq_unmask(INT_DMATLB_MISS); 1046 arch_local_irq_unmask(INT_DMATLB_MISS);
1047 arch_local_irq_unmask(INT_DMATLB_ACCESS); 1047 arch_local_irq_unmask(INT_DMATLB_ACCESS);
1048#endif 1048#endif
1049#if CHIP_HAS_SN_PROC()
1050 arch_local_irq_unmask(INT_SNITLB_MISS);
1051#endif
1052#ifdef __tilegx__ 1049#ifdef __tilegx__
1053 arch_local_irq_unmask(INT_SINGLE_STEP_K); 1050 arch_local_irq_unmask(INT_SINGLE_STEP_K);
1054#endif 1051#endif
@@ -1063,10 +1060,6 @@ void __cpuinit setup_cpu(int boot)
1063 /* Static network is not restricted. */ 1060 /* Static network is not restricted. */
1064 __insn_mtspr(SPR_MPL_SN_ACCESS_SET_0, 1); 1061 __insn_mtspr(SPR_MPL_SN_ACCESS_SET_0, 1);
1065#endif 1062#endif
1066#if CHIP_HAS_SN_PROC()
1067 __insn_mtspr(SPR_MPL_SN_NOTIFY_SET_0, 1);
1068 __insn_mtspr(SPR_MPL_SN_CPL_SET_0, 1);
1069#endif
1070 1063
1071 /* 1064 /*
1072 * Set the MPL for interrupt control 0 & 1 to the corresponding 1065 * Set the MPL for interrupt control 0 & 1 to the corresponding
@@ -1291,7 +1284,6 @@ static void __init validate_va(void)
1291struct cpumask __write_once cpu_lotar_map; 1284struct cpumask __write_once cpu_lotar_map;
1292EXPORT_SYMBOL(cpu_lotar_map); 1285EXPORT_SYMBOL(cpu_lotar_map);
1293 1286
1294#if CHIP_HAS_CBOX_HOME_MAP()
1295/* 1287/*
1296 * hash_for_home_map lists all the tiles that hash-for-home data 1288 * hash_for_home_map lists all the tiles that hash-for-home data
1297 * will be cached on. Note that this may includes tiles that are not 1289 * will be cached on. Note that this may includes tiles that are not
@@ -1301,7 +1293,6 @@ EXPORT_SYMBOL(cpu_lotar_map);
1301 */ 1293 */
1302struct cpumask hash_for_home_map; 1294struct cpumask hash_for_home_map;
1303EXPORT_SYMBOL(hash_for_home_map); 1295EXPORT_SYMBOL(hash_for_home_map);
1304#endif
1305 1296
1306/* 1297/*
1307 * cpu_cacheable_map lists all the cpus whose caches the hypervisor can 1298 * cpu_cacheable_map lists all the cpus whose caches the hypervisor can
@@ -1394,7 +1385,6 @@ static void __init setup_cpu_maps(void)
1394 cpu_lotar_map = *cpu_possible_mask; 1385 cpu_lotar_map = *cpu_possible_mask;
1395 } 1386 }
1396 1387
1397#if CHIP_HAS_CBOX_HOME_MAP()
1398 /* Retrieve set of CPUs used for hash-for-home caching */ 1388 /* Retrieve set of CPUs used for hash-for-home caching */
1399 rc = hv_inquire_tiles(HV_INQ_TILES_HFH_CACHE, 1389 rc = hv_inquire_tiles(HV_INQ_TILES_HFH_CACHE,
1400 (HV_VirtAddr) hash_for_home_map.bits, 1390 (HV_VirtAddr) hash_for_home_map.bits,
@@ -1402,9 +1392,6 @@ static void __init setup_cpu_maps(void)
1402 if (rc < 0) 1392 if (rc < 0)
1403 early_panic("hv_inquire_tiles(HFH_CACHE) failed: rc %d\n", rc); 1393 early_panic("hv_inquire_tiles(HFH_CACHE) failed: rc %d\n", rc);
1404 cpumask_or(&cpu_cacheable_map, cpu_possible_mask, &hash_for_home_map); 1394 cpumask_or(&cpu_cacheable_map, cpu_possible_mask, &hash_for_home_map);
1405#else
1406 cpu_cacheable_map = *cpu_possible_mask;
1407#endif
1408} 1395}
1409 1396
1410 1397