diff options
Diffstat (limited to 'arch/sh/kernel/cpu/sh4/fpu.c')
-rw-r--r-- | arch/sh/kernel/cpu/sh4/fpu.c | 159 |
1 files changed, 39 insertions, 120 deletions
diff --git a/arch/sh/kernel/cpu/sh4/fpu.c b/arch/sh/kernel/cpu/sh4/fpu.c index e97857aec8a0..447482d7f65e 100644 --- a/arch/sh/kernel/cpu/sh4/fpu.c +++ b/arch/sh/kernel/cpu/sh4/fpu.c | |||
@@ -85,14 +85,14 @@ void save_fpu(struct task_struct *tsk) | |||
85 | "fmov.s fr1, @-%0\n\t" | 85 | "fmov.s fr1, @-%0\n\t" |
86 | "fmov.s fr0, @-%0\n\t" | 86 | "fmov.s fr0, @-%0\n\t" |
87 | "lds %3, fpscr\n\t":"=r" (dummy) | 87 | "lds %3, fpscr\n\t":"=r" (dummy) |
88 | :"0"((char *)(&tsk->thread.fpu.hard.status)), | 88 | :"0"((char *)(&tsk->thread.xstate->hardfpu.status)), |
89 | "r"(FPSCR_RCHG), "r"(FPSCR_INIT) | 89 | "r"(FPSCR_RCHG), "r"(FPSCR_INIT) |
90 | :"memory"); | 90 | :"memory"); |
91 | 91 | ||
92 | disable_fpu(); | 92 | disable_fpu(); |
93 | } | 93 | } |
94 | 94 | ||
95 | static void restore_fpu(struct task_struct *tsk) | 95 | void restore_fpu(struct task_struct *tsk) |
96 | { | 96 | { |
97 | unsigned long dummy; | 97 | unsigned long dummy; |
98 | 98 | ||
@@ -135,62 +135,11 @@ static void restore_fpu(struct task_struct *tsk) | |||
135 | "lds.l @%0+, fpscr\n\t" | 135 | "lds.l @%0+, fpscr\n\t" |
136 | "lds.l @%0+, fpul\n\t" | 136 | "lds.l @%0+, fpul\n\t" |
137 | :"=r" (dummy) | 137 | :"=r" (dummy) |
138 | :"0"(&tsk->thread.fpu), "r"(FPSCR_RCHG) | 138 | :"0" (tsk->thread.xstate), "r" (FPSCR_RCHG) |
139 | :"memory"); | 139 | :"memory"); |
140 | disable_fpu(); | 140 | disable_fpu(); |
141 | } | 141 | } |
142 | 142 | ||
143 | /* | ||
144 | * Load the FPU with signalling NANS. This bit pattern we're using | ||
145 | * has the property that no matter wether considered as single or as | ||
146 | * double precision represents signaling NANS. | ||
147 | */ | ||
148 | |||
149 | static void fpu_init(void) | ||
150 | { | ||
151 | enable_fpu(); | ||
152 | asm volatile ( "lds %0, fpul\n\t" | ||
153 | "lds %1, fpscr\n\t" | ||
154 | "fsts fpul, fr0\n\t" | ||
155 | "fsts fpul, fr1\n\t" | ||
156 | "fsts fpul, fr2\n\t" | ||
157 | "fsts fpul, fr3\n\t" | ||
158 | "fsts fpul, fr4\n\t" | ||
159 | "fsts fpul, fr5\n\t" | ||
160 | "fsts fpul, fr6\n\t" | ||
161 | "fsts fpul, fr7\n\t" | ||
162 | "fsts fpul, fr8\n\t" | ||
163 | "fsts fpul, fr9\n\t" | ||
164 | "fsts fpul, fr10\n\t" | ||
165 | "fsts fpul, fr11\n\t" | ||
166 | "fsts fpul, fr12\n\t" | ||
167 | "fsts fpul, fr13\n\t" | ||
168 | "fsts fpul, fr14\n\t" | ||
169 | "fsts fpul, fr15\n\t" | ||
170 | "frchg\n\t" | ||
171 | "fsts fpul, fr0\n\t" | ||
172 | "fsts fpul, fr1\n\t" | ||
173 | "fsts fpul, fr2\n\t" | ||
174 | "fsts fpul, fr3\n\t" | ||
175 | "fsts fpul, fr4\n\t" | ||
176 | "fsts fpul, fr5\n\t" | ||
177 | "fsts fpul, fr6\n\t" | ||
178 | "fsts fpul, fr7\n\t" | ||
179 | "fsts fpul, fr8\n\t" | ||
180 | "fsts fpul, fr9\n\t" | ||
181 | "fsts fpul, fr10\n\t" | ||
182 | "fsts fpul, fr11\n\t" | ||
183 | "fsts fpul, fr12\n\t" | ||
184 | "fsts fpul, fr13\n\t" | ||
185 | "fsts fpul, fr14\n\t" | ||
186 | "fsts fpul, fr15\n\t" | ||
187 | "frchg\n\t" | ||
188 | "lds %2, fpscr\n\t" | ||
189 | : /* no output */ | ||
190 | :"r" (0), "r"(FPSCR_RCHG), "r"(FPSCR_INIT)); | ||
191 | disable_fpu(); | ||
192 | } | ||
193 | |||
194 | /** | 143 | /** |
195 | * denormal_to_double - Given denormalized float number, | 144 | * denormal_to_double - Given denormalized float number, |
196 | * store double float | 145 | * store double float |
@@ -282,9 +231,9 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
282 | /* fcnvsd */ | 231 | /* fcnvsd */ |
283 | struct task_struct *tsk = current; | 232 | struct task_struct *tsk = current; |
284 | 233 | ||
285 | if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR)) | 234 | if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR)) |
286 | /* FPU error */ | 235 | /* FPU error */ |
287 | denormal_to_double(&tsk->thread.fpu.hard, | 236 | denormal_to_double(&tsk->thread.xstate->hardfpu, |
288 | (finsn >> 8) & 0xf); | 237 | (finsn >> 8) & 0xf); |
289 | else | 238 | else |
290 | return 0; | 239 | return 0; |
@@ -300,9 +249,9 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
300 | 249 | ||
301 | n = (finsn >> 8) & 0xf; | 250 | n = (finsn >> 8) & 0xf; |
302 | m = (finsn >> 4) & 0xf; | 251 | m = (finsn >> 4) & 0xf; |
303 | hx = tsk->thread.fpu.hard.fp_regs[n]; | 252 | hx = tsk->thread.xstate->hardfpu.fp_regs[n]; |
304 | hy = tsk->thread.fpu.hard.fp_regs[m]; | 253 | hy = tsk->thread.xstate->hardfpu.fp_regs[m]; |
305 | fpscr = tsk->thread.fpu.hard.fpscr; | 254 | fpscr = tsk->thread.xstate->hardfpu.fpscr; |
306 | prec = fpscr & FPSCR_DBL_PRECISION; | 255 | prec = fpscr & FPSCR_DBL_PRECISION; |
307 | 256 | ||
308 | if ((fpscr & FPSCR_CAUSE_ERROR) | 257 | if ((fpscr & FPSCR_CAUSE_ERROR) |
@@ -312,18 +261,18 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
312 | 261 | ||
313 | /* FPU error because of denormal (doubles) */ | 262 | /* FPU error because of denormal (doubles) */ |
314 | llx = ((long long)hx << 32) | 263 | llx = ((long long)hx << 32) |
315 | | tsk->thread.fpu.hard.fp_regs[n + 1]; | 264 | | tsk->thread.xstate->hardfpu.fp_regs[n + 1]; |
316 | lly = ((long long)hy << 32) | 265 | lly = ((long long)hy << 32) |
317 | | tsk->thread.fpu.hard.fp_regs[m + 1]; | 266 | | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; |
318 | llx = float64_mul(llx, lly); | 267 | llx = float64_mul(llx, lly); |
319 | tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; | 268 | tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32; |
320 | tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff; | 269 | tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff; |
321 | } else if ((fpscr & FPSCR_CAUSE_ERROR) | 270 | } else if ((fpscr & FPSCR_CAUSE_ERROR) |
322 | && (!prec && ((hx & 0x7fffffff) < 0x00800000 | 271 | && (!prec && ((hx & 0x7fffffff) < 0x00800000 |
323 | || (hy & 0x7fffffff) < 0x00800000))) { | 272 | || (hy & 0x7fffffff) < 0x00800000))) { |
324 | /* FPU error because of denormal (floats) */ | 273 | /* FPU error because of denormal (floats) */ |
325 | hx = float32_mul(hx, hy); | 274 | hx = float32_mul(hx, hy); |
326 | tsk->thread.fpu.hard.fp_regs[n] = hx; | 275 | tsk->thread.xstate->hardfpu.fp_regs[n] = hx; |
327 | } else | 276 | } else |
328 | return 0; | 277 | return 0; |
329 | 278 | ||
@@ -338,9 +287,9 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
338 | 287 | ||
339 | n = (finsn >> 8) & 0xf; | 288 | n = (finsn >> 8) & 0xf; |
340 | m = (finsn >> 4) & 0xf; | 289 | m = (finsn >> 4) & 0xf; |
341 | hx = tsk->thread.fpu.hard.fp_regs[n]; | 290 | hx = tsk->thread.xstate->hardfpu.fp_regs[n]; |
342 | hy = tsk->thread.fpu.hard.fp_regs[m]; | 291 | hy = tsk->thread.xstate->hardfpu.fp_regs[m]; |
343 | fpscr = tsk->thread.fpu.hard.fpscr; | 292 | fpscr = tsk->thread.xstate->hardfpu.fpscr; |
344 | prec = fpscr & FPSCR_DBL_PRECISION; | 293 | prec = fpscr & FPSCR_DBL_PRECISION; |
345 | 294 | ||
346 | if ((fpscr & FPSCR_CAUSE_ERROR) | 295 | if ((fpscr & FPSCR_CAUSE_ERROR) |
@@ -350,15 +299,15 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
350 | 299 | ||
351 | /* FPU error because of denormal (doubles) */ | 300 | /* FPU error because of denormal (doubles) */ |
352 | llx = ((long long)hx << 32) | 301 | llx = ((long long)hx << 32) |
353 | | tsk->thread.fpu.hard.fp_regs[n + 1]; | 302 | | tsk->thread.xstate->hardfpu.fp_regs[n + 1]; |
354 | lly = ((long long)hy << 32) | 303 | lly = ((long long)hy << 32) |
355 | | tsk->thread.fpu.hard.fp_regs[m + 1]; | 304 | | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; |
356 | if ((finsn & 0xf00f) == 0xf000) | 305 | if ((finsn & 0xf00f) == 0xf000) |
357 | llx = float64_add(llx, lly); | 306 | llx = float64_add(llx, lly); |
358 | else | 307 | else |
359 | llx = float64_sub(llx, lly); | 308 | llx = float64_sub(llx, lly); |
360 | tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; | 309 | tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32; |
361 | tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff; | 310 | tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff; |
362 | } else if ((fpscr & FPSCR_CAUSE_ERROR) | 311 | } else if ((fpscr & FPSCR_CAUSE_ERROR) |
363 | && (!prec && ((hx & 0x7fffffff) < 0x00800000 | 312 | && (!prec && ((hx & 0x7fffffff) < 0x00800000 |
364 | || (hy & 0x7fffffff) < 0x00800000))) { | 313 | || (hy & 0x7fffffff) < 0x00800000))) { |
@@ -367,7 +316,7 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
367 | hx = float32_add(hx, hy); | 316 | hx = float32_add(hx, hy); |
368 | else | 317 | else |
369 | hx = float32_sub(hx, hy); | 318 | hx = float32_sub(hx, hy); |
370 | tsk->thread.fpu.hard.fp_regs[n] = hx; | 319 | tsk->thread.xstate->hardfpu.fp_regs[n] = hx; |
371 | } else | 320 | } else |
372 | return 0; | 321 | return 0; |
373 | 322 | ||
@@ -382,9 +331,9 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
382 | 331 | ||
383 | n = (finsn >> 8) & 0xf; | 332 | n = (finsn >> 8) & 0xf; |
384 | m = (finsn >> 4) & 0xf; | 333 | m = (finsn >> 4) & 0xf; |
385 | hx = tsk->thread.fpu.hard.fp_regs[n]; | 334 | hx = tsk->thread.xstate->hardfpu.fp_regs[n]; |
386 | hy = tsk->thread.fpu.hard.fp_regs[m]; | 335 | hy = tsk->thread.xstate->hardfpu.fp_regs[m]; |
387 | fpscr = tsk->thread.fpu.hard.fpscr; | 336 | fpscr = tsk->thread.xstate->hardfpu.fpscr; |
388 | prec = fpscr & FPSCR_DBL_PRECISION; | 337 | prec = fpscr & FPSCR_DBL_PRECISION; |
389 | 338 | ||
390 | if ((fpscr & FPSCR_CAUSE_ERROR) | 339 | if ((fpscr & FPSCR_CAUSE_ERROR) |
@@ -394,20 +343,20 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
394 | 343 | ||
395 | /* FPU error because of denormal (doubles) */ | 344 | /* FPU error because of denormal (doubles) */ |
396 | llx = ((long long)hx << 32) | 345 | llx = ((long long)hx << 32) |
397 | | tsk->thread.fpu.hard.fp_regs[n + 1]; | 346 | | tsk->thread.xstate->hardfpu.fp_regs[n + 1]; |
398 | lly = ((long long)hy << 32) | 347 | lly = ((long long)hy << 32) |
399 | | tsk->thread.fpu.hard.fp_regs[m + 1]; | 348 | | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; |
400 | 349 | ||
401 | llx = float64_div(llx, lly); | 350 | llx = float64_div(llx, lly); |
402 | 351 | ||
403 | tsk->thread.fpu.hard.fp_regs[n] = llx >> 32; | 352 | tsk->thread.xstate->hardfpu.fp_regs[n] = llx >> 32; |
404 | tsk->thread.fpu.hard.fp_regs[n + 1] = llx & 0xffffffff; | 353 | tsk->thread.xstate->hardfpu.fp_regs[n + 1] = llx & 0xffffffff; |
405 | } else if ((fpscr & FPSCR_CAUSE_ERROR) | 354 | } else if ((fpscr & FPSCR_CAUSE_ERROR) |
406 | && (!prec && ((hx & 0x7fffffff) < 0x00800000 | 355 | && (!prec && ((hx & 0x7fffffff) < 0x00800000 |
407 | || (hy & 0x7fffffff) < 0x00800000))) { | 356 | || (hy & 0x7fffffff) < 0x00800000))) { |
408 | /* FPU error because of denormal (floats) */ | 357 | /* FPU error because of denormal (floats) */ |
409 | hx = float32_div(hx, hy); | 358 | hx = float32_div(hx, hy); |
410 | tsk->thread.fpu.hard.fp_regs[n] = hx; | 359 | tsk->thread.xstate->hardfpu.fp_regs[n] = hx; |
411 | } else | 360 | } else |
412 | return 0; | 361 | return 0; |
413 | 362 | ||
@@ -420,17 +369,17 @@ static int ieee_fpe_handler(struct pt_regs *regs) | |||
420 | unsigned int hx; | 369 | unsigned int hx; |
421 | 370 | ||
422 | m = (finsn >> 8) & 0x7; | 371 | m = (finsn >> 8) & 0x7; |
423 | hx = tsk->thread.fpu.hard.fp_regs[m]; | 372 | hx = tsk->thread.xstate->hardfpu.fp_regs[m]; |
424 | 373 | ||
425 | if ((tsk->thread.fpu.hard.fpscr & FPSCR_CAUSE_ERROR) | 374 | if ((tsk->thread.xstate->hardfpu.fpscr & FPSCR_CAUSE_ERROR) |
426 | && ((hx & 0x7fffffff) < 0x00100000)) { | 375 | && ((hx & 0x7fffffff) < 0x00100000)) { |
427 | /* subnormal double to float conversion */ | 376 | /* subnormal double to float conversion */ |
428 | long long llx; | 377 | long long llx; |
429 | 378 | ||
430 | llx = ((long long)tsk->thread.fpu.hard.fp_regs[m] << 32) | 379 | llx = ((long long)tsk->thread.xstate->hardfpu.fp_regs[m] << 32) |
431 | | tsk->thread.fpu.hard.fp_regs[m + 1]; | 380 | | tsk->thread.xstate->hardfpu.fp_regs[m + 1]; |
432 | 381 | ||
433 | tsk->thread.fpu.hard.fpul = float64_to_float32(llx); | 382 | tsk->thread.xstate->hardfpu.fpul = float64_to_float32(llx); |
434 | } else | 383 | } else |
435 | return 0; | 384 | return 0; |
436 | 385 | ||
@@ -449,7 +398,7 @@ void float_raise(unsigned int flags) | |||
449 | int float_rounding_mode(void) | 398 | int float_rounding_mode(void) |
450 | { | 399 | { |
451 | struct task_struct *tsk = current; | 400 | struct task_struct *tsk = current; |
452 | int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.fpu.hard.fpscr); | 401 | int roundingMode = FPSCR_ROUNDING_MODE(tsk->thread.xstate->hardfpu.fpscr); |
453 | return roundingMode; | 402 | return roundingMode; |
454 | } | 403 | } |
455 | 404 | ||
@@ -461,16 +410,16 @@ BUILD_TRAP_HANDLER(fpu_error) | |||
461 | __unlazy_fpu(tsk, regs); | 410 | __unlazy_fpu(tsk, regs); |
462 | fpu_exception_flags = 0; | 411 | fpu_exception_flags = 0; |
463 | if (ieee_fpe_handler(regs)) { | 412 | if (ieee_fpe_handler(regs)) { |
464 | tsk->thread.fpu.hard.fpscr &= | 413 | tsk->thread.xstate->hardfpu.fpscr &= |
465 | ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK); | 414 | ~(FPSCR_CAUSE_MASK | FPSCR_FLAG_MASK); |
466 | tsk->thread.fpu.hard.fpscr |= fpu_exception_flags; | 415 | tsk->thread.xstate->hardfpu.fpscr |= fpu_exception_flags; |
467 | /* Set the FPSCR flag as well as cause bits - simply | 416 | /* Set the FPSCR flag as well as cause bits - simply |
468 | * replicate the cause */ | 417 | * replicate the cause */ |
469 | tsk->thread.fpu.hard.fpscr |= (fpu_exception_flags >> 10); | 418 | tsk->thread.xstate->hardfpu.fpscr |= (fpu_exception_flags >> 10); |
470 | grab_fpu(regs); | 419 | grab_fpu(regs); |
471 | restore_fpu(tsk); | 420 | restore_fpu(tsk); |
472 | task_thread_info(tsk)->status |= TS_USEDFPU; | 421 | task_thread_info(tsk)->status |= TS_USEDFPU; |
473 | if ((((tsk->thread.fpu.hard.fpscr & FPSCR_ENABLE_MASK) >> 7) & | 422 | if ((((tsk->thread.xstate->hardfpu.fpscr & FPSCR_ENABLE_MASK) >> 7) & |
474 | (fpu_exception_flags >> 2)) == 0) { | 423 | (fpu_exception_flags >> 2)) == 0) { |
475 | return; | 424 | return; |
476 | } | 425 | } |
@@ -478,33 +427,3 @@ BUILD_TRAP_HANDLER(fpu_error) | |||
478 | 427 | ||
479 | force_sig(SIGFPE, tsk); | 428 | force_sig(SIGFPE, tsk); |
480 | } | 429 | } |
481 | |||
482 | void fpu_state_restore(struct pt_regs *regs) | ||
483 | { | ||
484 | struct task_struct *tsk = current; | ||
485 | |||
486 | grab_fpu(regs); | ||
487 | if (unlikely(!user_mode(regs))) { | ||
488 | printk(KERN_ERR "BUG: FPU is used in kernel mode.\n"); | ||
489 | BUG(); | ||
490 | return; | ||
491 | } | ||
492 | |||
493 | if (likely(used_math())) { | ||
494 | /* Using the FPU again. */ | ||
495 | restore_fpu(tsk); | ||
496 | } else { | ||
497 | /* First time FPU user. */ | ||
498 | fpu_init(); | ||
499 | set_used_math(); | ||
500 | } | ||
501 | task_thread_info(tsk)->status |= TS_USEDFPU; | ||
502 | tsk->fpu_counter++; | ||
503 | } | ||
504 | |||
505 | BUILD_TRAP_HANDLER(fpu_state_restore) | ||
506 | { | ||
507 | TRAP_HANDLER_DECL; | ||
508 | |||
509 | fpu_state_restore(regs); | ||
510 | } | ||