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-rw-r--r--arch/riscv/kernel/cpu.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3a5a2ee31547..b4a7d4427fbb 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node)
64 64
65static void print_isa(struct seq_file *f, const char *orig_isa) 65static void print_isa(struct seq_file *f, const char *orig_isa)
66{ 66{
67 static const char *ext = "mafdc"; 67 static const char *ext = "mafdcsu";
68 const char *isa = orig_isa; 68 const char *isa = orig_isa;
69 const char *e; 69 const char *e;
70 70
@@ -88,11 +88,14 @@ static void print_isa(struct seq_file *f, const char *orig_isa)
88 /* 88 /*
89 * Check the rest of the ISA string for valid extensions, printing those 89 * Check the rest of the ISA string for valid extensions, printing those
90 * we find. RISC-V ISA strings define an order, so we only print the 90 * we find. RISC-V ISA strings define an order, so we only print the
91 * extension bits when they're in order. 91 * extension bits when they're in order. Hide the supervisor (S)
92 * extension from userspace as it's not accessible from there.
92 */ 93 */
93 for (e = ext; *e != '\0'; ++e) { 94 for (e = ext; *e != '\0'; ++e) {
94 if (isa[0] == e[0]) { 95 if (isa[0] == e[0]) {
95 seq_write(f, isa, 1); 96 if (isa[0] != 's')
97 seq_write(f, isa, 1);
98
96 isa++; 99 isa++;
97 } 100 }
98 } 101 }