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-rw-r--r--arch/powerpc/sysdev/cpm1.c18
-rw-r--r--arch/powerpc/sysdev/cpm2_pic.c32
-rw-r--r--arch/powerpc/sysdev/fsl_85xx_l2ctlr.c4
-rw-r--r--arch/powerpc/sysdev/fsl_msi.c111
-rw-r--r--arch/powerpc/sysdev/fsl_pci.c15
-rw-r--r--arch/powerpc/sysdev/fsl_pci.h17
-rw-r--r--arch/powerpc/sysdev/i8259.c42
-rw-r--r--arch/powerpc/sysdev/ipic.c54
-rw-r--r--arch/powerpc/sysdev/mpc8xx_pic.c32
-rw-r--r--arch/powerpc/sysdev/mpc8xxx_gpio.c46
-rw-r--r--arch/powerpc/sysdev/mpic.c137
-rw-r--r--arch/powerpc/sysdev/mpic.h5
-rw-r--r--arch/powerpc/sysdev/mpic_pasemi_msi.c18
-rw-r--r--arch/powerpc/sysdev/mpic_u3msi.c18
-rw-r--r--arch/powerpc/sysdev/mv64x60_dev.c2
-rw-r--r--arch/powerpc/sysdev/mv64x60_pic.c46
-rw-r--r--arch/powerpc/sysdev/qe_lib/qe_ic.c25
-rw-r--r--arch/powerpc/sysdev/tsi108_pci.c41
-rw-r--r--arch/powerpc/sysdev/uic.c59
-rw-r--r--arch/powerpc/sysdev/xilinx_intc.c48
20 files changed, 406 insertions, 364 deletions
diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 00852124ff4a..0476bcc7c3e1 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -56,32 +56,32 @@ static cpic8xx_t __iomem *cpic_reg;
56 56
57static struct irq_host *cpm_pic_host; 57static struct irq_host *cpm_pic_host;
58 58
59static void cpm_mask_irq(unsigned int irq) 59static void cpm_mask_irq(struct irq_data *d)
60{ 60{
61 unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; 61 unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq;
62 62
63 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); 63 clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
64} 64}
65 65
66static void cpm_unmask_irq(unsigned int irq) 66static void cpm_unmask_irq(struct irq_data *d)
67{ 67{
68 unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; 68 unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq;
69 69
70 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec)); 70 setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
71} 71}
72 72
73static void cpm_end_irq(unsigned int irq) 73static void cpm_end_irq(struct irq_data *d)
74{ 74{
75 unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq; 75 unsigned int cpm_vec = (unsigned int)irq_map[d->irq].hwirq;
76 76
77 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec)); 77 out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
78} 78}
79 79
80static struct irq_chip cpm_pic = { 80static struct irq_chip cpm_pic = {
81 .name = "CPM PIC", 81 .name = "CPM PIC",
82 .mask = cpm_mask_irq, 82 .irq_mask = cpm_mask_irq,
83 .unmask = cpm_unmask_irq, 83 .irq_unmask = cpm_unmask_irq,
84 .eoi = cpm_end_irq, 84 .irq_eoi = cpm_end_irq,
85}; 85};
86 86
87int cpm_get_irq(void) 87int cpm_get_irq(void)
diff --git a/arch/powerpc/sysdev/cpm2_pic.c b/arch/powerpc/sysdev/cpm2_pic.c
index fcea4ff825dd..473032556715 100644
--- a/arch/powerpc/sysdev/cpm2_pic.c
+++ b/arch/powerpc/sysdev/cpm2_pic.c
@@ -78,10 +78,10 @@ static const u_char irq_to_siubit[] = {
78 24, 25, 26, 27, 28, 29, 30, 31, 78 24, 25, 26, 27, 28, 29, 30, 31,
79}; 79};
80 80
81static void cpm2_mask_irq(unsigned int virq) 81static void cpm2_mask_irq(struct irq_data *d)
82{ 82{
83 int bit, word; 83 int bit, word;
84 unsigned int irq_nr = virq_to_hw(virq); 84 unsigned int irq_nr = virq_to_hw(d->irq);
85 85
86 bit = irq_to_siubit[irq_nr]; 86 bit = irq_to_siubit[irq_nr];
87 word = irq_to_siureg[irq_nr]; 87 word = irq_to_siureg[irq_nr];
@@ -90,10 +90,10 @@ static void cpm2_mask_irq(unsigned int virq)
90 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); 90 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
91} 91}
92 92
93static void cpm2_unmask_irq(unsigned int virq) 93static void cpm2_unmask_irq(struct irq_data *d)
94{ 94{
95 int bit, word; 95 int bit, word;
96 unsigned int irq_nr = virq_to_hw(virq); 96 unsigned int irq_nr = virq_to_hw(d->irq);
97 97
98 bit = irq_to_siubit[irq_nr]; 98 bit = irq_to_siubit[irq_nr];
99 word = irq_to_siureg[irq_nr]; 99 word = irq_to_siureg[irq_nr];
@@ -102,10 +102,10 @@ static void cpm2_unmask_irq(unsigned int virq)
102 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]); 102 out_be32(&cpm2_intctl->ic_simrh + word, ppc_cached_irq_mask[word]);
103} 103}
104 104
105static void cpm2_ack(unsigned int virq) 105static void cpm2_ack(struct irq_data *d)
106{ 106{
107 int bit, word; 107 int bit, word;
108 unsigned int irq_nr = virq_to_hw(virq); 108 unsigned int irq_nr = virq_to_hw(d->irq);
109 109
110 bit = irq_to_siubit[irq_nr]; 110 bit = irq_to_siubit[irq_nr];
111 word = irq_to_siureg[irq_nr]; 111 word = irq_to_siureg[irq_nr];
@@ -113,11 +113,11 @@ static void cpm2_ack(unsigned int virq)
113 out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit); 113 out_be32(&cpm2_intctl->ic_sipnrh + word, 1 << bit);
114} 114}
115 115
116static void cpm2_end_irq(unsigned int virq) 116static void cpm2_end_irq(struct irq_data *d)
117{ 117{
118 struct irq_desc *desc; 118 struct irq_desc *desc;
119 int bit, word; 119 int bit, word;
120 unsigned int irq_nr = virq_to_hw(virq); 120 unsigned int irq_nr = virq_to_hw(d->irq);
121 121
122 desc = irq_to_desc(irq_nr); 122 desc = irq_to_desc(irq_nr);
123 if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS)) 123 if (!(desc->status & (IRQ_DISABLED|IRQ_INPROGRESS))
@@ -137,10 +137,10 @@ static void cpm2_end_irq(unsigned int virq)
137 } 137 }
138} 138}
139 139
140static int cpm2_set_irq_type(unsigned int virq, unsigned int flow_type) 140static int cpm2_set_irq_type(struct irq_data *d, unsigned int flow_type)
141{ 141{
142 unsigned int src = virq_to_hw(virq); 142 unsigned int src = virq_to_hw(d->irq);
143 struct irq_desc *desc = irq_to_desc(virq); 143 struct irq_desc *desc = irq_to_desc(d->irq);
144 unsigned int vold, vnew, edibit; 144 unsigned int vold, vnew, edibit;
145 145
146 /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or 146 /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
@@ -199,11 +199,11 @@ err_sense:
199 199
200static struct irq_chip cpm2_pic = { 200static struct irq_chip cpm2_pic = {
201 .name = "CPM2 SIU", 201 .name = "CPM2 SIU",
202 .mask = cpm2_mask_irq, 202 .irq_mask = cpm2_mask_irq,
203 .unmask = cpm2_unmask_irq, 203 .irq_unmask = cpm2_unmask_irq,
204 .ack = cpm2_ack, 204 .irq_ack = cpm2_ack,
205 .eoi = cpm2_end_irq, 205 .irq_eoi = cpm2_end_irq,
206 .set_type = cpm2_set_irq_type, 206 .irq_set_type = cpm2_set_irq_type,
207}; 207};
208 208
209unsigned int cpm2_get_irq(void) 209unsigned int cpm2_get_irq(void)
diff --git a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
index 2b9f0c925326..5f88797dce73 100644
--- a/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
+++ b/arch/powerpc/sysdev/fsl_85xx_l2ctlr.c
@@ -93,14 +93,14 @@ static int __devinit mpc85xx_l2ctlr_of_probe(struct platform_device *dev)
93 l2cache_size = *prop; 93 l2cache_size = *prop;
94 94
95 sram_params.sram_size = get_cache_sram_size(); 95 sram_params.sram_size = get_cache_sram_size();
96 if (sram_params.sram_size <= 0) { 96 if ((int)sram_params.sram_size <= 0) {
97 dev_err(&dev->dev, 97 dev_err(&dev->dev,
98 "Entire L2 as cache, Aborting Cache-SRAM stuff\n"); 98 "Entire L2 as cache, Aborting Cache-SRAM stuff\n");
99 return -EINVAL; 99 return -EINVAL;
100 } 100 }
101 101
102 sram_params.sram_offset = get_cache_sram_offset(); 102 sram_params.sram_offset = get_cache_sram_offset();
103 if (sram_params.sram_offset <= 0) { 103 if ((int64_t)sram_params.sram_offset <= 0) {
104 dev_err(&dev->dev, 104 dev_err(&dev->dev,
105 "Entire L2 as cache, provide a valid sram offset\n"); 105 "Entire L2 as cache, provide a valid sram offset\n");
106 return -EINVAL; 106 return -EINVAL;
diff --git a/arch/powerpc/sysdev/fsl_msi.c b/arch/powerpc/sysdev/fsl_msi.c
index ee6a8a52ac71..58e09b2833f2 100644
--- a/arch/powerpc/sysdev/fsl_msi.c
+++ b/arch/powerpc/sysdev/fsl_msi.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. 2 * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
3 * 3 *
4 * Author: Tony Li <tony.li@freescale.com> 4 * Author: Tony Li <tony.li@freescale.com>
5 * Jason Jin <Jason.jin@freescale.com> 5 * Jason Jin <Jason.jin@freescale.com>
@@ -47,14 +47,14 @@ static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
47 * We do not need this actually. The MSIR register has been read once 47 * We do not need this actually. The MSIR register has been read once
48 * in the cascade interrupt. So, this MSI interrupt has been acked 48 * in the cascade interrupt. So, this MSI interrupt has been acked
49*/ 49*/
50static void fsl_msi_end_irq(unsigned int virq) 50static void fsl_msi_end_irq(struct irq_data *d)
51{ 51{
52} 52}
53 53
54static struct irq_chip fsl_msi_chip = { 54static struct irq_chip fsl_msi_chip = {
55 .irq_mask = mask_msi_irq, 55 .irq_mask = mask_msi_irq,
56 .irq_unmask = unmask_msi_irq, 56 .irq_unmask = unmask_msi_irq,
57 .ack = fsl_msi_end_irq, 57 .irq_ack = fsl_msi_end_irq,
58 .name = "FSL-MSI", 58 .name = "FSL-MSI",
59}; 59};
60 60
@@ -183,6 +183,7 @@ out_free:
183 183
184static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc) 184static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
185{ 185{
186 struct irq_chip *chip = get_irq_desc_chip(desc);
186 unsigned int cascade_irq; 187 unsigned int cascade_irq;
187 struct fsl_msi *msi_data; 188 struct fsl_msi *msi_data;
188 int msir_index = -1; 189 int msir_index = -1;
@@ -196,11 +197,11 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
196 197
197 raw_spin_lock(&desc->lock); 198 raw_spin_lock(&desc->lock);
198 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) { 199 if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
199 if (desc->chip->mask_ack) 200 if (chip->irq_mask_ack)
200 desc->chip->mask_ack(irq); 201 chip->irq_mask_ack(&desc->irq_data);
201 else { 202 else {
202 desc->chip->mask(irq); 203 chip->irq_mask(&desc->irq_data);
203 desc->chip->ack(irq); 204 chip->irq_ack(&desc->irq_data);
204 } 205 }
205 } 206 }
206 207
@@ -238,11 +239,11 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
238 239
239 switch (msi_data->feature & FSL_PIC_IP_MASK) { 240 switch (msi_data->feature & FSL_PIC_IP_MASK) {
240 case FSL_PIC_IP_MPIC: 241 case FSL_PIC_IP_MPIC:
241 desc->chip->eoi(irq); 242 chip->irq_eoi(&desc->irq_data);
242 break; 243 break;
243 case FSL_PIC_IP_IPIC: 244 case FSL_PIC_IP_IPIC:
244 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) 245 if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
245 desc->chip->unmask(irq); 246 chip->irq_unmask(&desc->irq_data);
246 break; 247 break;
247 } 248 }
248unlock: 249unlock:
@@ -273,18 +274,46 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
273 return 0; 274 return 0;
274} 275}
275 276
277static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
278 struct platform_device *dev,
279 int offset, int irq_index)
280{
281 struct fsl_msi_cascade_data *cascade_data = NULL;
282 int virt_msir;
283
284 virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
285 if (virt_msir == NO_IRQ) {
286 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
287 __func__, irq_index);
288 return 0;
289 }
290
291 cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
292 if (!cascade_data) {
293 dev_err(&dev->dev, "No memory for MSI cascade data\n");
294 return -ENOMEM;
295 }
296
297 msi->msi_virqs[irq_index] = virt_msir;
298 cascade_data->index = offset + irq_index;
299 cascade_data->msi_data = msi;
300 set_irq_data(virt_msir, cascade_data);
301 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
302
303 return 0;
304}
305
276static int __devinit fsl_of_msi_probe(struct platform_device *dev) 306static int __devinit fsl_of_msi_probe(struct platform_device *dev)
277{ 307{
278 struct fsl_msi *msi; 308 struct fsl_msi *msi;
279 struct resource res; 309 struct resource res;
280 int err, i, count; 310 int err, i, j, irq_index, count;
281 int rc; 311 int rc;
282 int virt_msir;
283 const u32 *p; 312 const u32 *p;
284 struct fsl_msi_feature *features; 313 struct fsl_msi_feature *features;
285 struct fsl_msi_cascade_data *cascade_data = NULL;
286 int len; 314 int len;
287 u32 offset; 315 u32 offset;
316 static const u32 all_avail[] = { 0, NR_MSI_IRQS };
288 317
289 if (!dev->dev.of_match) 318 if (!dev->dev.of_match)
290 return -EINVAL; 319 return -EINVAL;
@@ -335,42 +364,34 @@ static int __devinit fsl_of_msi_probe(struct platform_device *dev)
335 goto error_out; 364 goto error_out;
336 } 365 }
337 366
338 p = of_get_property(dev->dev.of_node, "interrupts", &count); 367 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
339 if (!p) { 368 if (p && len % (2 * sizeof(u32)) != 0) {
340 dev_err(&dev->dev, "no interrupts property found on %s\n", 369 dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
341 dev->dev.of_node->full_name); 370 __func__);
342 err = -ENODEV;
343 goto error_out;
344 }
345 if (count % 8 != 0) {
346 dev_err(&dev->dev, "Malformed interrupts property on %s\n",
347 dev->dev.of_node->full_name);
348 err = -EINVAL; 371 err = -EINVAL;
349 goto error_out; 372 goto error_out;
350 } 373 }
351 offset = 0; 374
352 p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len); 375 if (!p)
353 if (p) 376 p = all_avail;
354 offset = *p / IRQS_PER_MSI_REG; 377
355 378 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
356 count /= sizeof(u32); 379 if (p[i * 2] % IRQS_PER_MSI_REG ||
357 for (i = 0; i < min(count / 2, NR_MSI_REG); i++) { 380 p[i * 2 + 1] % IRQS_PER_MSI_REG) {
358 virt_msir = irq_of_parse_and_map(dev->dev.of_node, i); 381 printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
359 if (virt_msir != NO_IRQ) { 382 __func__, dev->dev.of_node->full_name,
360 cascade_data = kzalloc( 383 p[i * 2 + 1], p[i * 2]);
361 sizeof(struct fsl_msi_cascade_data), 384 err = -EINVAL;
362 GFP_KERNEL); 385 goto error_out;
363 if (!cascade_data) { 386 }
364 dev_err(&dev->dev, 387
365 "No memory for MSI cascade data\n"); 388 offset = p[i * 2] / IRQS_PER_MSI_REG;
366 err = -ENOMEM; 389 count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
390
391 for (j = 0; j < count; j++, irq_index++) {
392 err = fsl_msi_setup_hwirq(msi, dev, offset, irq_index);
393 if (err)
367 goto error_out; 394 goto error_out;
368 }
369 msi->msi_virqs[i] = virt_msir;
370 cascade_data->index = i + offset;
371 cascade_data->msi_data = msi;
372 set_irq_data(virt_msir, (void *)cascade_data);
373 set_irq_chained_handler(virt_msir, fsl_msi_cascade);
374 } 395 }
375 } 396 }
376 397
diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 818f7c6c8fa1..f8f7f28c6343 100644
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC83xx/85xx/86xx PCI/PCIE support routing. 2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
3 * 3 *
4 * Copyright 2007-2010 Freescale Semiconductor, Inc. 4 * Copyright 2007-2011 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc. 5 * Copyright 2008-2009 MontaVista Software, Inc.
6 * 6 *
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com> 7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
@@ -99,7 +99,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
99 struct resource *rsrc) 99 struct resource *rsrc)
100{ 100{
101 struct ccsr_pci __iomem *pci; 101 struct ccsr_pci __iomem *pci;
102 int i, j, n, mem_log, win_idx = 2; 102 int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
103 u64 mem, sz, paddr_hi = 0; 103 u64 mem, sz, paddr_hi = 0;
104 u64 paddr_lo = ULLONG_MAX; 104 u64 paddr_lo = ULLONG_MAX;
105 u32 pcicsrbar = 0, pcicsrbar_sz; 105 u32 pcicsrbar = 0, pcicsrbar_sz;
@@ -109,6 +109,13 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
109 109
110 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n", 110 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
111 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1); 111 (u64)rsrc->start, (u64)rsrc->end - (u64)rsrc->start + 1);
112
113 if (of_device_is_compatible(hose->dn, "fsl,qoriq-pcie-v2.2")) {
114 win_idx = 2;
115 start_idx = 0;
116 end_idx = 3;
117 }
118
112 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1); 119 pci = ioremap(rsrc->start, rsrc->end - rsrc->start + 1);
113 if (!pci) { 120 if (!pci) {
114 dev_err(hose->parent, "Unable to map ATMU registers\n"); 121 dev_err(hose->parent, "Unable to map ATMU registers\n");
@@ -118,7 +125,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
118 /* Disable all windows (except powar0 since it's ignored) */ 125 /* Disable all windows (except powar0 since it's ignored) */
119 for(i = 1; i < 5; i++) 126 for(i = 1; i < 5; i++)
120 out_be32(&pci->pow[i].powar, 0); 127 out_be32(&pci->pow[i].powar, 0);
121 for(i = 0; i < 3; i++) 128 for (i = start_idx; i < end_idx; i++)
122 out_be32(&pci->piw[i].piwar, 0); 129 out_be32(&pci->piw[i].piwar, 0);
123 130
124 /* Setup outbound MEM window */ 131 /* Setup outbound MEM window */
@@ -204,7 +211,7 @@ static void __init setup_pci_atmu(struct pci_controller *hose,
204 mem_log++; 211 mem_log++;
205 } 212 }
206 213
207 piwar |= (mem_log - 1); 214 piwar |= ((mem_log - 1) & PIWAR_SZ_MASK);
208 215
209 /* Setup inbound memory window */ 216 /* Setup inbound memory window */
210 out_be32(&pci->piw[win_idx].pitar, 0x00000000); 217 out_be32(&pci->piw[win_idx].pitar, 0x00000000);
diff --git a/arch/powerpc/sysdev/fsl_pci.h b/arch/powerpc/sysdev/fsl_pci.h
index 8ad72a11f77b..a39ed5cc2c5a 100644
--- a/arch/powerpc/sysdev/fsl_pci.h
+++ b/arch/powerpc/sysdev/fsl_pci.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * MPC85xx/86xx PCI Express structure define 2 * MPC85xx/86xx PCI Express structure define
3 * 3 *
4 * Copyright 2007 Freescale Semiconductor, Inc 4 * Copyright 2007,2011 Freescale Semiconductor, Inc
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 7 * under the terms of the GNU General Public License as published by the
@@ -21,6 +21,7 @@
21#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 21#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
22#define PIWAR_READ_SNOOP 0x00050000 22#define PIWAR_READ_SNOOP 0x00050000
23#define PIWAR_WRITE_SNOOP 0x00005000 23#define PIWAR_WRITE_SNOOP 0x00005000
24#define PIWAR_SZ_MASK 0x0000003f
24 25
25/* PCI/PCI Express outbound window reg */ 26/* PCI/PCI Express outbound window reg */
26struct pci_outbound_window_regs { 27struct pci_outbound_window_regs {
@@ -49,7 +50,9 @@ struct ccsr_pci {
49 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */ 50 __be32 int_ack; /* 0x.008 - PCI Interrupt Acknowledge Register */
50 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */ 51 __be32 pex_otb_cpl_tor; /* 0x.00c - PCIE Outbound completion timeout register */
51 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */ 52 __be32 pex_conf_tor; /* 0x.010 - PCIE configuration timeout register */
52 u8 res2[12]; 53 __be32 pex_config; /* 0x.014 - PCIE CONFIG Register */
54 __be32 pex_int_status; /* 0x.018 - PCIE interrupt status */
55 u8 res2[4];
53 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */ 56 __be32 pex_pme_mes_dr; /* 0x.020 - PCIE PME and message detect register */
54 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */ 57 __be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
55 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */ 58 __be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
@@ -62,14 +65,14 @@ struct ccsr_pci {
62 * in all of the other outbound windows. 65 * in all of the other outbound windows.
63 */ 66 */
64 struct pci_outbound_window_regs pow[5]; 67 struct pci_outbound_window_regs pow[5];
65 68 u8 res14[96];
66 u8 res14[256]; 69 struct pci_inbound_window_regs pmit; /* 0xd00 - 0xd9c Inbound MSI */
67 70 u8 res6[96];
68/* PCI/PCI Express inbound window 3-1 71/* PCI/PCI Express inbound window 3-0
69 * inbound window 1 supports only a 32-bit base address and does not 72 * inbound window 1 supports only a 32-bit base address and does not
70 * define an inbound window base extended address register. 73 * define an inbound window base extended address register.
71 */ 74 */
72 struct pci_inbound_window_regs piw[3]; 75 struct pci_inbound_window_regs piw[4];
73 76
74 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */ 77 __be32 pex_err_dr; /* 0x.e00 - PCI/PCIE error detect register */
75 u8 res21[4]; 78 u8 res21[4];
diff --git a/arch/powerpc/sysdev/i8259.c b/arch/powerpc/sysdev/i8259.c
index 6323e70e6bf4..aeda4c8d0a0a 100644
--- a/arch/powerpc/sysdev/i8259.c
+++ b/arch/powerpc/sysdev/i8259.c
@@ -78,19 +78,19 @@ unsigned int i8259_irq(void)
78 return irq; 78 return irq;
79} 79}
80 80
81static void i8259_mask_and_ack_irq(unsigned int irq_nr) 81static void i8259_mask_and_ack_irq(struct irq_data *d)
82{ 82{
83 unsigned long flags; 83 unsigned long flags;
84 84
85 raw_spin_lock_irqsave(&i8259_lock, flags); 85 raw_spin_lock_irqsave(&i8259_lock, flags);
86 if (irq_nr > 7) { 86 if (d->irq > 7) {
87 cached_A1 |= 1 << (irq_nr-8); 87 cached_A1 |= 1 << (d->irq-8);
88 inb(0xA1); /* DUMMY */ 88 inb(0xA1); /* DUMMY */
89 outb(cached_A1, 0xA1); 89 outb(cached_A1, 0xA1);
90 outb(0x20, 0xA0); /* Non-specific EOI */ 90 outb(0x20, 0xA0); /* Non-specific EOI */
91 outb(0x20, 0x20); /* Non-specific EOI to cascade */ 91 outb(0x20, 0x20); /* Non-specific EOI to cascade */
92 } else { 92 } else {
93 cached_21 |= 1 << irq_nr; 93 cached_21 |= 1 << d->irq;
94 inb(0x21); /* DUMMY */ 94 inb(0x21); /* DUMMY */
95 outb(cached_21, 0x21); 95 outb(cached_21, 0x21);
96 outb(0x20, 0x20); /* Non-specific EOI */ 96 outb(0x20, 0x20); /* Non-specific EOI */
@@ -104,42 +104,42 @@ static void i8259_set_irq_mask(int irq_nr)
104 outb(cached_21,0x21); 104 outb(cached_21,0x21);
105} 105}
106 106
107static void i8259_mask_irq(unsigned int irq_nr) 107static void i8259_mask_irq(struct irq_data *d)
108{ 108{
109 unsigned long flags; 109 unsigned long flags;
110 110
111 pr_debug("i8259_mask_irq(%d)\n", irq_nr); 111 pr_debug("i8259_mask_irq(%d)\n", d->irq);
112 112
113 raw_spin_lock_irqsave(&i8259_lock, flags); 113 raw_spin_lock_irqsave(&i8259_lock, flags);
114 if (irq_nr < 8) 114 if (d->irq < 8)
115 cached_21 |= 1 << irq_nr; 115 cached_21 |= 1 << d->irq;
116 else 116 else
117 cached_A1 |= 1 << (irq_nr-8); 117 cached_A1 |= 1 << (d->irq-8);
118 i8259_set_irq_mask(irq_nr); 118 i8259_set_irq_mask(d->irq);
119 raw_spin_unlock_irqrestore(&i8259_lock, flags); 119 raw_spin_unlock_irqrestore(&i8259_lock, flags);
120} 120}
121 121
122static void i8259_unmask_irq(unsigned int irq_nr) 122static void i8259_unmask_irq(struct irq_data *d)
123{ 123{
124 unsigned long flags; 124 unsigned long flags;
125 125
126 pr_debug("i8259_unmask_irq(%d)\n", irq_nr); 126 pr_debug("i8259_unmask_irq(%d)\n", d->irq);
127 127
128 raw_spin_lock_irqsave(&i8259_lock, flags); 128 raw_spin_lock_irqsave(&i8259_lock, flags);
129 if (irq_nr < 8) 129 if (d->irq < 8)
130 cached_21 &= ~(1 << irq_nr); 130 cached_21 &= ~(1 << d->irq);
131 else 131 else
132 cached_A1 &= ~(1 << (irq_nr-8)); 132 cached_A1 &= ~(1 << (d->irq-8));
133 i8259_set_irq_mask(irq_nr); 133 i8259_set_irq_mask(d->irq);
134 raw_spin_unlock_irqrestore(&i8259_lock, flags); 134 raw_spin_unlock_irqrestore(&i8259_lock, flags);
135} 135}
136 136
137static struct irq_chip i8259_pic = { 137static struct irq_chip i8259_pic = {
138 .name = "i8259", 138 .name = "i8259",
139 .mask = i8259_mask_irq, 139 .irq_mask = i8259_mask_irq,
140 .disable = i8259_mask_irq, 140 .irq_disable = i8259_mask_irq,
141 .unmask = i8259_unmask_irq, 141 .irq_unmask = i8259_unmask_irq,
142 .mask_ack = i8259_mask_and_ack_irq, 142 .irq_mask_ack = i8259_mask_and_ack_irq,
143}; 143};
144 144
145static struct resource pic1_iores = { 145static struct resource pic1_iores = {
@@ -188,7 +188,7 @@ static int i8259_host_map(struct irq_host *h, unsigned int virq,
188static void i8259_host_unmap(struct irq_host *h, unsigned int virq) 188static void i8259_host_unmap(struct irq_host *h, unsigned int virq)
189{ 189{
190 /* Make sure irq is masked in hardware */ 190 /* Make sure irq is masked in hardware */
191 i8259_mask_irq(virq); 191 i8259_mask_irq(irq_get_irq_data(virq));
192 192
193 /* remove chip and handler */ 193 /* remove chip and handler */
194 set_irq_chip_and_handler(virq, NULL, NULL); 194 set_irq_chip_and_handler(virq, NULL, NULL);
diff --git a/arch/powerpc/sysdev/ipic.c b/arch/powerpc/sysdev/ipic.c
index d7b9b9c69287..497047dc986e 100644
--- a/arch/powerpc/sysdev/ipic.c
+++ b/arch/powerpc/sysdev/ipic.c
@@ -523,10 +523,10 @@ static inline struct ipic * ipic_from_irq(unsigned int virq)
523 523
524#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 524#define ipic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
525 525
526static void ipic_unmask_irq(unsigned int virq) 526static void ipic_unmask_irq(struct irq_data *d)
527{ 527{
528 struct ipic *ipic = ipic_from_irq(virq); 528 struct ipic *ipic = ipic_from_irq(d->irq);
529 unsigned int src = ipic_irq_to_hw(virq); 529 unsigned int src = ipic_irq_to_hw(d->irq);
530 unsigned long flags; 530 unsigned long flags;
531 u32 temp; 531 u32 temp;
532 532
@@ -539,10 +539,10 @@ static void ipic_unmask_irq(unsigned int virq)
539 raw_spin_unlock_irqrestore(&ipic_lock, flags); 539 raw_spin_unlock_irqrestore(&ipic_lock, flags);
540} 540}
541 541
542static void ipic_mask_irq(unsigned int virq) 542static void ipic_mask_irq(struct irq_data *d)
543{ 543{
544 struct ipic *ipic = ipic_from_irq(virq); 544 struct ipic *ipic = ipic_from_irq(d->irq);
545 unsigned int src = ipic_irq_to_hw(virq); 545 unsigned int src = ipic_irq_to_hw(d->irq);
546 unsigned long flags; 546 unsigned long flags;
547 u32 temp; 547 u32 temp;
548 548
@@ -559,10 +559,10 @@ static void ipic_mask_irq(unsigned int virq)
559 raw_spin_unlock_irqrestore(&ipic_lock, flags); 559 raw_spin_unlock_irqrestore(&ipic_lock, flags);
560} 560}
561 561
562static void ipic_ack_irq(unsigned int virq) 562static void ipic_ack_irq(struct irq_data *d)
563{ 563{
564 struct ipic *ipic = ipic_from_irq(virq); 564 struct ipic *ipic = ipic_from_irq(d->irq);
565 unsigned int src = ipic_irq_to_hw(virq); 565 unsigned int src = ipic_irq_to_hw(d->irq);
566 unsigned long flags; 566 unsigned long flags;
567 u32 temp; 567 u32 temp;
568 568
@@ -578,10 +578,10 @@ static void ipic_ack_irq(unsigned int virq)
578 raw_spin_unlock_irqrestore(&ipic_lock, flags); 578 raw_spin_unlock_irqrestore(&ipic_lock, flags);
579} 579}
580 580
581static void ipic_mask_irq_and_ack(unsigned int virq) 581static void ipic_mask_irq_and_ack(struct irq_data *d)
582{ 582{
583 struct ipic *ipic = ipic_from_irq(virq); 583 struct ipic *ipic = ipic_from_irq(d->irq);
584 unsigned int src = ipic_irq_to_hw(virq); 584 unsigned int src = ipic_irq_to_hw(d->irq);
585 unsigned long flags; 585 unsigned long flags;
586 u32 temp; 586 u32 temp;
587 587
@@ -601,11 +601,11 @@ static void ipic_mask_irq_and_ack(unsigned int virq)
601 raw_spin_unlock_irqrestore(&ipic_lock, flags); 601 raw_spin_unlock_irqrestore(&ipic_lock, flags);
602} 602}
603 603
604static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type) 604static int ipic_set_irq_type(struct irq_data *d, unsigned int flow_type)
605{ 605{
606 struct ipic *ipic = ipic_from_irq(virq); 606 struct ipic *ipic = ipic_from_irq(d->irq);
607 unsigned int src = ipic_irq_to_hw(virq); 607 unsigned int src = ipic_irq_to_hw(d->irq);
608 struct irq_desc *desc = irq_to_desc(virq); 608 struct irq_desc *desc = irq_to_desc(d->irq);
609 unsigned int vold, vnew, edibit; 609 unsigned int vold, vnew, edibit;
610 610
611 if (flow_type == IRQ_TYPE_NONE) 611 if (flow_type == IRQ_TYPE_NONE)
@@ -630,10 +630,10 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
630 if (flow_type & IRQ_TYPE_LEVEL_LOW) { 630 if (flow_type & IRQ_TYPE_LEVEL_LOW) {
631 desc->status |= IRQ_LEVEL; 631 desc->status |= IRQ_LEVEL;
632 desc->handle_irq = handle_level_irq; 632 desc->handle_irq = handle_level_irq;
633 desc->chip = &ipic_level_irq_chip; 633 desc->irq_data.chip = &ipic_level_irq_chip;
634 } else { 634 } else {
635 desc->handle_irq = handle_edge_irq; 635 desc->handle_irq = handle_edge_irq;
636 desc->chip = &ipic_edge_irq_chip; 636 desc->irq_data.chip = &ipic_edge_irq_chip;
637 } 637 }
638 638
639 /* only EXT IRQ senses are programmable on ipic 639 /* only EXT IRQ senses are programmable on ipic
@@ -661,19 +661,19 @@ static int ipic_set_irq_type(unsigned int virq, unsigned int flow_type)
661/* level interrupts and edge interrupts have different ack operations */ 661/* level interrupts and edge interrupts have different ack operations */
662static struct irq_chip ipic_level_irq_chip = { 662static struct irq_chip ipic_level_irq_chip = {
663 .name = "IPIC", 663 .name = "IPIC",
664 .unmask = ipic_unmask_irq, 664 .irq_unmask = ipic_unmask_irq,
665 .mask = ipic_mask_irq, 665 .irq_mask = ipic_mask_irq,
666 .mask_ack = ipic_mask_irq, 666 .irq_mask_ack = ipic_mask_irq,
667 .set_type = ipic_set_irq_type, 667 .irq_set_type = ipic_set_irq_type,
668}; 668};
669 669
670static struct irq_chip ipic_edge_irq_chip = { 670static struct irq_chip ipic_edge_irq_chip = {
671 .name = "IPIC", 671 .name = "IPIC",
672 .unmask = ipic_unmask_irq, 672 .irq_unmask = ipic_unmask_irq,
673 .mask = ipic_mask_irq, 673 .irq_mask = ipic_mask_irq,
674 .mask_ack = ipic_mask_irq_and_ack, 674 .irq_mask_ack = ipic_mask_irq_and_ack,
675 .ack = ipic_ack_irq, 675 .irq_ack = ipic_ack_irq,
676 .set_type = ipic_set_irq_type, 676 .irq_set_type = ipic_set_irq_type,
677}; 677};
678 678
679static int ipic_host_match(struct irq_host *h, struct device_node *node) 679static int ipic_host_match(struct irq_host *h, struct device_node *node)
diff --git a/arch/powerpc/sysdev/mpc8xx_pic.c b/arch/powerpc/sysdev/mpc8xx_pic.c
index 8c27d261aba8..1a75a7fb4a99 100644
--- a/arch/powerpc/sysdev/mpc8xx_pic.c
+++ b/arch/powerpc/sysdev/mpc8xx_pic.c
@@ -25,10 +25,10 @@ static sysconf8xx_t __iomem *siu_reg;
25 25
26int cpm_get_irq(struct pt_regs *regs); 26int cpm_get_irq(struct pt_regs *regs);
27 27
28static void mpc8xx_unmask_irq(unsigned int virq) 28static void mpc8xx_unmask_irq(struct irq_data *d)
29{ 29{
30 int bit, word; 30 int bit, word;
31 unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; 31 unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq;
32 32
33 bit = irq_nr & 0x1f; 33 bit = irq_nr & 0x1f;
34 word = irq_nr >> 5; 34 word = irq_nr >> 5;
@@ -37,10 +37,10 @@ static void mpc8xx_unmask_irq(unsigned int virq)
37 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); 37 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
38} 38}
39 39
40static void mpc8xx_mask_irq(unsigned int virq) 40static void mpc8xx_mask_irq(struct irq_data *d)
41{ 41{
42 int bit, word; 42 int bit, word;
43 unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; 43 unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq;
44 44
45 bit = irq_nr & 0x1f; 45 bit = irq_nr & 0x1f;
46 word = irq_nr >> 5; 46 word = irq_nr >> 5;
@@ -49,19 +49,19 @@ static void mpc8xx_mask_irq(unsigned int virq)
49 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); 49 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
50} 50}
51 51
52static void mpc8xx_ack(unsigned int virq) 52static void mpc8xx_ack(struct irq_data *d)
53{ 53{
54 int bit; 54 int bit;
55 unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; 55 unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq;
56 56
57 bit = irq_nr & 0x1f; 57 bit = irq_nr & 0x1f;
58 out_be32(&siu_reg->sc_sipend, 1 << (31-bit)); 58 out_be32(&siu_reg->sc_sipend, 1 << (31-bit));
59} 59}
60 60
61static void mpc8xx_end_irq(unsigned int virq) 61static void mpc8xx_end_irq(struct irq_data *d)
62{ 62{
63 int bit, word; 63 int bit, word;
64 unsigned int irq_nr = (unsigned int)irq_map[virq].hwirq; 64 unsigned int irq_nr = (unsigned int)irq_map[d->irq].hwirq;
65 65
66 bit = irq_nr & 0x1f; 66 bit = irq_nr & 0x1f;
67 word = irq_nr >> 5; 67 word = irq_nr >> 5;
@@ -70,9 +70,9 @@ static void mpc8xx_end_irq(unsigned int virq)
70 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]); 70 out_be32(&siu_reg->sc_simask, ppc_cached_irq_mask[word]);
71} 71}
72 72
73static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type) 73static int mpc8xx_set_irq_type(struct irq_data *d, unsigned int flow_type)
74{ 74{
75 struct irq_desc *desc = irq_to_desc(virq); 75 struct irq_desc *desc = irq_to_desc(d->irq);
76 76
77 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 77 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
78 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 78 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
@@ -80,7 +80,7 @@ static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
80 desc->status |= IRQ_LEVEL; 80 desc->status |= IRQ_LEVEL;
81 81
82 if (flow_type & IRQ_TYPE_EDGE_FALLING) { 82 if (flow_type & IRQ_TYPE_EDGE_FALLING) {
83 irq_hw_number_t hw = (unsigned int)irq_map[virq].hwirq; 83 irq_hw_number_t hw = (unsigned int)irq_map[d->irq].hwirq;
84 unsigned int siel = in_be32(&siu_reg->sc_siel); 84 unsigned int siel = in_be32(&siu_reg->sc_siel);
85 85
86 /* only external IRQ senses are programmable */ 86 /* only external IRQ senses are programmable */
@@ -95,11 +95,11 @@ static int mpc8xx_set_irq_type(unsigned int virq, unsigned int flow_type)
95 95
96static struct irq_chip mpc8xx_pic = { 96static struct irq_chip mpc8xx_pic = {
97 .name = "MPC8XX SIU", 97 .name = "MPC8XX SIU",
98 .unmask = mpc8xx_unmask_irq, 98 .irq_unmask = mpc8xx_unmask_irq,
99 .mask = mpc8xx_mask_irq, 99 .irq_mask = mpc8xx_mask_irq,
100 .ack = mpc8xx_ack, 100 .irq_ack = mpc8xx_ack,
101 .eoi = mpc8xx_end_irq, 101 .irq_eoi = mpc8xx_end_irq,
102 .set_type = mpc8xx_set_irq_type, 102 .irq_set_type = mpc8xx_set_irq_type,
103}; 103};
104 104
105unsigned int mpc8xx_get_irq(void) 105unsigned int mpc8xx_get_irq(void)
diff --git a/arch/powerpc/sysdev/mpc8xxx_gpio.c b/arch/powerpc/sysdev/mpc8xxx_gpio.c
index c48cd8178079..232e701245d7 100644
--- a/arch/powerpc/sysdev/mpc8xxx_gpio.c
+++ b/arch/powerpc/sysdev/mpc8xxx_gpio.c
@@ -155,43 +155,43 @@ static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
155 32 - ffs(mask))); 155 32 - ffs(mask)));
156} 156}
157 157
158static void mpc8xxx_irq_unmask(unsigned int virq) 158static void mpc8xxx_irq_unmask(struct irq_data *d)
159{ 159{
160 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 160 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
161 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 161 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
162 unsigned long flags; 162 unsigned long flags;
163 163
164 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 164 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
165 165
166 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); 166 setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
167 167
168 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 168 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
169} 169}
170 170
171static void mpc8xxx_irq_mask(unsigned int virq) 171static void mpc8xxx_irq_mask(struct irq_data *d)
172{ 172{
173 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 173 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
174 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 174 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
175 unsigned long flags; 175 unsigned long flags;
176 176
177 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 177 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
178 178
179 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq))); 179 clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
180 180
181 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 181 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
182} 182}
183 183
184static void mpc8xxx_irq_ack(unsigned int virq) 184static void mpc8xxx_irq_ack(struct irq_data *d)
185{ 185{
186 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 186 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
187 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 187 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
188 188
189 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq))); 189 out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
190} 190}
191 191
192static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type) 192static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
193{ 193{
194 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 194 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
195 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 195 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
196 unsigned long flags; 196 unsigned long flags;
197 197
@@ -199,14 +199,14 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
199 case IRQ_TYPE_EDGE_FALLING: 199 case IRQ_TYPE_EDGE_FALLING:
200 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 200 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
201 setbits32(mm->regs + GPIO_ICR, 201 setbits32(mm->regs + GPIO_ICR,
202 mpc8xxx_gpio2mask(virq_to_hw(virq))); 202 mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
203 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 203 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
204 break; 204 break;
205 205
206 case IRQ_TYPE_EDGE_BOTH: 206 case IRQ_TYPE_EDGE_BOTH:
207 spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 207 spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
208 clrbits32(mm->regs + GPIO_ICR, 208 clrbits32(mm->regs + GPIO_ICR,
209 mpc8xxx_gpio2mask(virq_to_hw(virq))); 209 mpc8xxx_gpio2mask(virq_to_hw(d->irq)));
210 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 210 spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
211 break; 211 break;
212 212
@@ -217,11 +217,11 @@ static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
217 return 0; 217 return 0;
218} 218}
219 219
220static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type) 220static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
221{ 221{
222 struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq); 222 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
223 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc; 223 struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
224 unsigned long gpio = virq_to_hw(virq); 224 unsigned long gpio = virq_to_hw(d->irq);
225 void __iomem *reg; 225 void __iomem *reg;
226 unsigned int shift; 226 unsigned int shift;
227 unsigned long flags; 227 unsigned long flags;
@@ -264,10 +264,10 @@ static int mpc512x_irq_set_type(unsigned int virq, unsigned int flow_type)
264 264
265static struct irq_chip mpc8xxx_irq_chip = { 265static struct irq_chip mpc8xxx_irq_chip = {
266 .name = "mpc8xxx-gpio", 266 .name = "mpc8xxx-gpio",
267 .unmask = mpc8xxx_irq_unmask, 267 .irq_unmask = mpc8xxx_irq_unmask,
268 .mask = mpc8xxx_irq_mask, 268 .irq_mask = mpc8xxx_irq_mask,
269 .ack = mpc8xxx_irq_ack, 269 .irq_ack = mpc8xxx_irq_ack,
270 .set_type = mpc8xxx_irq_set_type, 270 .irq_set_type = mpc8xxx_irq_set_type,
271}; 271};
272 272
273static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq, 273static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
@@ -276,7 +276,7 @@ static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
276 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data; 276 struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
277 277
278 if (mpc8xxx_gc->of_dev_id_data) 278 if (mpc8xxx_gc->of_dev_id_data)
279 mpc8xxx_irq_chip.set_type = mpc8xxx_gc->of_dev_id_data; 279 mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
280 280
281 set_irq_chip_data(virq, h->host_data); 281 set_irq_chip_data(virq, h->host_data);
282 set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq); 282 set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
@@ -310,6 +310,7 @@ static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
310 { .compatible = "fsl,mpc8572-gpio", }, 310 { .compatible = "fsl,mpc8572-gpio", },
311 { .compatible = "fsl,mpc8610-gpio", }, 311 { .compatible = "fsl,mpc8610-gpio", },
312 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, }, 312 { .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
313 { .compatible = "fsl,qoriq-gpio", },
313 {} 314 {}
314}; 315};
315 316
@@ -389,9 +390,6 @@ static int __init mpc8xxx_add_gpiochips(void)
389 for_each_matching_node(np, mpc8xxx_gpio_ids) 390 for_each_matching_node(np, mpc8xxx_gpio_ids)
390 mpc8xxx_add_controller(np); 391 mpc8xxx_add_controller(np);
391 392
392 for_each_compatible_node(np, NULL, "fsl,qoriq-gpio")
393 mpc8xxx_add_controller(np);
394
395 return 0; 393 return 0;
396} 394}
397arch_initcall(mpc8xxx_add_gpiochips); 395arch_initcall(mpc8xxx_add_gpiochips);
diff --git a/arch/powerpc/sysdev/mpic.c b/arch/powerpc/sysdev/mpic.c
index b0c8469e5ddd..eb7021815e2d 100644
--- a/arch/powerpc/sysdev/mpic.c
+++ b/arch/powerpc/sysdev/mpic.c
@@ -611,7 +611,7 @@ static struct mpic *mpic_find(unsigned int irq)
611 if (irq < NUM_ISA_INTERRUPTS) 611 if (irq < NUM_ISA_INTERRUPTS)
612 return NULL; 612 return NULL;
613 613
614 return irq_to_desc(irq)->chip_data; 614 return get_irq_chip_data(irq);
615} 615}
616 616
617/* Determine if the linux irq is an IPI */ 617/* Determine if the linux irq is an IPI */
@@ -636,16 +636,22 @@ static inline u32 mpic_physmask(u32 cpumask)
636 636
637#ifdef CONFIG_SMP 637#ifdef CONFIG_SMP
638/* Get the mpic structure from the IPI number */ 638/* Get the mpic structure from the IPI number */
639static inline struct mpic * mpic_from_ipi(unsigned int ipi) 639static inline struct mpic * mpic_from_ipi(struct irq_data *d)
640{ 640{
641 return irq_to_desc(ipi)->chip_data; 641 return irq_data_get_irq_chip_data(d);
642} 642}
643#endif 643#endif
644 644
645/* Get the mpic structure from the irq number */ 645/* Get the mpic structure from the irq number */
646static inline struct mpic * mpic_from_irq(unsigned int irq) 646static inline struct mpic * mpic_from_irq(unsigned int irq)
647{ 647{
648 return irq_to_desc(irq)->chip_data; 648 return get_irq_chip_data(irq);
649}
650
651/* Get the mpic structure from the irq data */
652static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
653{
654 return irq_data_get_irq_chip_data(d);
649} 655}
650 656
651/* Send an EOI */ 657/* Send an EOI */
@@ -660,13 +666,13 @@ static inline void mpic_eoi(struct mpic *mpic)
660 */ 666 */
661 667
662 668
663void mpic_unmask_irq(unsigned int irq) 669void mpic_unmask_irq(struct irq_data *d)
664{ 670{
665 unsigned int loops = 100000; 671 unsigned int loops = 100000;
666 struct mpic *mpic = mpic_from_irq(irq); 672 struct mpic *mpic = mpic_from_irq_data(d);
667 unsigned int src = mpic_irq_to_hw(irq); 673 unsigned int src = mpic_irq_to_hw(d->irq);
668 674
669 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, irq, src); 675 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
670 676
671 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 677 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
672 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & 678 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
@@ -681,13 +687,13 @@ void mpic_unmask_irq(unsigned int irq)
681 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK); 687 } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
682} 688}
683 689
684void mpic_mask_irq(unsigned int irq) 690void mpic_mask_irq(struct irq_data *d)
685{ 691{
686 unsigned int loops = 100000; 692 unsigned int loops = 100000;
687 struct mpic *mpic = mpic_from_irq(irq); 693 struct mpic *mpic = mpic_from_irq_data(d);
688 unsigned int src = mpic_irq_to_hw(irq); 694 unsigned int src = mpic_irq_to_hw(d->irq);
689 695
690 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, irq, src); 696 DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
691 697
692 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), 698 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
693 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) | 699 mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
@@ -703,12 +709,12 @@ void mpic_mask_irq(unsigned int irq)
703 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK)); 709 } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
704} 710}
705 711
706void mpic_end_irq(unsigned int irq) 712void mpic_end_irq(struct irq_data *d)
707{ 713{
708 struct mpic *mpic = mpic_from_irq(irq); 714 struct mpic *mpic = mpic_from_irq_data(d);
709 715
710#ifdef DEBUG_IRQ 716#ifdef DEBUG_IRQ
711 DBG("%s: end_irq: %d\n", mpic->name, irq); 717 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
712#endif 718#endif
713 /* We always EOI on end_irq() even for edge interrupts since that 719 /* We always EOI on end_irq() even for edge interrupts since that
714 * should only lower the priority, the MPIC should have properly 720 * should only lower the priority, the MPIC should have properly
@@ -720,51 +726,51 @@ void mpic_end_irq(unsigned int irq)
720 726
721#ifdef CONFIG_MPIC_U3_HT_IRQS 727#ifdef CONFIG_MPIC_U3_HT_IRQS
722 728
723static void mpic_unmask_ht_irq(unsigned int irq) 729static void mpic_unmask_ht_irq(struct irq_data *d)
724{ 730{
725 struct mpic *mpic = mpic_from_irq(irq); 731 struct mpic *mpic = mpic_from_irq_data(d);
726 unsigned int src = mpic_irq_to_hw(irq); 732 unsigned int src = mpic_irq_to_hw(d->irq);
727 733
728 mpic_unmask_irq(irq); 734 mpic_unmask_irq(d);
729 735
730 if (irq_to_desc(irq)->status & IRQ_LEVEL) 736 if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
731 mpic_ht_end_irq(mpic, src); 737 mpic_ht_end_irq(mpic, src);
732} 738}
733 739
734static unsigned int mpic_startup_ht_irq(unsigned int irq) 740static unsigned int mpic_startup_ht_irq(struct irq_data *d)
735{ 741{
736 struct mpic *mpic = mpic_from_irq(irq); 742 struct mpic *mpic = mpic_from_irq_data(d);
737 unsigned int src = mpic_irq_to_hw(irq); 743 unsigned int src = mpic_irq_to_hw(d->irq);
738 744
739 mpic_unmask_irq(irq); 745 mpic_unmask_irq(d);
740 mpic_startup_ht_interrupt(mpic, src, irq_to_desc(irq)->status); 746 mpic_startup_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
741 747
742 return 0; 748 return 0;
743} 749}
744 750
745static void mpic_shutdown_ht_irq(unsigned int irq) 751static void mpic_shutdown_ht_irq(struct irq_data *d)
746{ 752{
747 struct mpic *mpic = mpic_from_irq(irq); 753 struct mpic *mpic = mpic_from_irq_data(d);
748 unsigned int src = mpic_irq_to_hw(irq); 754 unsigned int src = mpic_irq_to_hw(d->irq);
749 755
750 mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(irq)->status); 756 mpic_shutdown_ht_interrupt(mpic, src, irq_to_desc(d->irq)->status);
751 mpic_mask_irq(irq); 757 mpic_mask_irq(d);
752} 758}
753 759
754static void mpic_end_ht_irq(unsigned int irq) 760static void mpic_end_ht_irq(struct irq_data *d)
755{ 761{
756 struct mpic *mpic = mpic_from_irq(irq); 762 struct mpic *mpic = mpic_from_irq_data(d);
757 unsigned int src = mpic_irq_to_hw(irq); 763 unsigned int src = mpic_irq_to_hw(d->irq);
758 764
759#ifdef DEBUG_IRQ 765#ifdef DEBUG_IRQ
760 DBG("%s: end_irq: %d\n", mpic->name, irq); 766 DBG("%s: end_irq: %d\n", mpic->name, d->irq);
761#endif 767#endif
762 /* We always EOI on end_irq() even for edge interrupts since that 768 /* We always EOI on end_irq() even for edge interrupts since that
763 * should only lower the priority, the MPIC should have properly 769 * should only lower the priority, the MPIC should have properly
764 * latched another edge interrupt coming in anyway 770 * latched another edge interrupt coming in anyway
765 */ 771 */
766 772
767 if (irq_to_desc(irq)->status & IRQ_LEVEL) 773 if (irq_to_desc(d->irq)->status & IRQ_LEVEL)
768 mpic_ht_end_irq(mpic, src); 774 mpic_ht_end_irq(mpic, src);
769 mpic_eoi(mpic); 775 mpic_eoi(mpic);
770} 776}
@@ -772,23 +778,23 @@ static void mpic_end_ht_irq(unsigned int irq)
772 778
773#ifdef CONFIG_SMP 779#ifdef CONFIG_SMP
774 780
775static void mpic_unmask_ipi(unsigned int irq) 781static void mpic_unmask_ipi(struct irq_data *d)
776{ 782{
777 struct mpic *mpic = mpic_from_ipi(irq); 783 struct mpic *mpic = mpic_from_ipi(d);
778 unsigned int src = mpic_irq_to_hw(irq) - mpic->ipi_vecs[0]; 784 unsigned int src = mpic_irq_to_hw(d->irq) - mpic->ipi_vecs[0];
779 785
780 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, irq, src); 786 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
781 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK); 787 mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
782} 788}
783 789
784static void mpic_mask_ipi(unsigned int irq) 790static void mpic_mask_ipi(struct irq_data *d)
785{ 791{
786 /* NEVER disable an IPI... that's just plain wrong! */ 792 /* NEVER disable an IPI... that's just plain wrong! */
787} 793}
788 794
789static void mpic_end_ipi(unsigned int irq) 795static void mpic_end_ipi(struct irq_data *d)
790{ 796{
791 struct mpic *mpic = mpic_from_ipi(irq); 797 struct mpic *mpic = mpic_from_ipi(d);
792 798
793 /* 799 /*
794 * IPIs are marked IRQ_PER_CPU. This has the side effect of 800 * IPIs are marked IRQ_PER_CPU. This has the side effect of
@@ -802,10 +808,11 @@ static void mpic_end_ipi(unsigned int irq)
802 808
803#endif /* CONFIG_SMP */ 809#endif /* CONFIG_SMP */
804 810
805int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask) 811int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
812 bool force)
806{ 813{
807 struct mpic *mpic = mpic_from_irq(irq); 814 struct mpic *mpic = mpic_from_irq_data(d);
808 unsigned int src = mpic_irq_to_hw(irq); 815 unsigned int src = mpic_irq_to_hw(d->irq);
809 816
810 if (mpic->flags & MPIC_SINGLE_DEST_CPU) { 817 if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
811 int cpuid = irq_choose_cpu(cpumask); 818 int cpuid = irq_choose_cpu(cpumask);
@@ -848,15 +855,15 @@ static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
848 } 855 }
849} 856}
850 857
851int mpic_set_irq_type(unsigned int virq, unsigned int flow_type) 858int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
852{ 859{
853 struct mpic *mpic = mpic_from_irq(virq); 860 struct mpic *mpic = mpic_from_irq_data(d);
854 unsigned int src = mpic_irq_to_hw(virq); 861 unsigned int src = mpic_irq_to_hw(d->irq);
855 struct irq_desc *desc = irq_to_desc(virq); 862 struct irq_desc *desc = irq_to_desc(d->irq);
856 unsigned int vecpri, vold, vnew; 863 unsigned int vecpri, vold, vnew;
857 864
858 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n", 865 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
859 mpic, virq, src, flow_type); 866 mpic, d->irq, src, flow_type);
860 867
861 if (src >= mpic->irq_count) 868 if (src >= mpic->irq_count)
862 return -EINVAL; 869 return -EINVAL;
@@ -907,28 +914,28 @@ void mpic_set_vector(unsigned int virq, unsigned int vector)
907} 914}
908 915
909static struct irq_chip mpic_irq_chip = { 916static struct irq_chip mpic_irq_chip = {
910 .mask = mpic_mask_irq, 917 .irq_mask = mpic_mask_irq,
911 .unmask = mpic_unmask_irq, 918 .irq_unmask = mpic_unmask_irq,
912 .eoi = mpic_end_irq, 919 .irq_eoi = mpic_end_irq,
913 .set_type = mpic_set_irq_type, 920 .irq_set_type = mpic_set_irq_type,
914}; 921};
915 922
916#ifdef CONFIG_SMP 923#ifdef CONFIG_SMP
917static struct irq_chip mpic_ipi_chip = { 924static struct irq_chip mpic_ipi_chip = {
918 .mask = mpic_mask_ipi, 925 .irq_mask = mpic_mask_ipi,
919 .unmask = mpic_unmask_ipi, 926 .irq_unmask = mpic_unmask_ipi,
920 .eoi = mpic_end_ipi, 927 .irq_eoi = mpic_end_ipi,
921}; 928};
922#endif /* CONFIG_SMP */ 929#endif /* CONFIG_SMP */
923 930
924#ifdef CONFIG_MPIC_U3_HT_IRQS 931#ifdef CONFIG_MPIC_U3_HT_IRQS
925static struct irq_chip mpic_irq_ht_chip = { 932static struct irq_chip mpic_irq_ht_chip = {
926 .startup = mpic_startup_ht_irq, 933 .irq_startup = mpic_startup_ht_irq,
927 .shutdown = mpic_shutdown_ht_irq, 934 .irq_shutdown = mpic_shutdown_ht_irq,
928 .mask = mpic_mask_irq, 935 .irq_mask = mpic_mask_irq,
929 .unmask = mpic_unmask_ht_irq, 936 .irq_unmask = mpic_unmask_ht_irq,
930 .eoi = mpic_end_ht_irq, 937 .irq_eoi = mpic_end_ht_irq,
931 .set_type = mpic_set_irq_type, 938 .irq_set_type = mpic_set_irq_type,
932}; 939};
933#endif /* CONFIG_MPIC_U3_HT_IRQS */ 940#endif /* CONFIG_MPIC_U3_HT_IRQS */
934 941
@@ -1060,12 +1067,12 @@ struct mpic * __init mpic_alloc(struct device_node *node,
1060 mpic->hc_irq = mpic_irq_chip; 1067 mpic->hc_irq = mpic_irq_chip;
1061 mpic->hc_irq.name = name; 1068 mpic->hc_irq.name = name;
1062 if (flags & MPIC_PRIMARY) 1069 if (flags & MPIC_PRIMARY)
1063 mpic->hc_irq.set_affinity = mpic_set_affinity; 1070 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1064#ifdef CONFIG_MPIC_U3_HT_IRQS 1071#ifdef CONFIG_MPIC_U3_HT_IRQS
1065 mpic->hc_ht_irq = mpic_irq_ht_chip; 1072 mpic->hc_ht_irq = mpic_irq_ht_chip;
1066 mpic->hc_ht_irq.name = name; 1073 mpic->hc_ht_irq.name = name;
1067 if (flags & MPIC_PRIMARY) 1074 if (flags & MPIC_PRIMARY)
1068 mpic->hc_ht_irq.set_affinity = mpic_set_affinity; 1075 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1069#endif /* CONFIG_MPIC_U3_HT_IRQS */ 1076#endif /* CONFIG_MPIC_U3_HT_IRQS */
1070 1077
1071#ifdef CONFIG_SMP 1078#ifdef CONFIG_SMP
diff --git a/arch/powerpc/sysdev/mpic.h b/arch/powerpc/sysdev/mpic.h
index e4a6df77b8d7..13f3e8913a93 100644
--- a/arch/powerpc/sysdev/mpic.h
+++ b/arch/powerpc/sysdev/mpic.h
@@ -34,9 +34,10 @@ static inline int mpic_pasemi_msi_init(struct mpic *mpic)
34} 34}
35#endif 35#endif
36 36
37extern int mpic_set_irq_type(unsigned int virq, unsigned int flow_type); 37extern int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type);
38extern void mpic_set_vector(unsigned int virq, unsigned int vector); 38extern void mpic_set_vector(unsigned int virq, unsigned int vector);
39extern int mpic_set_affinity(unsigned int irq, const struct cpumask *cpumask); 39extern int mpic_set_affinity(struct irq_data *d,
40 const struct cpumask *cpumask, bool force);
40extern void mpic_reset_core(int cpu); 41extern void mpic_reset_core(int cpu);
41 42
42#endif /* _POWERPC_SYSDEV_MPIC_H */ 43#endif /* _POWERPC_SYSDEV_MPIC_H */
diff --git a/arch/powerpc/sysdev/mpic_pasemi_msi.c b/arch/powerpc/sysdev/mpic_pasemi_msi.c
index 320ad5a9a25d..0b7794acfce1 100644
--- a/arch/powerpc/sysdev/mpic_pasemi_msi.c
+++ b/arch/powerpc/sysdev/mpic_pasemi_msi.c
@@ -43,24 +43,24 @@ static void mpic_pasemi_msi_mask_irq(struct irq_data *data)
43{ 43{
44 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq); 44 pr_debug("mpic_pasemi_msi_mask_irq %d\n", data->irq);
45 mask_msi_irq(data); 45 mask_msi_irq(data);
46 mpic_mask_irq(data->irq); 46 mpic_mask_irq(data);
47} 47}
48 48
49static void mpic_pasemi_msi_unmask_irq(struct irq_data *data) 49static void mpic_pasemi_msi_unmask_irq(struct irq_data *data)
50{ 50{
51 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq); 51 pr_debug("mpic_pasemi_msi_unmask_irq %d\n", data->irq);
52 mpic_unmask_irq(data->irq); 52 mpic_unmask_irq(data);
53 unmask_msi_irq(data); 53 unmask_msi_irq(data);
54} 54}
55 55
56static struct irq_chip mpic_pasemi_msi_chip = { 56static struct irq_chip mpic_pasemi_msi_chip = {
57 .irq_shutdown = mpic_pasemi_msi_mask_irq, 57 .irq_shutdown = mpic_pasemi_msi_mask_irq,
58 .irq_mask = mpic_pasemi_msi_mask_irq, 58 .irq_mask = mpic_pasemi_msi_mask_irq,
59 .irq_unmask = mpic_pasemi_msi_unmask_irq, 59 .irq_unmask = mpic_pasemi_msi_unmask_irq,
60 .eoi = mpic_end_irq, 60 .irq_eoi = mpic_end_irq,
61 .set_type = mpic_set_irq_type, 61 .irq_set_type = mpic_set_irq_type,
62 .set_affinity = mpic_set_affinity, 62 .irq_set_affinity = mpic_set_affinity,
63 .name = "PASEMI-MSI", 63 .name = "PASEMI-MSI",
64}; 64};
65 65
66static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type) 66static int pasemi_msi_check_device(struct pci_dev *pdev, int nvec, int type)
diff --git a/arch/powerpc/sysdev/mpic_u3msi.c b/arch/powerpc/sysdev/mpic_u3msi.c
index a2b028b4a202..71900ac78270 100644
--- a/arch/powerpc/sysdev/mpic_u3msi.c
+++ b/arch/powerpc/sysdev/mpic_u3msi.c
@@ -26,23 +26,23 @@ static struct mpic *msi_mpic;
26static void mpic_u3msi_mask_irq(struct irq_data *data) 26static void mpic_u3msi_mask_irq(struct irq_data *data)
27{ 27{
28 mask_msi_irq(data); 28 mask_msi_irq(data);
29 mpic_mask_irq(data->irq); 29 mpic_mask_irq(data);
30} 30}
31 31
32static void mpic_u3msi_unmask_irq(struct irq_data *data) 32static void mpic_u3msi_unmask_irq(struct irq_data *data)
33{ 33{
34 mpic_unmask_irq(data->irq); 34 mpic_unmask_irq(data);
35 unmask_msi_irq(data); 35 unmask_msi_irq(data);
36} 36}
37 37
38static struct irq_chip mpic_u3msi_chip = { 38static struct irq_chip mpic_u3msi_chip = {
39 .irq_shutdown = mpic_u3msi_mask_irq, 39 .irq_shutdown = mpic_u3msi_mask_irq,
40 .irq_mask = mpic_u3msi_mask_irq, 40 .irq_mask = mpic_u3msi_mask_irq,
41 .irq_unmask = mpic_u3msi_unmask_irq, 41 .irq_unmask = mpic_u3msi_unmask_irq,
42 .eoi = mpic_end_irq, 42 .irq_eoi = mpic_end_irq,
43 .set_type = mpic_set_irq_type, 43 .irq_set_type = mpic_set_irq_type,
44 .set_affinity = mpic_set_affinity, 44 .irq_set_affinity = mpic_set_affinity,
45 .name = "MPIC-U3MSI", 45 .name = "MPIC-U3MSI",
46}; 46};
47 47
48static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos) 48static u64 read_ht_magic_addr(struct pci_dev *pdev, unsigned int pos)
diff --git a/arch/powerpc/sysdev/mv64x60_dev.c b/arch/powerpc/sysdev/mv64x60_dev.c
index feaee402e2d6..0f6af41ebb44 100644
--- a/arch/powerpc/sysdev/mv64x60_dev.c
+++ b/arch/powerpc/sysdev/mv64x60_dev.c
@@ -346,7 +346,7 @@ static int __init mv64x60_i2c_device_setup(struct device_node *np, int id)
346 if (prop) 346 if (prop)
347 pdata.freq_m = *prop; 347 pdata.freq_m = *prop;
348 348
349 pdata.freq_m = 3; /* default */ 349 pdata.freq_n = 3; /* default */
350 prop = of_get_property(np, "freq_n", NULL); 350 prop = of_get_property(np, "freq_n", NULL);
351 if (prop) 351 if (prop)
352 pdata.freq_n = *prop; 352 pdata.freq_n = *prop;
diff --git a/arch/powerpc/sysdev/mv64x60_pic.c b/arch/powerpc/sysdev/mv64x60_pic.c
index 485b92477d7c..bc61ebb8987c 100644
--- a/arch/powerpc/sysdev/mv64x60_pic.c
+++ b/arch/powerpc/sysdev/mv64x60_pic.c
@@ -76,9 +76,9 @@ static struct irq_host *mv64x60_irq_host;
76 * mv64x60_chip_low functions 76 * mv64x60_chip_low functions
77 */ 77 */
78 78
79static void mv64x60_mask_low(unsigned int virq) 79static void mv64x60_mask_low(struct irq_data *d)
80{ 80{
81 int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 81 int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK;
82 unsigned long flags; 82 unsigned long flags;
83 83
84 spin_lock_irqsave(&mv64x60_lock, flags); 84 spin_lock_irqsave(&mv64x60_lock, flags);
@@ -89,9 +89,9 @@ static void mv64x60_mask_low(unsigned int virq)
89 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO); 89 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_LO);
90} 90}
91 91
92static void mv64x60_unmask_low(unsigned int virq) 92static void mv64x60_unmask_low(struct irq_data *d)
93{ 93{
94 int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 94 int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK;
95 unsigned long flags; 95 unsigned long flags;
96 96
97 spin_lock_irqsave(&mv64x60_lock, flags); 97 spin_lock_irqsave(&mv64x60_lock, flags);
@@ -104,18 +104,18 @@ static void mv64x60_unmask_low(unsigned int virq)
104 104
105static struct irq_chip mv64x60_chip_low = { 105static struct irq_chip mv64x60_chip_low = {
106 .name = "mv64x60_low", 106 .name = "mv64x60_low",
107 .mask = mv64x60_mask_low, 107 .irq_mask = mv64x60_mask_low,
108 .mask_ack = mv64x60_mask_low, 108 .irq_mask_ack = mv64x60_mask_low,
109 .unmask = mv64x60_unmask_low, 109 .irq_unmask = mv64x60_unmask_low,
110}; 110};
111 111
112/* 112/*
113 * mv64x60_chip_high functions 113 * mv64x60_chip_high functions
114 */ 114 */
115 115
116static void mv64x60_mask_high(unsigned int virq) 116static void mv64x60_mask_high(struct irq_data *d)
117{ 117{
118 int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 118 int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK;
119 unsigned long flags; 119 unsigned long flags;
120 120
121 spin_lock_irqsave(&mv64x60_lock, flags); 121 spin_lock_irqsave(&mv64x60_lock, flags);
@@ -126,9 +126,9 @@ static void mv64x60_mask_high(unsigned int virq)
126 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI); 126 (void)in_le32(mv64x60_irq_reg_base + MV64X60_IC_CPU0_INTR_MASK_HI);
127} 127}
128 128
129static void mv64x60_unmask_high(unsigned int virq) 129static void mv64x60_unmask_high(struct irq_data *d)
130{ 130{
131 int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 131 int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK;
132 unsigned long flags; 132 unsigned long flags;
133 133
134 spin_lock_irqsave(&mv64x60_lock, flags); 134 spin_lock_irqsave(&mv64x60_lock, flags);
@@ -141,18 +141,18 @@ static void mv64x60_unmask_high(unsigned int virq)
141 141
142static struct irq_chip mv64x60_chip_high = { 142static struct irq_chip mv64x60_chip_high = {
143 .name = "mv64x60_high", 143 .name = "mv64x60_high",
144 .mask = mv64x60_mask_high, 144 .irq_mask = mv64x60_mask_high,
145 .mask_ack = mv64x60_mask_high, 145 .irq_mask_ack = mv64x60_mask_high,
146 .unmask = mv64x60_unmask_high, 146 .irq_unmask = mv64x60_unmask_high,
147}; 147};
148 148
149/* 149/*
150 * mv64x60_chip_gpp functions 150 * mv64x60_chip_gpp functions
151 */ 151 */
152 152
153static void mv64x60_mask_gpp(unsigned int virq) 153static void mv64x60_mask_gpp(struct irq_data *d)
154{ 154{
155 int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 155 int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK;
156 unsigned long flags; 156 unsigned long flags;
157 157
158 spin_lock_irqsave(&mv64x60_lock, flags); 158 spin_lock_irqsave(&mv64x60_lock, flags);
@@ -163,9 +163,9 @@ static void mv64x60_mask_gpp(unsigned int virq)
163 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK); 163 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_MASK);
164} 164}
165 165
166static void mv64x60_mask_ack_gpp(unsigned int virq) 166static void mv64x60_mask_ack_gpp(struct irq_data *d)
167{ 167{
168 int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 168 int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK;
169 unsigned long flags; 169 unsigned long flags;
170 170
171 spin_lock_irqsave(&mv64x60_lock, flags); 171 spin_lock_irqsave(&mv64x60_lock, flags);
@@ -178,9 +178,9 @@ static void mv64x60_mask_ack_gpp(unsigned int virq)
178 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE); 178 (void)in_le32(mv64x60_gpp_reg_base + MV64x60_GPP_INTR_CAUSE);
179} 179}
180 180
181static void mv64x60_unmask_gpp(unsigned int virq) 181static void mv64x60_unmask_gpp(struct irq_data *d)
182{ 182{
183 int level2 = irq_map[virq].hwirq & MV64x60_LEVEL2_MASK; 183 int level2 = irq_map[d->irq].hwirq & MV64x60_LEVEL2_MASK;
184 unsigned long flags; 184 unsigned long flags;
185 185
186 spin_lock_irqsave(&mv64x60_lock, flags); 186 spin_lock_irqsave(&mv64x60_lock, flags);
@@ -193,9 +193,9 @@ static void mv64x60_unmask_gpp(unsigned int virq)
193 193
194static struct irq_chip mv64x60_chip_gpp = { 194static struct irq_chip mv64x60_chip_gpp = {
195 .name = "mv64x60_gpp", 195 .name = "mv64x60_gpp",
196 .mask = mv64x60_mask_gpp, 196 .irq_mask = mv64x60_mask_gpp,
197 .mask_ack = mv64x60_mask_ack_gpp, 197 .irq_mask_ack = mv64x60_mask_ack_gpp,
198 .unmask = mv64x60_unmask_gpp, 198 .irq_unmask = mv64x60_unmask_gpp,
199}; 199};
200 200
201/* 201/*
diff --git a/arch/powerpc/sysdev/qe_lib/qe_ic.c b/arch/powerpc/sysdev/qe_lib/qe_ic.c
index 541ba9863647..8c9ded8ea07c 100644
--- a/arch/powerpc/sysdev/qe_lib/qe_ic.c
+++ b/arch/powerpc/sysdev/qe_lib/qe_ic.c
@@ -189,15 +189,20 @@ static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg
189 189
190static inline struct qe_ic *qe_ic_from_irq(unsigned int virq) 190static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
191{ 191{
192 return irq_to_desc(virq)->chip_data; 192 return get_irq_chip_data(virq);
193}
194
195static inline struct qe_ic *qe_ic_from_irq_data(struct irq_data *d)
196{
197 return irq_data_get_irq_chip_data(d);
193} 198}
194 199
195#define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq) 200#define virq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
196 201
197static void qe_ic_unmask_irq(unsigned int virq) 202static void qe_ic_unmask_irq(struct irq_data *d)
198{ 203{
199 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 204 struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
200 unsigned int src = virq_to_hw(virq); 205 unsigned int src = virq_to_hw(d->irq);
201 unsigned long flags; 206 unsigned long flags;
202 u32 temp; 207 u32 temp;
203 208
@@ -210,10 +215,10 @@ static void qe_ic_unmask_irq(unsigned int virq)
210 raw_spin_unlock_irqrestore(&qe_ic_lock, flags); 215 raw_spin_unlock_irqrestore(&qe_ic_lock, flags);
211} 216}
212 217
213static void qe_ic_mask_irq(unsigned int virq) 218static void qe_ic_mask_irq(struct irq_data *d)
214{ 219{
215 struct qe_ic *qe_ic = qe_ic_from_irq(virq); 220 struct qe_ic *qe_ic = qe_ic_from_irq_data(d);
216 unsigned int src = virq_to_hw(virq); 221 unsigned int src = virq_to_hw(d->irq);
217 unsigned long flags; 222 unsigned long flags;
218 u32 temp; 223 u32 temp;
219 224
@@ -238,9 +243,9 @@ static void qe_ic_mask_irq(unsigned int virq)
238 243
239static struct irq_chip qe_ic_irq_chip = { 244static struct irq_chip qe_ic_irq_chip = {
240 .name = "QEIC", 245 .name = "QEIC",
241 .unmask = qe_ic_unmask_irq, 246 .irq_unmask = qe_ic_unmask_irq,
242 .mask = qe_ic_mask_irq, 247 .irq_mask = qe_ic_mask_irq,
243 .mask_ack = qe_ic_mask_irq, 248 .irq_mask_ack = qe_ic_mask_irq,
244}; 249};
245 250
246static int qe_ic_host_match(struct irq_host *h, struct device_node *node) 251static int qe_ic_host_match(struct irq_host *h, struct device_node *node)
diff --git a/arch/powerpc/sysdev/tsi108_pci.c b/arch/powerpc/sysdev/tsi108_pci.c
index 0ab9281e49ae..02c91db90037 100644
--- a/arch/powerpc/sysdev/tsi108_pci.c
+++ b/arch/powerpc/sysdev/tsi108_pci.c
@@ -343,24 +343,9 @@ static inline unsigned int get_pci_source(void)
343 * Linux descriptor level callbacks 343 * Linux descriptor level callbacks
344 */ 344 */
345 345
346static void tsi108_pci_irq_enable(u_int irq) 346static void tsi108_pci_irq_unmask(struct irq_data *d)
347{ 347{
348 tsi108_pci_int_unmask(irq); 348 tsi108_pci_int_unmask(d->irq);
349}
350
351static void tsi108_pci_irq_disable(u_int irq)
352{
353 tsi108_pci_int_mask(irq);
354}
355
356static void tsi108_pci_irq_ack(u_int irq)
357{
358 tsi108_pci_int_mask(irq);
359}
360
361static void tsi108_pci_irq_end(u_int irq)
362{
363 tsi108_pci_int_unmask(irq);
364 349
365 /* Enable interrupts from PCI block */ 350 /* Enable interrupts from PCI block */
366 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE, 351 tsi108_write_reg(TSI108_PCI_OFFSET + TSI108_PCI_IRP_ENABLE,
@@ -370,16 +355,25 @@ static void tsi108_pci_irq_end(u_int irq)
370 mb(); 355 mb();
371} 356}
372 357
358static void tsi108_pci_irq_mask(struct irq_data *d)
359{
360 tsi108_pci_int_mask(d->irq);
361}
362
363static void tsi108_pci_irq_ack(struct irq_data *d)
364{
365 tsi108_pci_int_mask(d->irq);
366}
367
373/* 368/*
374 * Interrupt controller descriptor for cascaded PCI interrupt controller. 369 * Interrupt controller descriptor for cascaded PCI interrupt controller.
375 */ 370 */
376 371
377static struct irq_chip tsi108_pci_irq = { 372static struct irq_chip tsi108_pci_irq = {
378 .name = "tsi108_PCI_int", 373 .name = "tsi108_PCI_int",
379 .mask = tsi108_pci_irq_disable, 374 .irq_mask = tsi108_pci_irq_mask,
380 .ack = tsi108_pci_irq_ack, 375 .irq_ack = tsi108_pci_irq_ack,
381 .end = tsi108_pci_irq_end, 376 .irq_unmask = tsi108_pci_irq_unmask,
382 .unmask = tsi108_pci_irq_enable,
383}; 377};
384 378
385static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct, 379static int pci_irq_host_xlate(struct irq_host *h, struct device_node *ct,
@@ -437,8 +431,11 @@ void __init tsi108_pci_int_init(struct device_node *node)
437 431
438void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc) 432void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc)
439{ 433{
434 struct irq_chip *chip = get_irq_desc_chip(desc);
440 unsigned int cascade_irq = get_pci_source(); 435 unsigned int cascade_irq = get_pci_source();
436
441 if (cascade_irq != NO_IRQ) 437 if (cascade_irq != NO_IRQ)
442 generic_handle_irq(cascade_irq); 438 generic_handle_irq(cascade_irq);
443 desc->chip->eoi(irq); 439
440 chip->irq_eoi(&desc->irq_data);
444} 441}
diff --git a/arch/powerpc/sysdev/uic.c b/arch/powerpc/sysdev/uic.c
index 0038fb78f094..835f7958b237 100644
--- a/arch/powerpc/sysdev/uic.c
+++ b/arch/powerpc/sysdev/uic.c
@@ -55,11 +55,11 @@ struct uic {
55 struct irq_host *irqhost; 55 struct irq_host *irqhost;
56}; 56};
57 57
58static void uic_unmask_irq(unsigned int virq) 58static void uic_unmask_irq(struct irq_data *d)
59{ 59{
60 struct irq_desc *desc = irq_to_desc(virq); 60 struct irq_desc *desc = irq_to_desc(d->irq);
61 struct uic *uic = get_irq_chip_data(virq); 61 struct uic *uic = irq_data_get_irq_chip_data(d);
62 unsigned int src = uic_irq_to_hw(virq); 62 unsigned int src = uic_irq_to_hw(d->irq);
63 unsigned long flags; 63 unsigned long flags;
64 u32 er, sr; 64 u32 er, sr;
65 65
@@ -74,10 +74,10 @@ static void uic_unmask_irq(unsigned int virq)
74 spin_unlock_irqrestore(&uic->lock, flags); 74 spin_unlock_irqrestore(&uic->lock, flags);
75} 75}
76 76
77static void uic_mask_irq(unsigned int virq) 77static void uic_mask_irq(struct irq_data *d)
78{ 78{
79 struct uic *uic = get_irq_chip_data(virq); 79 struct uic *uic = irq_data_get_irq_chip_data(d);
80 unsigned int src = uic_irq_to_hw(virq); 80 unsigned int src = uic_irq_to_hw(d->irq);
81 unsigned long flags; 81 unsigned long flags;
82 u32 er; 82 u32 er;
83 83
@@ -88,10 +88,10 @@ static void uic_mask_irq(unsigned int virq)
88 spin_unlock_irqrestore(&uic->lock, flags); 88 spin_unlock_irqrestore(&uic->lock, flags);
89} 89}
90 90
91static void uic_ack_irq(unsigned int virq) 91static void uic_ack_irq(struct irq_data *d)
92{ 92{
93 struct uic *uic = get_irq_chip_data(virq); 93 struct uic *uic = irq_data_get_irq_chip_data(d);
94 unsigned int src = uic_irq_to_hw(virq); 94 unsigned int src = uic_irq_to_hw(d->irq);
95 unsigned long flags; 95 unsigned long flags;
96 96
97 spin_lock_irqsave(&uic->lock, flags); 97 spin_lock_irqsave(&uic->lock, flags);
@@ -99,11 +99,11 @@ static void uic_ack_irq(unsigned int virq)
99 spin_unlock_irqrestore(&uic->lock, flags); 99 spin_unlock_irqrestore(&uic->lock, flags);
100} 100}
101 101
102static void uic_mask_ack_irq(unsigned int virq) 102static void uic_mask_ack_irq(struct irq_data *d)
103{ 103{
104 struct irq_desc *desc = irq_to_desc(virq); 104 struct irq_desc *desc = irq_to_desc(d->irq);
105 struct uic *uic = get_irq_chip_data(virq); 105 struct uic *uic = irq_data_get_irq_chip_data(d);
106 unsigned int src = uic_irq_to_hw(virq); 106 unsigned int src = uic_irq_to_hw(d->irq);
107 unsigned long flags; 107 unsigned long flags;
108 u32 er, sr; 108 u32 er, sr;
109 109
@@ -125,18 +125,18 @@ static void uic_mask_ack_irq(unsigned int virq)
125 spin_unlock_irqrestore(&uic->lock, flags); 125 spin_unlock_irqrestore(&uic->lock, flags);
126} 126}
127 127
128static int uic_set_irq_type(unsigned int virq, unsigned int flow_type) 128static int uic_set_irq_type(struct irq_data *d, unsigned int flow_type)
129{ 129{
130 struct uic *uic = get_irq_chip_data(virq); 130 struct uic *uic = irq_data_get_irq_chip_data(d);
131 unsigned int src = uic_irq_to_hw(virq); 131 unsigned int src = uic_irq_to_hw(d->irq);
132 struct irq_desc *desc = irq_to_desc(virq); 132 struct irq_desc *desc = irq_to_desc(d->irq);
133 unsigned long flags; 133 unsigned long flags;
134 int trigger, polarity; 134 int trigger, polarity;
135 u32 tr, pr, mask; 135 u32 tr, pr, mask;
136 136
137 switch (flow_type & IRQ_TYPE_SENSE_MASK) { 137 switch (flow_type & IRQ_TYPE_SENSE_MASK) {
138 case IRQ_TYPE_NONE: 138 case IRQ_TYPE_NONE:
139 uic_mask_irq(virq); 139 uic_mask_irq(d);
140 return 0; 140 return 0;
141 141
142 case IRQ_TYPE_EDGE_RISING: 142 case IRQ_TYPE_EDGE_RISING:
@@ -178,11 +178,11 @@ static int uic_set_irq_type(unsigned int virq, unsigned int flow_type)
178 178
179static struct irq_chip uic_irq_chip = { 179static struct irq_chip uic_irq_chip = {
180 .name = "UIC", 180 .name = "UIC",
181 .unmask = uic_unmask_irq, 181 .irq_unmask = uic_unmask_irq,
182 .mask = uic_mask_irq, 182 .irq_mask = uic_mask_irq,
183 .mask_ack = uic_mask_ack_irq, 183 .irq_mask_ack = uic_mask_ack_irq,
184 .ack = uic_ack_irq, 184 .irq_ack = uic_ack_irq,
185 .set_type = uic_set_irq_type, 185 .irq_set_type = uic_set_irq_type,
186}; 186};
187 187
188static int uic_host_map(struct irq_host *h, unsigned int virq, 188static int uic_host_map(struct irq_host *h, unsigned int virq,
@@ -220,6 +220,7 @@ static struct irq_host_ops uic_host_ops = {
220 220
221void uic_irq_cascade(unsigned int virq, struct irq_desc *desc) 221void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
222{ 222{
223 struct irq_chip *chip = get_irq_desc_chip(desc);
223 struct uic *uic = get_irq_data(virq); 224 struct uic *uic = get_irq_data(virq);
224 u32 msr; 225 u32 msr;
225 int src; 226 int src;
@@ -227,9 +228,9 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
227 228
228 raw_spin_lock(&desc->lock); 229 raw_spin_lock(&desc->lock);
229 if (desc->status & IRQ_LEVEL) 230 if (desc->status & IRQ_LEVEL)
230 desc->chip->mask(virq); 231 chip->irq_mask(&desc->irq_data);
231 else 232 else
232 desc->chip->mask_ack(virq); 233 chip->irq_mask_ack(&desc->irq_data);
233 raw_spin_unlock(&desc->lock); 234 raw_spin_unlock(&desc->lock);
234 235
235 msr = mfdcr(uic->dcrbase + UIC_MSR); 236 msr = mfdcr(uic->dcrbase + UIC_MSR);
@@ -244,9 +245,9 @@ void uic_irq_cascade(unsigned int virq, struct irq_desc *desc)
244uic_irq_ret: 245uic_irq_ret:
245 raw_spin_lock(&desc->lock); 246 raw_spin_lock(&desc->lock);
246 if (desc->status & IRQ_LEVEL) 247 if (desc->status & IRQ_LEVEL)
247 desc->chip->ack(virq); 248 chip->irq_ack(&desc->irq_data);
248 if (!(desc->status & IRQ_DISABLED) && desc->chip->unmask) 249 if (!(desc->status & IRQ_DISABLED) && chip->irq_unmask)
249 desc->chip->unmask(virq); 250 chip->irq_unmask(&desc->irq_data);
250 raw_spin_unlock(&desc->lock); 251 raw_spin_unlock(&desc->lock);
251} 252}
252 253
diff --git a/arch/powerpc/sysdev/xilinx_intc.c b/arch/powerpc/sysdev/xilinx_intc.c
index 1e0ccfaf403e..7436f3ed4df6 100644
--- a/arch/powerpc/sysdev/xilinx_intc.c
+++ b/arch/powerpc/sysdev/xilinx_intc.c
@@ -69,17 +69,17 @@ static unsigned char xilinx_intc_map_senses[] = {
69 * 69 *
70 * IRQ Chip common (across level and edge) operations 70 * IRQ Chip common (across level and edge) operations
71 */ 71 */
72static void xilinx_intc_mask(unsigned int virq) 72static void xilinx_intc_mask(struct irq_data *d)
73{ 73{
74 int irq = virq_to_hw(virq); 74 int irq = virq_to_hw(d->irq);
75 void * regs = get_irq_chip_data(virq); 75 void * regs = irq_data_get_irq_chip_data(d);
76 pr_debug("mask: %d\n", irq); 76 pr_debug("mask: %d\n", irq);
77 out_be32(regs + XINTC_CIE, 1 << irq); 77 out_be32(regs + XINTC_CIE, 1 << irq);
78} 78}
79 79
80static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type) 80static int xilinx_intc_set_type(struct irq_data *d, unsigned int flow_type)
81{ 81{
82 struct irq_desc *desc = irq_to_desc(virq); 82 struct irq_desc *desc = irq_to_desc(d->irq);
83 83
84 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL); 84 desc->status &= ~(IRQ_TYPE_SENSE_MASK | IRQ_LEVEL);
85 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK; 85 desc->status |= flow_type & IRQ_TYPE_SENSE_MASK;
@@ -91,10 +91,10 @@ static int xilinx_intc_set_type(unsigned int virq, unsigned int flow_type)
91/* 91/*
92 * IRQ Chip level operations 92 * IRQ Chip level operations
93 */ 93 */
94static void xilinx_intc_level_unmask(unsigned int virq) 94static void xilinx_intc_level_unmask(struct irq_data *d)
95{ 95{
96 int irq = virq_to_hw(virq); 96 int irq = virq_to_hw(d->irq);
97 void * regs = get_irq_chip_data(virq); 97 void * regs = irq_data_get_irq_chip_data(d);
98 pr_debug("unmask: %d\n", irq); 98 pr_debug("unmask: %d\n", irq);
99 out_be32(regs + XINTC_SIE, 1 << irq); 99 out_be32(regs + XINTC_SIE, 1 << irq);
100 100
@@ -107,37 +107,37 @@ static void xilinx_intc_level_unmask(unsigned int virq)
107 107
108static struct irq_chip xilinx_intc_level_irqchip = { 108static struct irq_chip xilinx_intc_level_irqchip = {
109 .name = "Xilinx Level INTC", 109 .name = "Xilinx Level INTC",
110 .mask = xilinx_intc_mask, 110 .irq_mask = xilinx_intc_mask,
111 .mask_ack = xilinx_intc_mask, 111 .irq_mask_ack = xilinx_intc_mask,
112 .unmask = xilinx_intc_level_unmask, 112 .irq_unmask = xilinx_intc_level_unmask,
113 .set_type = xilinx_intc_set_type, 113 .irq_set_type = xilinx_intc_set_type,
114}; 114};
115 115
116/* 116/*
117 * IRQ Chip edge operations 117 * IRQ Chip edge operations
118 */ 118 */
119static void xilinx_intc_edge_unmask(unsigned int virq) 119static void xilinx_intc_edge_unmask(struct irq_data *d)
120{ 120{
121 int irq = virq_to_hw(virq); 121 int irq = virq_to_hw(d->irq);
122 void *regs = get_irq_chip_data(virq); 122 void *regs = irq_data_get_irq_chip_data(d);
123 pr_debug("unmask: %d\n", irq); 123 pr_debug("unmask: %d\n", irq);
124 out_be32(regs + XINTC_SIE, 1 << irq); 124 out_be32(regs + XINTC_SIE, 1 << irq);
125} 125}
126 126
127static void xilinx_intc_edge_ack(unsigned int virq) 127static void xilinx_intc_edge_ack(struct irq_data *d)
128{ 128{
129 int irq = virq_to_hw(virq); 129 int irq = virq_to_hw(d->irq);
130 void * regs = get_irq_chip_data(virq); 130 void * regs = irq_data_get_irq_chip_data(d);
131 pr_debug("ack: %d\n", irq); 131 pr_debug("ack: %d\n", irq);
132 out_be32(regs + XINTC_IAR, 1 << irq); 132 out_be32(regs + XINTC_IAR, 1 << irq);
133} 133}
134 134
135static struct irq_chip xilinx_intc_edge_irqchip = { 135static struct irq_chip xilinx_intc_edge_irqchip = {
136 .name = "Xilinx Edge INTC", 136 .name = "Xilinx Edge INTC",
137 .mask = xilinx_intc_mask, 137 .irq_mask = xilinx_intc_mask,
138 .unmask = xilinx_intc_edge_unmask, 138 .irq_unmask = xilinx_intc_edge_unmask,
139 .ack = xilinx_intc_edge_ack, 139 .irq_ack = xilinx_intc_edge_ack,
140 .set_type = xilinx_intc_set_type, 140 .irq_set_type = xilinx_intc_set_type,
141}; 141};
142 142
143/* 143/*
@@ -229,12 +229,14 @@ int xilinx_intc_get_irq(void)
229 */ 229 */
230static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc) 230static void xilinx_i8259_cascade(unsigned int irq, struct irq_desc *desc)
231{ 231{
232 struct irq_chip *chip = get_irq_desc_chip(desc);
232 unsigned int cascade_irq = i8259_irq(); 233 unsigned int cascade_irq = i8259_irq();
234
233 if (cascade_irq) 235 if (cascade_irq)
234 generic_handle_irq(cascade_irq); 236 generic_handle_irq(cascade_irq);
235 237
236 /* Let xilinx_intc end the interrupt */ 238 /* Let xilinx_intc end the interrupt */
237 desc->chip->unmask(irq); 239 chip->irq_unmask(&desc->irq_data);
238} 240}
239 241
240static void __init xilinx_i8259_setup_cascade(void) 242static void __init xilinx_i8259_setup_cascade(void)
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-25 00:32:39 -0500