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-rw-r--r--arch/powerpc/perf/power9-pmu.c54
1 files changed, 1 insertions, 53 deletions
diff --git a/arch/powerpc/perf/power9-pmu.c b/arch/powerpc/perf/power9-pmu.c
index 2ca0b33b4efb..e012b1030a5b 100644
--- a/arch/powerpc/perf/power9-pmu.c
+++ b/arch/powerpc/perf/power9-pmu.c
@@ -219,12 +219,6 @@ static struct attribute_group power9_pmu_events_group = {
219 .attrs = power9_events_attr, 219 .attrs = power9_events_attr,
220}; 220};
221 221
222static const struct attribute_group *power9_isa207_pmu_attr_groups[] = {
223 &isa207_pmu_format_group,
224 &power9_pmu_events_group,
225 NULL,
226};
227
228PMU_FORMAT_ATTR(event, "config:0-51"); 222PMU_FORMAT_ATTR(event, "config:0-51");
229PMU_FORMAT_ATTR(pmcxsel, "config:0-7"); 223PMU_FORMAT_ATTR(pmcxsel, "config:0-7");
230PMU_FORMAT_ATTR(mark, "config:8"); 224PMU_FORMAT_ATTR(mark, "config:8");
@@ -267,17 +261,6 @@ static const struct attribute_group *power9_pmu_attr_groups[] = {
267 NULL, 261 NULL,
268}; 262};
269 263
270static int power9_generic_events_dd1[] = {
271 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
272 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
273 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = PM_CMPLU_STALL,
274 [PERF_COUNT_HW_INSTRUCTIONS] = PM_INST_DISP,
275 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = PM_BR_CMPL_ALT,
276 [PERF_COUNT_HW_BRANCH_MISSES] = PM_BR_MPRED_CMPL,
277 [PERF_COUNT_HW_CACHE_REFERENCES] = PM_LD_REF_L1,
278 [PERF_COUNT_HW_CACHE_MISSES] = PM_LD_MISS_L1_FIN,
279};
280
281static int power9_generic_events[] = { 264static int power9_generic_events[] = {
282 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC, 265 [PERF_COUNT_HW_CPU_CYCLES] = PM_CYC,
283 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC, 266 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = PM_ICT_NOSLOT_CYC,
@@ -439,25 +422,6 @@ static int power9_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
439 422
440#undef C 423#undef C
441 424
442static struct power_pmu power9_isa207_pmu = {
443 .name = "POWER9",
444 .n_counter = MAX_PMU_COUNTERS,
445 .add_fields = ISA207_ADD_FIELDS,
446 .test_adder = P9_DD1_TEST_ADDER,
447 .compute_mmcr = isa207_compute_mmcr,
448 .config_bhrb = power9_config_bhrb,
449 .bhrb_filter_map = power9_bhrb_filter_map,
450 .get_constraint = isa207_get_constraint,
451 .get_alternatives = power9_get_alternatives,
452 .disable_pmc = isa207_disable_pmc,
453 .flags = PPMU_NO_SIAR | PPMU_ARCH_207S,
454 .n_generic = ARRAY_SIZE(power9_generic_events_dd1),
455 .generic_events = power9_generic_events_dd1,
456 .cache_events = &power9_cache_events,
457 .attr_groups = power9_isa207_pmu_attr_groups,
458 .bhrb_nr = 32,
459};
460
461static struct power_pmu power9_pmu = { 425static struct power_pmu power9_pmu = {
462 .name = "POWER9", 426 .name = "POWER9",
463 .n_counter = MAX_PMU_COUNTERS, 427 .n_counter = MAX_PMU_COUNTERS,
@@ -500,23 +464,7 @@ static int __init init_power9_pmu(void)
500 } 464 }
501 } 465 }
502 466
503 if (cpu_has_feature(CPU_FTR_POWER9_DD1)) { 467 rc = register_power_pmu(&power9_pmu);
504 /*
505 * Since PM_INST_CMPL may not provide right counts in all
506 * sampling scenarios in power9 DD1, instead use PM_INST_DISP.
507 */
508 EVENT_VAR(PM_INST_CMPL, _g).id = PM_INST_DISP;
509 /*
510 * Power9 DD1 should use PM_BR_CMPL_ALT event code for
511 * "branches" to provide correct counter value.
512 */
513 EVENT_VAR(PM_BR_CMPL, _g).id = PM_BR_CMPL_ALT;
514 EVENT_VAR(PM_BR_CMPL, _c).id = PM_BR_CMPL_ALT;
515 rc = register_power_pmu(&power9_isa207_pmu);
516 } else {
517 rc = register_power_pmu(&power9_pmu);
518 }
519
520 if (rc) 468 if (rc)
521 return rc; 469 return rc;
522 470